Method of fabricating a semiconductor device

Abstract

The present invention relates to a method of fabricating a semiconductor device which reduces The leakage current by controlling an etch of a field oxide layer when a contact hole is formed. The present invention includes the steps of forming a in a semiconductor device is reduced. A field oxide layer defining an active area and a field area is formed on a semiconductor substrateof a first conductive type, forming a . A gate is formed on the an active area of the semiconductor substrate. by inserting a gate insulating layer between the semiconductor substrate and the gate, forming impurity regions of a second conductive type in the semiconductor are formed on the substrate in use of using the gate as a mask, forming a . A first insulating interlayer layer is formed on the semiconductor substrate by depositing an insulator of which having the heat expansion coefficient and lattice mismatch that are less than those of the semiconductor substrateto cover the field oxide layer and the gate, forming a . A second insulating interlayer layer is formed on the first insulating interlayer layer by depositing another insulator of which having an etch rate that is different from that of the first insulating interlayer, forming a layer. A third insulating interlayer layer is formed on the second insulating interlayer layer by depositing yet another insulator of which having an etch rate that is different from that of the second insulating interlayer, and forming a first contact hole layer. first and second contact holes exposing the gate and heavily doped regions respectively are formed by patterning the third to first insulating interlayer successively by photolithography layers.

Description

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a method of fabricating a semiconductor device which reduces leakage current by controlling an etch of a field oxide layer when a contact hole is formed.

2. Discussion of Related Art

As the integration of a semiconductor device increases, so the size of an unit transistor decreases. Thus, sizes of contact holes exposing impurity regions are reduced as well as the impurity regions for source and drain regions are decreased in size, causing difficulty in process. Besides, leakage current on the operation of the device is brought about by the etch of a field oxide layer due to misalignment in forming the contact holes.

Therefore, a technique of forming a borderless contact has been developed to reduce leakage current by forming the contact hole to be overlapped with a field oxide layer, which provides an easy process and prevents the etch of the field oxide layer.

FIG. 1A to FIG. 1D show cross-sectional views of fabricating a semiconductor device according to a related art.

Referring to FIG. 1A, a field oxide layer 13 defining an active area and a field area of a device is formed on a p-typed semiconductor substrate 11 by shallow trench isolation (hereinafter abbreviated STI). In this case, the field oxide layer 13 is formed by forming a pad oxide layer(not shown in the drawing) and a mask layer(not shown in the drawing) which expose the field area on the semiconductor substrate 11, by forming trenches 12 which are slant to a predetermined degree by carrying out an anisotropic etch such as reaction ion etching(hereinafter abbreviated RIE) and the like on the exposed parts of the semiconductor substrate 11, by filling the trenches with silicon oxide, then by removing the pad oxide and mask layers.

After a gate oxide layer 15 has been formed on the active area of the semiconductor substrate 11, polysilicon doped with impurities is deposited on the gate insulating layer 15 by chemical vapor deposition(hereinafter abbreviated CVD). Then, a gate 17 is formed by patterning the polysilicon to remain on a predetermined portion of the semiconductor substrate 11 by photolithography including anisotropic etches such as RME and the like.

Lightly doped regions 19 for LDD(lightly doped drain) regions are formed by implanting ions lightly into the exposed portions of the semiconductor substrate 11 with n typed impurities in use of the gate 17 as a mask.

Referring to FIG. 1B, a sidewall spacer 21 is formed at the sides of the gate 17. In this case, the sidewall spacer 21 is formed by deposing silicon oxide on the semiconductor substrate 11 to cover the field oxide layer 13 and gate 17 by CVD, then by etching back the silicon oxide to have the semiconductor substrate 11 exposed by RIE.

Heavily doped regions 23 for a source and a drain region are formed by implanting with n typed impurity ions heavily into the exposed portions of the semiconductor substrate 11 in use of the gate 17 and sidewall spacer 21 as a mask.

Referring to FIG. 1C, a first insulating Tointerlayerof in the method of fabricating a semiconductor device of according to the present invention, a first insulating layer made of silicon oxide of which heat expansion coefficient and lattice mismatch are less than those of silicon nitride is formed on a semiconductor substrate, and a second insulating interlayer layer made of silicon nitride used as an etch-stop layer and a third insulating interlayer layer made of silicon oxide are formed on the first insulating interlayer layer successively.

And, a first and a second contact hole a first and second holes exposing a gate and heavily doped regions are formed by patterning the third to first insulating interlayers layers by photolithography in order, wherein the third insulating interlayer are overetched layer is over-etched to expose a portion of the second insulating interlayer layer corresponding to the heavily doped regions. In this case, the second insulating interlayer layer used as an etch-stop layer prevents the first insulating interlayer layer and field oxide layer from being etched.

Accordingly, the present invention prevents the a leakage current occurrence from being generated by avoiding the stress generation due to the contact between the semiconductor substrate and insulating interlayer layer.

It will be apparent to those skilled in the art that various modifications and variations can be made in a method of fabricating a semiconductor device of the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and equivalents.

Claims

1. A method of fabricating a semiconductor device comprising the steps of:

forming a field oxide layerdefining , which defines an active area and a field area on a semiconductor substrate of a first conductive type;

forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate;

forming impurity regions of a second conductive type in the semiconductor substrate in use of using the gate as a mask;

forming a first insulating interlayer layer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate;

forming a second insulating interlayer layer on the first insulating interlayer layer by depositing another insulator of which an etch rate is different from that of the first insulating interlayer layer;

forming a third insulating interlayer layer on the second insulating interlayer layer by depositing still another insulator of which an etch rate is different from that of the second insulating interlayer layer; and

forming a first contact hole and second contact holes respectively exposing the gate and heavily doped impurity regions respectively by successively patterning the third to first insulating interlayer successively by layers through photolithography,

wherein the second insulating layer is etched by C₂HF₆O₂, and

wherein the successive patterning of the third to first insulating layers excludes portions of the third to first insulating layers formed above the field oxide layer such that the portions of the third to first insulating layers formed above the field oxide layer prevent the etching of the field oxide layer.

2. The method of fabricating a semiconductor device according to claim 1, wherein the field oxide layer is formed by shallow trench isolation or by local oxidation of silicon.

3. The method of fabricating a semiconductor device according to claim 1, wherein the first insulating interlayer layer is formed by depositing silicon oxide to a thickness of 100 to 300 Åthick .

4. The method of fabricating a semiconductor device according to claim 3, wherein the first insulating interlayer layer is etched by a mixed gas of (C2F6+O2) or (C4F8+O2) (C₂F₆+O₂) or (C₄F₈+O₂).

5. The method of fabricating a semiconductor device according to claim 1, wherein the second insulating interlayer layer is formed by depositing silicon nitride to a thickness of 100 to 300 Åthick .

6. The method of fabricating a semiconductor device according to claim 5, wherein the second insulating interlayer is etched by C2HF6O2.

7. The method of fabricating a semiconductor device according to claim 1, wherein the third insulating interlayer layer is formed by depositing silicon oxide or boro phospho silicate glass or by coating with spin on glass.

8. The method of fabricating a semiconductor device according to claim 7, wherein the third insulating interlayer of a single layer is formed with one or more layers made of silicon oxide, boro phospho silicate glass, or spin on glassor wherein the third insulating interlayer of at least double layers is formed with silicon oxide, boro phospho silicate glass and spin on glass .

9. The method of fabricating a semiconductor device according to claim 7, wherein a surface of the third insulating interlayer layer is formed to be even.

10. The method of fabricating a semiconductor device according to claim 7, wherein the third insulating interlayer layer is etched by a mixed gas of (C2F6+O2) or (C4F8+O2) (C₂F₆+O₂) or (C₄F₈+O₂).

11. The method of fabricating a semiconductor device according to claim 10, wherein the third insulating interlayer layer is overetched over-etched to expose the second insulating interlayer layer corresponding to the heavily doped impurity regions.

12. The method of fabricating a semiconductor device according to claim 1, the method further comprising the step of forming first and second plugs in the first and second contact holes.

13. A method of fabricating a semiconductor device comprising the steps of

forming a field oxide layer defining which defines an active area and a field area on a semiconductor substrate of a first conductive type;

forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate;

forming a sidewall spacer at a side of the gate;

forming lightly doped regions of a second conductive type in exposed portions of the semiconductor substrate;

forming a sidewall spacer at a side of the gate;

forming heavily doped regions of the second conductive type in the semiconductor substrate in use of using the gate and sidewall spacer as a mask wherein so that the heavily doped regions are overlapped with the lightly doped regions;

forming a first insulating interlayer layer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate;

forming a second insulating interlayer layer on the first insulating interlayer layer by depositing another insulator of which an etch rate is different from that of the first insulating interlayer layer;

forming a third insulating interlayer layer on the second insulating interlayer layer by depositing still another insulator of which an etch rate is different from that of the second insulating interlayer layer;

forming a first contact hole first and second contact holes respectively exposing the gate and heavily doped regions respectively by successively patterning the third to first insulating interlayer successively by layers through photolithography; and

forming first and second plugs in the first and second contact holes,

wherein the second insulating layer is etched by C₂HF₆O₂, and

wherein the successive patterning of the third to first insulating layers excludes portions of the third to first insulating layers formed above the field oxide layer such that the portions of the third to first insulating layers formed above the field oxide layer prevent the etching of the field oxide layer.

14. A method of fabricating a semiconductor device comprising the steps of:

forming a field oxide layer, which defines an active area and a field area on a semiconductor substrate of a first conductive type;

forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate;

forming impurity regions of a second conductive type in the semiconductor substrate using the gate as a mask;

forming a first insulating layer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate;

forming a second insulating layer on the first insulating layer by depositing another insulator of which an etch rate is different from that of the first insulating layer;

forming a third insulating layer on the second insulating layer by depositing still another insulator of which an etch rate is different from that of the second insulating layer, the third insulating layer comprising two or more layers among silicon oxide, boro phospho silicate glass, and spin on glass; and

forming a first contact hole and second contact holes respectively exposing the gate and impurity regions by successively patterning the third to first insulating layers through photolithography,

wherein the successive patterning of the third to first insulating layers excludes portions of the third to first insulating layers formed above the field oxide layer such that the portions of the third to first insulating layers formed above the field oxide layer prevent the etching of the field oxide layer.

15. The method of fabricating a semiconductor device according to claim 14, wherein the field oxide layer is formed by shallow trench isolation or by local oxidation of silicon.

16. The method of fabricating a semiconductor device according to claim 14, wherein the first insulating layer is formed by depositing silicon oxide to a thickness of 100 to 300 Å.

17. The method of fabricating a semiconductor device according to claim 16, wherein the first insulating layer is etched by a mixed gas of (C₂F₆+O₂) or (C₄F₈+O₂).

18. The method of fabricating a semiconductor device according to claim 14, wherein the second insulating layer is formed by depositing silicon nitride to a thickness of 100 to 300 Å.

19. The method of fabricating a semiconductor device according to claim 18, wherein the second insulating layer is etched by C₂HF₆O₂.

20. The method of fabricating a semiconductor device according to claim 14, wherein the third insulating layer is formed by depositing silicon oxide or boro phospho silicate glass or by coating spin on glass.

21. The method of fabricating a semiconductor device according to claim 20, wherein a surface of the third insulating layer is formed to be even.

22. The method of fabricating a semiconductor device according to claim 20, wherein the third insulating layer is etched by a mixed gas of (C₂F₆+O₂) or (C₄F₈+O₂).

23. The method of fabricating a semiconductor device according to claim 22, wherein the third insulating layer is over-etched to expose the second insulating layer corresponding to the impurity regions.

24. The method of fabricating a semiconductor device according to claim 14, further comprising the step of forming first and second plugs in the first and second contact holes.

25. A method of fabricating a semiconductor device comprising the steps of

forming a field oxide layer which defines an active area and a field area on a semiconductor substrate of a first conductive type;

forming a gate on the active area of the semiconductor substrate by inserting a gate insulating layer between the semiconductor substrate and the gate;

forming lightly doped regions of a second conductive type in exposed portions of the semiconductor substrate;

forming a sidewall spacer at a side of the gate;

forming heavily doped regions of the second conductive type in the semiconductor substrate using the gate and sidewall spacer as a mask so that the heavily doped regions are overlapped with the lightly doped regions;

forming a first insulating layer on the semiconductor substrate by depositing an insulator of which heat expansion coefficient and lattice mismatch are less than those of the semiconductor substrate to cover the field oxide layer and the gate;

forming a second insulating layer on the first insulating layer by depositing another insulator of which an etch rate is different from that of the first insulating layer;

forming a third insulating layer on the second insulating layer by depositing still another insulator of which an etch rate is different from that of the second insulating layer, the third insulating layer comprising two or more layers among silicon oxide, boro phospho silicate glass, and spin on glass;

forming first and second contact holes respectively exposing the gate and heavily doped regions by successively patterning the third to first insulating layers through photolithography; and

forming first and second plugs in the first and second contact holes,

wherein the successive patterning of the third to first insulating layers excludes portions of the third to first insulating layers formed above the field oxide layer such that the portions of the third to first insulating layers formed above the field oxide layer prevent the etching of the field oxide layer.