A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the doped copper seed layer. The method may further include annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer. The doped copper seed layer may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to provide the enhanced electromigration resistance. Forming the copper layer may comprise plating the copper layer. In addition, forming the copper layer may comprise forming the copper layer to include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant. In some embodiments, the dopant in the seed layer may be sufficient so that no additional dopant is needed in the copper layer.
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1. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure adjacent a substrate by , wherein said forming at least one interconnect structure comprises:
forming at least one barrier layer, ;
forming a doped copper seed layer on the at least one barrier layer, wherein the doped copper seed layer including includes a dopant comprising at least one of calcium, cadmium, neodymium, or tellurium, and ytterbium, ; and
forming a copper layer on the doped copper seed layer.
10. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure adjacent a substrate by , wherein said forming at least one interconnect structure comprises:
forming at least one metal barrier layer, ;
forming a doped copper seed layer on the at least one metal barrier layer, wherein the doped copper seed layer including includes a dopant comprising at least one of calcium, cadmium, neodymium, or tellurium, and ytterbium, ; and
forming a copper layer on the doped copper seed layer.
0. 64. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure, wherein said forming at least one interconnect structure comprises:
forming at least one barrier layer;
forming a doped copper seed layer including at least one dopant configured to provide enhanced electromigration resistance; and
forming a copper-containing layer over the doped copper seed layer, wherein at least a portion of the copper-containing layer is plated with a plating layer including a metal more noble than copper.
0. 43. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure, wherein said forming at least one interconnect structure comprises:
forming at least one barrier layer;
forming a doped copper seed layer including at least one dopant comprising calcium, cadmium, zinc, neodymium, tellurium, or ytterbium; and
forming a copper-containing layer over the doped copper seed layer, wherein at least a portion of the copper-containing layer is plated with a plating layer including a metal more noble than copper.
0. 25. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure, wherein said forming at least one interconnect structure comprises:
forming a plating layer on a first copper-containing layer, wherein the plating layer includes a metal more noble than copper;
forming at least one barrier layer on the plating layer;
forming a doped copper seed layer including at least one dopant comprising calcium, cadmium, zinc, neodymium, tellurium, or ytterbium; and
forming a second copper-containing layer on the doped copper seed layer.
0. 54. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure, wherein said forming at least one interconnect structure comprises:
forming at least one barrier layer;
forming a doped copper seed layer including at least one dopant configured to provide enhanced electromigration resistance;
forming a copper-containing layer on the doped copper seed layer, wherein the doped copper seed layer has a higher dopant concentration than the copper-containing layer; and
annealing the integrated circuit device after forming the copper-containing layer to diffuse the dopant from the doped copper seed layer at least into the copper-containing layer.
18. A method for making an integrated circuit device, comprising:
forming at least one interconnect structure adjacent a substrate by , wherein said forming at least one interconnect structure comprises:
forming at least one barrier layer, ;
forming a doped copper seed layer on the at least one barrier layer, wherein the doped copper seed layer including includes a dopant comprising at least one of calcium, cadmium, neodymium, tellurium, and or ytterbium, ;
plating a copper layer on the doped copper seed layer, wherein the doped copper seed layer has a higher dopant concentration than the copper layer; and
annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into the copper layer.
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forming at least one dielectric layer adjacent the a substrate; and
forming at least one opening in the at least one dielectric layer for receiving the at least one interconnect structure therein.
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forming at least one dielectric layer adjacent the a substrate; and
forming at least one opening in the at least one dielectric layer for receiving the at least one interconnect structure therein.
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forming at least one dielectric layer adjacent the a substrate; and
forming at least one opening in the at least one dielectric layer for receiving the at least one interconnect structure therein.
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forming at least one dielectric layer; and
forming at least one opening in the at least one dielectric layer for receiving at least part of the at least one interconnect structure therein.
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forming at least one dielectric layer; and
forming at least one opening in the at least one dielectric layer for receiving the at least one interconnect structure therein.
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forming at least one dielectric layer; and
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forming at least one dielectric layer; and
forming at least one opening in the at least one dielectric layer for receiving the at least one interconnect structure therein.
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This application is a based upon provisional application Ser. No. 60/150,156 filed Aug. 20, 1999, now abandoned and is a continuation-in-part application of U.S. patent application Ser. No. 09/619,587 filed on Jul. 19, 2000 which, in turn, is based upon prior filed provisional application Ser. No. 60/145,036 filed Jul. 22, 1999, the entire disclosures of all of which are incorporated herein by reference.
The present invention relates to the field of integrated circuits and integrated circuit manufacturing, and more particularly, to making interconnection structures with enhanced electromigration resistance, and while not significantly increasing the resistivity of the metal.
A metal interconnect system in wide use in the later 1990's included an Al+Cu alloy interconnect line clad on each side with a barrier metal, and combined with planarized tungsten plugs for vias. A via is the structure that provides the electrical connection from one vertical level of interconnects to the next. The system saw wide acceptance in the industry, especially for high performance logic applications, such as microprocessor chips. The system was perceived as satisfactory, except that a severe degradation in electromigration resistance was noted on test patterns with multiple levels of interconnects and tungsten plug vias, versus test patterns using one interconnect level and no vias.
As much as a 100 times reduction in median-time-to-failure (T50) values, or more, were noted. One technical paper covering this phenomenon in detail is by R. G. Filippi et al., entitled, “The Effect of Copper Concentration on the Electromigration of Layered Aluminum-Copper (Ti-AlCu-Ti) Metallurgy With Tungsten Diffusion Barriers.” The paper appears in the 1992 VMIC Conference Proceedings, on page 359. The researchers showed that the copper doping is swept away from the tungsten in the direction of current flow. The aluminum, then depleted of its copper, electromigrates rapidly and voids appear at or near the W/Al interface. Increasing the concentration of copper helps to a limited extent, but degrades the resistivity. Stripes with a close by “reservoir” of copper also showed improvement, but none of these measures completely solved the problem. In general, the phenomenon may be referred to as a flux divergence at a dissimilar material interface.
A similar phenomenon has been noted in a copper system with tungsten plugs. This was reported, for example, by Kazuhide Abe, et al., and coworkers in a paper entitled, “Cu Damascene Interconnects with Crystallographic Texture Control and Its Electromigration Performance,” and appears in the IEEE 1998 Reliability Physics Symposium Proceedings on page 342.
The widely-accepted dual Damascene copper systems does not use tungsten plugs between interconnect levels, but does employ a barrier metal. This barrier layer lies, in general, between the upper surface of a copper interconnect and the bottom of an overlying copper via. Thus, some flux divergence may occur at this interface at high current density. The location of the copper metal depletion depends on the direction of current flow. For example, if the current flows up into overlying metal, this is the area of voiding and damage.
In view of the foregoing background, it is therefore an object of the invention to provide a integrated circuit processing method which eliminates or significantly diminishes the flux divergence phenomenon such that little degradation of electromigration resistance occurs at the via structures relative to other regions in the interconnect system.
Another object of the invention is to provide a thin, hardened alloy skin on selected copper surfaces to reduce electromigration resistance and/or provide for passivation.
These and other objects, features and advantages in accordance with the present invention are provided by a method for making an integrated circuit device comprising forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the doped copper seed layer. The method may further comprise annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer. The doped copper seed layer may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to provide the enhanced electromigration resistance.
Forming the copper layer may comprise plating the copper layer. In addition, forming the copper layer may comprise forming the copper layer to include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant. In some embodiments, the dopant in the seed layer may be sufficient so that no additional dopant is needed in the copper layer.
The method may further comprise forming at least one dielectric layer adjacent the substrate, and forming at least one opening in the at least one dielectric layer for receiving the at least one interconnect structure therein. Forming the at least one barrier layer may include forming at least one barrier layer comprising metal. The barrier layer may comprise one of tantalum nitride and tantalum silicon nitride. Alternately, the barrier layer may include cobalt and phosphorous. The method may also include forming a displacement plated copper layer on which the at least one barrier layer is formed.
Another aspect of the invention relates to an integrated circuit device. More particularly, the device may include a substrate, at least one dielectric layer adjacent the substrate and having at least one opening therein, and at least one interconnect structure in the at least one opening. The interconnect structure may comprise at least one barrier layer adjacent the at least one opening, a doped copper seed layer on the at least one barrier layer, and a copper layer on the doped copper seed layer. The copper layer may comprise grain boundaries adjacent the doped copper seed layer containing dopant therein. These grain boundaries may be filled during an annealing step during processing. The doped copper seed layer may comprise at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant. If desired, the copper layer may also comprise at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout, and prime notation is used in an alternate embodiment to indicate similar elements.
Referring initially to
As shown in
As shown in
By selection of relatively inert metals, such as Pd or Pt, the invention also tends to passivate the temporarily exposed surface of the copper until the next step in the process is underway. This reduces oxidation and staining of the copper.
Alternatively, the copper interconnect 15 may be displacement plated following its delineation by CMP as is normally used in the Damascene approach as will be appreciated by those skilled in the art. In other words, in other embodiments, the entire upper surface could be displacement plated as described herein.
Several metals have higher reduction potentials than copper, that is, are more noble than copper. Selected reduction potentials are as follows: Ag+→Ag, 0.8 volts; Au+→Au, 1.7 volts; Pd++→Pd, 0.95 volts; Ir+++→Ir, 1.2 volts; Rh++→Rh, 0.6 volts; Hg++→Hg, 0.8 volts; Pt++→Pt, 1.2 volts, Copper itself exhibits a single electrode potential of Cu+→Cu, 0.52 volts. Any metal in a simple ion solution which has a reduction potential more positive than copper will spontaneously oxidize the copper and plate itself onto the copper as the metal. The displacement plating can be achieved using simple ion chemistries, such as sulfates or chlorides as will be appreciated by those skilled in the art. A monolayer or more will form depending on the porosity of the coating. A metal which is less noble than copper, such as cadmium, Cd+→Cd, −0.4 volts, will not undergo the displacement reaction with copper.
After the formation of the very thin metal coating or plating layer 20, an anneal is preferably performed sometime in the wafer processing flow so that the metal is driven into the copper a few atomic layers downward. For palladium, for example, considering the bulk diffusion constant of Pd through Cu, the diffusion length √ Dt for an anneal of one hour at 450° C. is about 100 Å. Thus a zone of roughly 100 Å of Cu+Pd alloy wold be characterized by a marked increase in electromigration resistance due primarily, in this case, to a reduced rate of material transport from lattice diffusion processes.
Palladium and other metals listed above may not have ideal metallurgical characteristics which lend themselves towards the reduction of material transport rates due to high current density effects. In this case, however, the dopants would exist in high concentration. This is a factor which would tend to offset negative factors and which might contribute to their efficacy.
The deposition method described is not an electroless plating process. Thus, the coating or plating layer 20 thickness is self-limiting, and does not tend to coat the adjacent dielectric material 16. For this reason, the concentration of the metal in the aqueous plating bath 24 and the plating time are not critical as will be readily appreciated by those skilled in the art.
The rise in resistivity in the narrow zone of copper near the surface would be large with the high concentration of dopant. But, since the thickness of the effected layer is so narrow, the added via resistance would be small.
Such a treatment will tend to form a more stable transition from the barrier metal to the undoped or lightly-doped copper of the seed layer 22, reducing material transport rates during high current density periods.
In order to similarly protect the copper metal 23 on the upper side of the barrier layer 21, the seed layer 22 upon which the copper is plated may be sputter deposited with dopants. For example, the seed layer 22 cold be 300-500 Å thick, sputter deposited, and contain 0.2 to 3 at.% Cd or Zn. The copper seed layer 22 could also include at least one of calcium, neodymium, tellurium, and ytterbium.
Alternatively, as explained with reference to
As scaling down into submicron dimensions continues in the semiconductor industry, the deposition of a uniform and conformal barrier metal into contact and via openings becomes increasingly difficult. This holds true for coating methods, such as sputtering and to a somewhat lesser extent for CVD methods. But plating methods, such as electroless plating, offer improved conformality. Various metal barrier films deposited by electroless methods have been studied. For example, some of these results appear in E. J. O'Sullivan et al., “Electrolessly deposited diffusion barriers for microelectronics,” IBM J. Res. Dev. Vol. 42, No. 5, September 1998, p. 607; and Milan Paunovic et al., “Electrochemically Deposited Diffusion Barriers,” J. Electrochem. Soc., 141, No. 7, July 1994, p. 1843. This work showed that out of several candidates, a barrier of Co+P gave the best results. Electroless “Co(P)” did not interdiffuse with copper even with extended heating at 400° C. This alloy may be plated to dielectric surfaces by activation with PdCl2, as will be readily appreciated by those skilled in the art.
Referring now additionally to
First and second nitride layers 37 and 41 are shown adjacent the top and bottom, respectively, of a second dielectric layer 42 which act as etch stops as will be appreciated by those skilled in the art. A third dielectric layer 43 is provided on the upper etch stop layer 41 in the illustrated embodiment. A second barrier layer 44 is also provided to line or coat the opening for the second interconnect line 45 as will also be appreciated by those of skill in the art of Damascene copper technology. The upper surface portion of the copper interconnect layer 45 will be polished flush in a subsequent step as will be understood by those skilled in the art.
In accordance with another important aspect of the invention, a doped copper seed layer 46 is provided on which the copper interconnect layer 45 is formed. This doped copper seed layer may be deposited by sputtering. Alternately, an all electrochemically formed copper-based interconnect may be formed by first forming the electrolessly deposited barrier layer 44 as shown, and then electroplating the doped seed layer 46 on the activated barrier layer. The activation may be accomplished by displacement or electrolessly plating a very thin layer of a more noble metal, such as Pd, Pt, Ag or Au, for example, as discussed above.
Following the doped seed layer 46 deposition, the thick copper or copper alloy film 45 may be built up by electroplating, for example. The doped copper or copper alloy seed layer 46 may have a higher dopant concentration than the bulk interconnect layer 45 increasing the process latitude. The doped copper seed layer 46 may include a dopant comprising at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium. Such a system provides an electromigration resistant via in both current directions as will be appreciated by those skilled in the art. Of course, in some embodiments, the bulk copper interconnect layer 45 may also include the same or other such dopants to enhance electromigration resistance as described herein.
Other related concepts and discussions are provided in the following U.S. patent applications: Ser. No. 09/045,610, filed Mar. 20, 1998; Ser. No. 09/148,096 filed on Sep. 4, 1998; Ser. No. 09/271,179 filed on Mar. 17, 1999; Ser. No. 09/289,331 filed on Apr. 9, 1999; Ser. No. 09/619,587 filed on Jul. 19, 2000; Ser. No. 60/150,156 filed on Aug. 20, 1999; Ser. No. 60/153,400 filed on Sep. 10, 1999; and Ser. No. 60/159,068 filed on Oct. 12, 1999. The entire disclosure of each of these applications is incorporated herein by reference.
Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed, and that other modifications and embodiments are intended to be included within the scope of the appended claims.
| Patent | Priority | Assignee | Title |
| 9295163, | May 30 2013 | Method of making a circuit board structure with embedded fine-pitch wires | |
| 9788427, | May 30 2013 | Circuit board structure with embedded fine-pitch wires and fabrication method thereof |
| Patent | Priority | Assignee | Title |
| 4233067, | Jan 19 1978 | Sumitomo Electric Industries, Ltd. | Soft copper alloy conductors |
| 4592891, | Jun 14 1984 | Nippon Mining & Metals Company, Limited | Corrosion-resistant copper alloy |
| 4732731, | Aug 29 1985 | FURUKAWA ELECTRIC CO , LTD , THE, NO 6-1, MARUNOUCHI 2-CHOME, CHIYODA-KU, TOKYO, JAPAN | Copper alloy for electronic instruments and method of manufacturing the same |
| 4750029, | Aug 31 1984 | MITSUBISHI SHINDOH CO , LTD , NO 6-2, GINZA 1-CHOME, CHUO-KU, TOKYO, JAPAN, A CORP OF JAPAN | Copper base lead material for leads of semiconductor devices |
| 4908275, | Mar 04 1987 | NIKKO MATERIALS COMPANY LIMITED AKA KABUSHIKI KAISHA NIKKO MATERIALS ; JAPAN ENERGY DENSHI ZAIRYO KABUSHIKI KAISHA | Film carrier and method of manufacturing same |
| 4986856, | Jun 25 1987 | FURUKAWA ELECTRIC CO , LTD , THE; FURUKAWA SPECIAL METAL CO , LTD | Fine copper wire for electronic instruments and method of manufacturing the same |
| 5130274, | Apr 05 1991 | GLOBALFOUNDRIES Inc | Copper alloy metallurgies for VLSI interconnection structures |
| 5143867, | Feb 13 1991 | International Business Machines Corporation | Method for depositing interconnection metallurgy using low temperature alloy processes |
| 5592024, | Oct 29 1993 | Kabushiki Kaisha Toshiba | Semiconductor device having a wiring layer with a barrier layer |
| 5624506, | Sep 30 1993 | Kabushiki Kaisha Kobe Seiko Sho; Yazaki Corporation | Copper alloy for use in electrical and electronic parts |
| 5674787, | Jan 16 1996 | Cornell Research Foundation, Inc | Selective electroless copper deposited interconnect plugs for ULSI applications |
| 5694184, | Aug 01 1995 | Kabushiki Kaisha Toshiba | Liquid crystal display device |
| 5695810, | Nov 20 1996 | Cornell Research Foundation, Inc.; Sematech, Inc.; Intel Corporation | Use of cobalt tungsten phosphide as a barrier material for copper metallization |
| 5719447, | Jun 03 1993 | Intel Corporation | Metal alloy interconnections for integrated circuits |
| 5789320, | Apr 23 1996 | GLOBALFOUNDRIES Inc | Plating of noble metal electrodes for DRAM and FRAM |
| 5830563, | Nov 29 1995 | NEC Corporation | Interconnection structures and method of making same |
| 6037257, | May 08 1997 | Applied Materials, Inc. | Sputter deposition and annealing of copper alloy metallization |
| 6037664, | Aug 20 1997 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer |
| 6060892, | Dec 27 1996 | Tokyo Electron Limited | Probe card attaching mechanism |
| 6066892, | Jun 18 1997 | Applied Materials, Inc. | Copper alloy seed layer for copper metallization in an integrated circuit |
| 6077780, | Dec 03 1997 | GLOBALFOUNDRIES Inc | Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure |
| 6100194, | Jun 22 1998 | STMicroelectronics, Inc. | Silver metallization by damascene method |
| 6100195, | Dec 28 1998 | Chartered Semiconductor Manu. Ltd.; National University of Singapore; Nahyang Techn. Univ. of Singapore; Institute of Microelectronics | Passivation of copper interconnect surfaces with a passivating metal layer |
| 6136707, | Oct 02 1999 | COHEN, URI, DR | Seed layers for interconnects and methods for fabricating such seed layers |
| 6140234, | Jan 20 1998 | GLOBALFOUNDRIES Inc | Method to selectively fill recesses with conductive metal |
| 6143422, | Feb 05 1998 | Sumitomo Metal Industries, Ltd. | Surface-treated steel sheet having improved corrosion resistance after forming |
| 6147402, | Feb 26 1992 | GLOBALFOUNDRIES Inc | Refractory metal capped low resistivity metal conductor lines and vias |
| 6157081, | Mar 10 1999 | Advanced Micro Devices, Inc. | High-reliability damascene interconnect formation for semiconductor fabrication |
| 6174799, | Jan 05 1999 | GLOBALFOUNDRIES Inc | Graded compound seed layers for semiconductors |
| 6180523, | Oct 13 1998 | Industrial Technology Research Institute | Copper metallization of USLI by electroless process |
| 6181012, | Apr 27 1998 | GLOBALFOUNDRIES Inc | Copper interconnection structure incorporating a metal seed layer |
| 6197688, | Feb 12 1998 | Freescale Semiconductor, Inc | Interconnect structure in a semiconductor device and method of formation |
| 6214728, | Nov 20 1998 | Chartered Semiconductor Manufacturing, Ltd. | Method to encapsulate copper plug for interconnect metallization |
| 6249055, | Feb 03 1998 | GLOBALFOUNDRIES Inc | Self-encapsulated copper metallization |
| 6268291, | Dec 03 1998 | AURIGA INNOVATIONS, INC | Method for forming electromigration-resistant structures by doping |
| 6303498, | Aug 20 1999 | Taiwan Semiconductor Manufacturing Company | Method for preventing seed layer oxidation for high aspect gap fill |
| JP10008167, | |||
| JP1028337, | |||
| JP1056842, | |||
| JP2230756, | |||
| JP60110868, | |||
| JP62127438, | |||
| JP62133050, | |||
| JP9157775, |
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