System and method for integrating a digital core with a switch mode power supply

Abstract

A digital core embodied within a semiconductor die that requires plural separate power supply voltage domains is situated within any of a variety of integrated circuit packaging technologies. Within the integrated circuit package including this semiconductor die also exists a switch mode dc-to-dc voltage converter, preferably a synchronous step-down regulator powering the entire integrated circuit from one supply voltage. The components contained within the integrated circuit package along with the semiconductor die include the switch mode power supply's power switching transistors, inductor core and windings, digital open-loop output voltage fixing circuitry, output capacitors and substrate for mounting said components when integrated within a packaging technology that does not already include a substrate.

Description

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention is generally in the field of semiconductor circuits. More specifically, the present invention is in the field of semiconductor die packaging with integrated power supply voltage regulation.

2. Background Art

Advances in semiconductor integrated circuit fabrication processes and digital standard cell and semi-custom application specific integrated circuit, “ASIC”, design methodologies have given rise to digital and mixed analog and digital signal integrated circuits requiring separate power supplies for various parts including a unique voltage for the digital core power supply, and a second, unique power supply voltage for the input/output pad ring, and possibly a third power supply voltage for miscellaneous analog functions. While this advancement brings the advantage of reduced core power consumption as a product of one-half the total gate capacitances times the gate voltages squared times the switching frequency, there arises the problem of regulation of these additional voltages. With the advent of system-on-chip technologies, designers of these devices have only begun to address this requirement for regulating multiple power supply domains on-chip. Given prior art, it often finally remains the responsibility of the top-level system integrator to provide this variety of power supply voltage domains at the board level and not chip level, obscuring the costs of the total solution implementing the prior art system-on-chip. Often both the system-on-chip designer and the top-level integrator, not having the time, resources, or background of experience in power supply design tend to choose simple-to-implement, but less than optimal linear voltage regulation cores or devices to provide these plural voltage domains from a single supply voltage. When implemented using a linear voltage regulation device, a substantial amount of the power savings realized by accepting a lower core voltage is lost in the form heat dissipated through the linear regulator's transistors, by design. The overall solution cost and power consumption may actually rise if this heat dissipated in the linear voltage regulator is great enough to require additional components to provide forced air convection cooling. Also, the system-on-chip itself could require additional heat-sinking components or else suffer reduced reliability due to the implementation of a linear voltage regulator on-chip, thereby driving-up hidden costs of the total solution.

Therefore, there exists a need for a novel and reliable system and method to provide power to multiple voltage domains of semiconductor dies to overcome the problems faced by conventional semiconductor die packages integrating a linear voltage regulation power supply. More specifically, there exists a need for a novel and reliable system and method to optimally provide power to multiple voltage domains within semiconductor dies while reducing overall system cost, power consumption, and heat dissipation.

SUMMARY OF INVENTION

The present invention is directed to a system and method for integrating a semiconductor die of plural power supply voltage domains with a switch mode DC-to-DC converter in an integrated circuit package. The invention discloses a system and a method to design and fabricate such an integrated circuit system in a single package to obtain optimal power savings, and minimal heat dissipation and cost. According to one embodiment, a semiconductor die is situated within the periphery of a lead frame adjacent to the switch mode power supply substrate. The substrate can comprise, for example, a ceramic material, or most economically, a fiberglass resin epoxy based laminate material such as FR4. In one embodiment, the semiconductor die is situated on the substrate adjacent to the integrated switch mode DC-to-DC converter. In one embodiment, a semiconductor die may receive power for its lower voltage supply pads through any DC-to-DC converter of the switch mode step-down variety in a closed-loop general solution implementation.

In the preferred embodiment, the present invention provides a superior means for optimally converting voltages to the correct domains for semiconductor die operation through synchronous step-down conversion. Furthermore, the present invention's substantial departure from prior art and significant novelty exists in the preferred embodiment wherein said switch mode synchronous DC-to-DC step-down converter is implemented in an open-loop configuration retaining precision based on semiconductor die power consumption characterization data, thus achieving the lowest possible cost for total solution of the system-on-chip.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1115—(R501)(C502) In(1−07/V_in) seconds and a minimum of—(R501)(C502)In1;a few tens of less than ten milliohms and thus the ripple voltage, a product of the ripple current multiplied by this capacitor's ESR, will be less than 5 milliVolts. Therefore this exemplary circuit integrating a digital core with a high efficiency switch mode voltage regulator comprising a semiconductor die and three low profile packages could fit well within the confines of many packaging technologies, especially the presently popular Ball Grid Array or the Plastic Quad Flat Pack standard form factors of the Joint Electron Device Engineering Council.

FIG. 7 and FIG. 8 render a perspective view of a physical embodiment of the previously described design example within the scope of the present invention. Power supply substrate 703 and likewise substrate 800 may consist of a ceramic material, an organic material such as polytetrafluoroethylene material, or most commonly a fiberglass resin epoxy based laminate material such as FR4. In FIG. 7, the power supply substrate 703 and the semiconductor die 100 sit adjacent to each other within the periphery of a lead frame 700 for assembly within a leaded package. In FIG. 8, the power supply components are mounted on the same substrate 800 as the semiconductor die 100, the practice of mounting a semiconductor die directly to a substrate as such being common to Ball Grid Array packages of prior art. In both of these two exemplary embodiments, the toroid core inductor 105, the package containing the power switching transistors 103, 104, and the output capacitor 106 are first mounted to the substrate. In any of the methods within the scope of the present invention, once these components are mounted to the substrate, the substrate may be probe tested at various load currents and duty cycles corresponding to the power states of the semiconductor die 100, and then trimmed according to any of the previously described output voltage offset adjusting systems or methods. According to the embodiment of FIG. 7, the bonding pads of the power supply substrate 703 and the semiconductor die 100 are then first affixed to the lead frame 700 by bonding wires 706 and 708, respectively, attaching to lead frame bonding pads 707 and 701, respectively, and then interstitial bonding wires 704 attach the bonding pads 702 of the semiconductor die 100 to the bonding pads 705 of the power supply substrate 703. The present invention places no restriction upon the signal types conducted via the interstitial bonding wires 704, they may conduct any of the power supply specific signals or also simply any signals conveniently routed to the side of semiconductor die 100 in the location of bonding pads 702, across the interstitial bonding wires 704, and routed directly from bonding pads 705 across the power supply substrate 703 to the power supply substrate pads nearest the lead frame bonding pads 707. After affixing all of the interstitial bonding wires 704, the device may then be sealed with an epoxy in a ceramic body or molded in a plastic body and undergo final test. In FIG. 8, as with the embodiment of FIG. 7, once the supply components 103, 104, 105, 106 have been mounted and optionally tested and trimmed, bonding wires 802 affix the semiconductor die 100 to the substrate 800 and permit electrical and perhaps heat conduction from the bonding pads 702 of the semiconductor die 100 to the bonding pads 801 of the substrate 800. The top surface of the substrate 800 may then be sealed with an epoxy or molded over with a plastic body and undergo final test. In the case of a Ball Grid Array package, the bottom surface of the substrate 800 contains pads that in the final step have solder balls attached.

From the preceding description of the present invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Furthermore, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would recognize that changes could be made in form and detail without departing from the scope and the spirit of the invention. The described embodiments have been presented in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the previously described particular embodiments, but is capable of many rearrangements, modifications, omissions, and substitutions without departing from the scope of the invention.

Thus, a system and method for integrating a digital core with a switch mode power supply has been described.

Claims

1. An integrated circuit package, comprising:

a semiconductor die of plural separate power supply voltage domains; and

a switch mode dc-to-dc converter, comprising:

wherein said switch mode dc-to-dc converter comprises:

an inductor core and windings;

a power switching transistor; and

an output voltage fixing circuit comprising a digital open-loop means circuit configuration requiring no feed-forward loop and no feedback loop.

2. An integrated circuit package, comprising:

a semiconductor die of plural separate power supply voltage domains; and

a switch mode dc-to-dc converter, comprising:

wherein said switch mode dc-to-dc converter comprises:

an inductor core and windings;

a power switching transistor; and

an output voltage fixing circuit,

wherein said semiconductor die comprises a decoder that compares an entry from a table corresponding to the present power state of said semiconductor die to a clock counter frequency divider output to determine a duty cycle and/or switching frequency of said power switching transistor for said output voltage fixing circuit.

3. The integrated circuit of claim 2, wherein said table of entries of clock counter values used to determine said duty cycle is encoded within logic within circuitry of said semiconductor die.

4. The integrated circuit of claim 2, wherein said table of entries of clock counter values used to determine said duty cycle is contained within non-volatile memory.

5. The integrated circuit package of claim 2, wherein the a power transistor gate-driving signal output from said semiconductor die is connected through a charge pump circuit to optimize the efficiency of the power switching transistor of said dc-to-dc converter.

6. The integrated circuit package of claim 2, further comprising a substrate of fiberglass resin epoxy of type FR4 based FR4-based laminate material for mounting components of said dc-to-dc converter components .

7. The integrated circuit package of claim 6, wherein said semiconductor die further comprises a plurality of pads from which to accept a binary number offset for fine tuning said duty cycle and/or switching frequency by modifying the value said table entry being compared to the clock counter frequency divider in output by said output voltage fixing circuit of said dc-to-dc converter.

8. The output voltage fixing integrated circuit package of claim 7, wherein said binary number offset is embodied included within fusible leads on said substrate that are electrically or mechanically trimmed or laser-trimmed at the factory .

9. The output voltage fixing integrated circuit package of claim 7, wherein said binary number offset is embodied included within a an optional wire-bonding option during assembly of said plurality of semiconductor die pads to the lead frame of said integrated circuit package.

10. The integrated circuit package of claim 6, wherein the a power transistor gate driving that drives signal output from said semiconductor die is connected through a trimmed delay circuit to fine tune the duty cycle of a pulse width modulator or pulse frequency modulator of the output voltage fixing circuit of said dc-to-dc converter.

11. The output voltage fixing integrated circuit package of claim 10, wherein said trimmed delay circuit further comprises a laser-trimmed printed film resistor on the substrate that is laser-trimmed at the factory .

12. An integrated circuit package, comprising,

a substrate of fiberglass resin epoxy of type FR4 g based laminate material for mounting: ;

a semiconductor die of plural separate power supply voltage domains mounted on said substrate; and

a switch mode dc-to-dc converter further comprising an inductor core and windings, mounted on said substrate, wherein said switch mode dc-to-dc converter comprises:

a power switching transistor; and

an output voltage fixing circuit comprising a digital open-loop means circuit configuration requiring no feed-forward loop and no feedback loop.

13. The output voltage fixing integrated circuit package of claim 7, wherein said binary number offset is embodied included within a an optional wire-bonding option during assembly of said plurality of semiconductor die pads onto a said substrate of fiberglass resin epoxy of type FR4 based FR4-based laminate material.

14. A method for design and fabrication of an integrated circuit package comprising a semiconductor die of plural separate power supply voltage domains with an integrated switch mode power supply, said method comprising steps of :

designing a semi-custom or standard cell library based digital core and obtaining from the design automation tools power consumption estimates in various power states given known clocking rates;

determining switch mode power supply frequency, inductance, and duty cycles for various power states given said power consumption estimates and system clocking;

fabricating said semiconductor die for prototyping purposes, packaged without said integrated switch mode power supply;

characterizing said prototype semiconductor die for power consumption over all operating power states and environmental conditions and process variations;

fabricating said switch mode power supply onto final production substrates;

trimming the output voltage fixing circuit of said switch mode power supply after a probe test to determine the output voltages at given duty cycles versus output currents defined by said semiconductor die known characterization data; and

bonding and molding or sealing with epoxy said semiconductor die and power supply substrate into an integrated package.

15. The method of claim 14, wherein said step of trimming the output voltage fixing circuit further comprises a step of binning said final production power supply substrates into the appropriate wire-bonding assembly line to set the proper binary number offset of the output voltage fixing circuit.

16. The method of claim 14, wherein said step of trimming the output voltage fixing circuit further comprises a step of breaking fusible leads on said final production power supply substrate to set the binary number offset of the output voltage fixing circuit.

17. The method of claim 14, wherein said step of trimming the output voltage fixing circuit further comprises a step of laser trimming a printed film resistor forming a delay circuit of the output voltage fixing circuit on said final power supply substrate.

18. The method of claim 14, wherein said step of trimming the output voltage fixing circuit further comprises a step of programming a non-volatile memory with entries of clock counter values to determine duty cycle and/or switching frequency corresponding to each power state of the semiconductor die.

19. A method for design and fabrication of an integrated circuit package comprising a semiconductor die of plural separate power supply voltage domains with an integrated switch mode power supply, said method comprising steps of :

designing a semi-custom or standard cell library based digital core and obtaining from the design automation tools power consumption estimates in various power states given known clocking rates;

determining switch mode power supply frequency, inductance, and duty cycles for various power states given said power consumption estimates and system clocking;

fabricating said semiconductor die for prototyping purposes, packaged without said integrated switch mode power supply;

characterizing said prototype semiconductor die for power consumption over all operating power states and environmental conditions and process variations;

fabricating said switch mode power supply onto final production substrates; and

bonding and molding or sealing with epoxy said semiconductor die and assembled final power supply substrate into an integrated package.

20. A semiconductor die comprising a decoder that compares an entry from a table corresponding to a present power state of said semiconductor die to a clock counter frequency divider output to determine a duty cycle and/or switching frequency of at least one power switching transistor for an output voltage fixing circuit of a switch mode dc-to-dc converter.

21. The semiconductor die of claim 20, wherein said table used to determine said duty cycle is encoded within logic circuitry of said semiconductor die.

22. The semiconductor die of claim 20, wherein said table used to determine said duty cycle is contained within non-volatile memory.

23. The semiconductor die of claim 20, further comprising:

at least one pad from which to accept a binary number offset for fine tuning said duty cycle and/or switching frequency, wherein said fine tuning operates by modifying said table entry being compared to the clock counter frequency divider output by said output voltage fixing circuit of said dc-to-dc converter.

24. The semiconductor die of claim 23, wherein said binary offset is a binary output of at least one analog comparator.

25. A method of design of a power supply for an integrated circuit, comprising:

determining a prior characterization of power consumption over all operating power states, environmental conditions, and process variations of said integrated circuit; and

providing as said power supply an output voltage fixing circuit that retains precision based on said determined power consumption characterization data of said integrated circuit.

26. The integrated circuit package of claim 1, wherein said switch mode dc-to-dc converter further comprises an inductor core and windings.

27. An integrated circuit package, comprising:

a semiconductor die of plural separate power supply voltage domains; and

a switch mode dc-to-dc converter, comprising:

a power switching transistor; and

an output voltage fixing circuit comprising a digital open-loop circuit configuration that retains precision based on power consumption characterization data of said semiconductor die.

28. The integrated circuit package of claim 27, wherein said switch mode dc-to-dc converter further comprises an inductor core and windings.

29. The integrated circuit package of claim 2, wherein said decoder compares an entry from a table, said entry based on power consumption characterization data and corresponding to the present power state of said semiconductor die, to the clock counter frequency divider output to determine a duty cycle and/or switching frequency of said power switching transistor for said output voltage fixing circuit.

30. The integrated circuit package of claim 12, wherein said substrate is fiberglass resin epoxy of type FR4-based laminate material.

31. The integrated circuit package of claim 12, wherein said switch mode dc-to-dc converter comprises an inductor core and windings.

32. An integrated circuit package, comprising:

a substrate;

a semiconductor die of plural separate power supply voltage domains mounted on said substrate; and

a switch mode dc-to-dc converter comprising:

a power switching transistor; and

an output voltage fixing circuit configured to retain precision based on power consumption characterization data of said semiconductor die.

33. The integrated circuit package of claim 32, wherein said switch mode dc-to-dc converter further comprises an inductor core and windings.

34. The integrated circuit package of claim 32, wherein said output voltage fixing circuit comprises a digital open-loop circuit configuration requiring no feed-forward loop and no feedback loop.

35. The integrated circuit package of claim 32, wherein said substrate is fiberglass resin epoxy of type FR4-based laminate material.

36. The semiconductor die of claim 20, wherein said table entries are based on power consumption characterization data and correspond to the present power state of said semiconductor die.

37. The semiconductor die of claim 24, wherein said at least one analog comparator enables operation of said dc-to-dc converter in an energy-saving pulse skip mode.

38. The integrated circuit package of claim 2, wherein said switch mode dc-to-dc converter further comprises an inductor core and windings.