A digital core embodied within a semiconductor die that requires plural separate power supply voltage domains is situated within any of a variety of integrated circuit packaging technologies. Within the integrated circuit package including this semiconductor die also exists a switch mode dc-to-dc voltage converter, preferably a synchronous step-down regulator powering the entire integrated circuit from one supply voltage. The components contained within the integrated circuit package along with the semiconductor die include the switch mode power supply's power switching transistors, inductor core and windings, digital open-loop output voltage fixing circuitry, output capacitors and substrate for mounting said components when integrated within a packaging technology that does not already include a substrate.
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0. 20. A semiconductor die comprising a decoder that compares an entry from a table corresponding to a present power state of said semiconductor die to a clock counter frequency divider output to determine a duty cycle and/or switching frequency of at least one power switching transistor for an output voltage fixing circuit of a switch mode dc-to-dc converter.
1. An integrated circuit package, comprising:
a semiconductor die of plural separate power supply voltage domains; and
a switch mode dc-to-dc converter, comprising:
wherein said switch mode dc-to-dc converter comprises:
an inductor core and windings;
a power switching transistor; and
an output voltage fixing circuit comprising a digital open-loop means circuit configuration requiring no feed-forward loop and no feedback loop.
0. 32. An integrated circuit package, comprising:
a substrate;
a semiconductor die of plural separate power supply voltage domains mounted on said substrate; and
a switch mode dc-to-dc converter comprising:
a power switching transistor; and
an output voltage fixing circuit configured to retain precision based on power consumption characterization data of said semiconductor die.
0. 27. An integrated circuit package, comprising:
a semiconductor die of plural separate power supply voltage domains; and
a switch mode dc-to-dc converter, comprising:
a power switching transistor; and
an output voltage fixing circuit comprising a digital open-loop circuit configuration that retains precision based on power consumption characterization data of said semiconductor die.
0. 25. A method of design of a power supply for an integrated circuit, comprising:
determining a prior characterization of power consumption over all operating power states, environmental conditions, and process variations of said integrated circuit; and
providing as said power supply an output voltage fixing circuit that retains precision based on said determined power consumption characterization data of said integrated circuit.
12. An integrated circuit package, comprising,
a substrate of fiberglass resin epoxy of type FR4 g based laminate material for mounting: ;
a semiconductor die of plural separate power supply voltage domains mounted on said substrate; and
a switch mode dc-to-dc converter further comprising an inductor core and windings, mounted on said substrate, wherein said switch mode dc-to-dc converter comprises:
a power switching transistor; and
an output voltage fixing circuit comprising a digital open-loop means circuit configuration requiring no feed-forward loop and no feedback loop.
2. An integrated circuit package, comprising:
a semiconductor die of plural separate power supply voltage domains; and
a switch mode dc-to-dc converter, comprising:
wherein said switch mode dc-to-dc converter comprises:
an inductor core and windings;
a power switching transistor; and
an output voltage fixing circuit,
wherein said semiconductor die comprises a decoder that compares an entry from a table corresponding to the present power state of said semiconductor die to a clock counter frequency divider output to determine a duty cycle and/or switching frequency of said power switching transistor for said output voltage fixing circuit.
19. A method for design and fabrication of an integrated circuit package comprising a semiconductor die of plural separate power supply voltage domains with an integrated switch mode power supply, said method comprising steps of :
designing a semi-custom or standard cell library based digital core and obtaining from the design automation tools power consumption estimates in various power states given known clocking rates;
determining switch mode power supply frequency, inductance, and duty cycles for various power states given said power consumption estimates and system clocking;
fabricating said semiconductor die for prototyping purposes, packaged without said integrated switch mode power supply;
characterizing said prototype semiconductor die for power consumption over all operating power states and environmental conditions and process variations;
fabricating said switch mode power supply onto final production substrates; and
bonding and molding or sealing with epoxy said semiconductor die and assembled final power supply substrate into an integrated package.
14. A method for design and fabrication of an integrated circuit package comprising a semiconductor die of plural separate power supply voltage domains with an integrated switch mode power supply, said method comprising steps of :
designing a semi-custom or standard cell library based digital core and obtaining from the design automation tools power consumption estimates in various power states given known clocking rates;
determining switch mode power supply frequency, inductance, and duty cycles for various power states given said power consumption estimates and system clocking;
fabricating said semiconductor die for prototyping purposes, packaged without said integrated switch mode power supply;
characterizing said prototype semiconductor die for power consumption over all operating power states and environmental conditions and process variations;
fabricating said switch mode power supply onto final production substrates;
trimming the output voltage fixing circuit of said switch mode power supply after a probe test to determine the output voltages at given duty cycles versus output currents defined by said semiconductor die known characterization data; and
bonding and molding or sealing with epoxy said semiconductor die and power supply substrate into an integrated package.
3. The integrated circuit of
4. The integrated circuit of
5. The integrated circuit package of
6. The integrated circuit package of
7. The integrated circuit package of
8. The output voltage fixing integrated circuit package of
9. The output voltage fixing integrated circuit package of
10. The integrated circuit package of
11. The output voltage fixing integrated circuit package of
13. The output voltage fixing integrated circuit package of
15. The method of
16. The method of
17. The method of
18. The method of
0. 21. The semiconductor die of
0. 22. The semiconductor die of
0. 23. The semiconductor die of
at least one pad from which to accept a binary number offset for fine tuning said duty cycle and/or switching frequency, wherein said fine tuning operates by modifying said table entry being compared to the clock counter frequency divider output by said output voltage fixing circuit of said dc-to-dc converter.
0. 24. The semiconductor die of
0. 26. The integrated circuit package of
0. 28. The integrated circuit package of
0. 29. The integrated circuit package of
0. 30. The integrated circuit package of
0. 31. The integrated circuit package of
0. 33. The integrated circuit package of
0. 34. The integrated circuit package of
0. 35. The integrated circuit package of
0. 36. The semiconductor die of
0. 37. The semiconductor die of
0. 38. The integrated circuit package of
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1. Field of the Invention
The present invention is generally in the field of semiconductor circuits. More specifically, the present invention is in the field of semiconductor die packaging with integrated power supply voltage regulation.
2. Background Art
Advances in semiconductor integrated circuit fabrication processes and digital standard cell and semi-custom application specific integrated circuit, “ASIC”, design methodologies have given rise to digital and mixed analog and digital signal integrated circuits requiring separate power supplies for various parts including a unique voltage for the digital core power supply, and a second, unique power supply voltage for the input/output pad ring, and possibly a third power supply voltage for miscellaneous analog functions. While this advancement brings the advantage of reduced core power consumption as a product of one-half the total gate capacitances times the gate voltages squared times the switching frequency, there arises the problem of regulation of these additional voltages. With the advent of system-on-chip technologies, designers of these devices have only begun to address this requirement for regulating multiple power supply domains on-chip. Given prior art, it often finally remains the responsibility of the top-level system integrator to provide this variety of power supply voltage domains at the board level and not chip level, obscuring the costs of the total solution implementing the prior art system-on-chip. Often both the system-on-chip designer and the top-level integrator, not having the time, resources, or background of experience in power supply design tend to choose simple-to-implement, but less than optimal linear voltage regulation cores or devices to provide these plural voltage domains from a single supply voltage. When implemented using a linear voltage regulation device, a substantial amount of the power savings realized by accepting a lower core voltage is lost in the form heat dissipated through the linear regulator's transistors, by design. The overall solution cost and power consumption may actually rise if this heat dissipated in the linear voltage regulator is great enough to require additional components to provide forced air convection cooling. Also, the system-on-chip itself could require additional heat-sinking components or else suffer reduced reliability due to the implementation of a linear voltage regulator on-chip, thereby driving-up hidden costs of the total solution.
Therefore, there exists a need for a novel and reliable system and method to provide power to multiple voltage domains of semiconductor dies to overcome the problems faced by conventional semiconductor die packages integrating a linear voltage regulation power supply. More specifically, there exists a need for a novel and reliable system and method to optimally provide power to multiple voltage domains within semiconductor dies while reducing overall system cost, power consumption, and heat dissipation.
The present invention is directed to a system and method for integrating a semiconductor die of plural power supply voltage domains with a switch mode DC-to-DC converter in an integrated circuit package. The invention discloses a system and a method to design and fabricate such an integrated circuit system in a single package to obtain optimal power savings, and minimal heat dissipation and cost. According to one embodiment, a semiconductor die is situated within the periphery of a lead frame adjacent to the switch mode power supply substrate. The substrate can comprise, for example, a ceramic material, or most economically, a fiberglass resin epoxy based laminate material such as FR4. In one embodiment, the semiconductor die is situated on the substrate adjacent to the integrated switch mode DC-to-DC converter. In one embodiment, a semiconductor die may receive power for its lower voltage supply pads through any DC-to-DC converter of the switch mode step-down variety in a closed-loop general solution implementation.
In the preferred embodiment, the present invention provides a superior means for optimally converting voltages to the correct domains for semiconductor die operation through synchronous step-down conversion. Furthermore, the present invention's substantial departure from prior art and significant novelty exists in the preferred embodiment wherein said switch mode synchronous DC-to-DC step-down converter is implemented in an open-loop configuration retaining precision based on semiconductor die power consumption characterization data, thus achieving the lowest possible cost for total solution of the system-on-chip.
FIG. 7 and
From the preceding description of the present invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Furthermore, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would recognize that changes could be made in form and detail without departing from the scope and the spirit of the invention. The described embodiments have been presented in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the previously described particular embodiments, but is capable of many rearrangements, modifications, omissions, and substitutions without departing from the scope of the invention.
Thus, a system and method for integrating a digital core with a switch mode power supply has been described.
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