Dual-addressed rectifier storage device

Abstract

A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed rectifier Storage (DRS) array very scaleable scalable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.

Description

CROSS-REFERENCE TO RELATED APPLICATION

Lanalog toColumnsfor For example, one skilled in the art will recognize that The the Storage Bit Sensing Rectifiers could be connected to the Storage Columns if transistor Q1 was of the PNP type, rectifiers D33, D34, and D35 were reversed in polarity and connected in series to ground instead of to the positive supply, and resistor R9 was connected to the positive supply instead of to ground; in this variation, the collector of transistor Q1 would be a current source instead of a current sink.

In another variation the means of row or column selection by disabling certain rows or columns might be used in combination with other selection means disclosed in the prior or subsequent art. It is believed that Dual-addressed Rectifier Storage Arrays will typically be fabricated as an integrated circuit; a possible layout of the Rows, the Columns, and the rectifiers are shown in FIGS. 6 through 10 (the addressing transistors and resistors, the Row and Column Resistors, and the connection pads to the chip have been omitted for clarity—the fabrication of these devices are well known to those skilled in the art). In FIG. 6, an N-type wafer is shown to be doped with P-type channels which form the Rows. Next (FIG. 7) is shown that an oxide layer is grown and then (FIG. 8) openings corresponding to the rectifiers in the circuit are etched through that oxide layer. The data stored in the device is programmed during this step—wherever a Storage Rectifier is desired, a hole is etched through the oxide layer (it should be noted that the pattern of the openings matches the pattern of the rectifiers as drawn in FIG. 3). FIG. 9 shows the chip with an aluminum metalization layer and finally (FIG. 10) shows the result of etching that aluminum into vertical lines which form the Columns. Wherever the aluminum contacts a doped region through one of the holes in the oxide layer, a rectifier (of the type sometimes referred to as a metal-on-silicon junction type or as a Schottky Diode type) is formed. The N-type wafer substrate would be kept at the most negative voltage in the circuit thereby creating reverse biased p-n junction between the doped regions and the substrate, the result of which is to electrically isolate those generally parallel doped regions. The generally parallel metalized regions which form the Columns are electrically isolated from each other due to their being formed upon the non-conducting oxide layer (except where they contact the doped regions through the holes in the oxide layer). Where the aluminum Columns contact the P-type Rows, a metal-on-silicon junction rectifier is formed such that the current flow (where conventional current flow is the flow of holes, that is to say, current flowing from positive voltage potential to negative voltage potential) is from the doped regions to the metalized regions when the junction is forward biased. As shown in FIG. 10, space is available for the manufacture of the addressing components and the Row and Column Resistive means at the lower left corner of the chip and around the edges.

The addressing components might also be modified when constructing a DRS Array as an integrated circuit. The pair of resistors directly connected between each address input and the bases of the two addressing transistors could be replaced by a single resistor (as shown in FIG. 3, a single resistor could do the job of resistors R10 and R12, a single resistor could do the job of resistors R13 and R15, and so on). Those transistors could be external to the integrated circuit form of the DRS Array.

A variation on the semiconductor manufacturing of a DRS Array might be to dope N-type regions into a P-type wafer thereby reversing the polarity of the metal-on-silicon junction rectifiers (the Rows and the Columns would be reversed). Another variation would spread out the Addressing Columns across the width of the chip—alternating Addressing Columns with one or more Storage Columns—instead of grouping those Addressing Columns at the left side of the chip; this will spread out those Lines lines carrying most of the current in the circuit thereby more evenly distributing the power dissipation across the chip (the same technique could be done with the Rows). Another variation would be to construct the device with p-n junction rectifiers or a combination on metal-on-silicon junction rectifiers and p-n junction rectifiers.

Another variation might enable programming the stored data during the metalization etching step. Referring to FIG. 11, an opening has been etched through the oxide layer at every potential Storage Rectifier location. Programming of the stored data bits is accomplished when the metalization layer is etched. In those locations where a storage Rectifier is desired, a metal connection is left during the metal etching step between the metal pad covering the opening in the oxide layer and the metal Column; where no storage Rectifier is desired, that metal connection is etched away. It is believed that this approach will enable all of the semiconductor manufacturing steps, except the final metal etching step to be performed and that wafers so made could be stored safely under the protective metalized layer. In this way, wafers could be mass produced without regard to the data to be stored in the chip.

Economic concerns may drive several other possible variations on the semiconductor manufacturing of a DRS Array. It is expected that a significant part of the cost to manufacture these devices will be in the packaging where the greater the number of electrical connections between the package and the controlling device, the greater the cost of that packaging; a package with more leads will be more expensive and more prone to mechanical failures. As a result, it is believed that steps will be taken to reduce the number of package leads needed. One skilled in the art will quickly realize the circuitry needed to implement any of the following variations. One possibility would be to address the lower address lines directly but to retain the higher address lines internally; in other words, the latch shown in FIG. 2 would be incorporated into the DRS Array integrated circuit. Another possibility would be to incorporate a shift-register where the address bits would be shifted into the device serially and retained thereby reducing the number of addressing leads to two (the shift-register serial input and the shifting-clock). However, a more practical variation, shown in FIG. 14, might be to incorporate both a counter and a shift register where the shift register would be used to enter an address onto the chip which could then be loaded into the counter. In this last variation of the serially loaded counter, the address would be retained within the counter so the many address lines are essentially reduced to four: one for the serial address input (S), one for clocking the shift register (K), one for clocking the counter (C), and one for loading the address into the counter from the shift register (L). One skilled in the art will quickly realize the circuitry needed to implement any of these variations. One well skilled in the art will recognize that a reduction to three lines can be achieved here resulting in a total of six connections to the chip (three plus power, ground, and data out).

Finally, a variation on the digital logic device comprising one or more DRS Arrays of which one or more may be removable which themselves comprise the above mentioned serially loaded counter logic. By limiting the manufacture of such devices to having output in analog format only, the risks to the makers of programming (e.g., music and video programs) will be reduced. With CD-ROM technology, the output from some CD-ROM readers is in a digital format. As a result, any copy made will be of the same quality as the original. This potentially results in significant lost revenue as the users of this technology could casually make copies for friends and relatives that cannot be distinguished from the originals (this was not the case with prior technologies such as cassette tapes and video tapes where each successive copy degraded somewhat). By limiting the manufacture of devices comprising DRS Arrays that are addressed via serially loaded counters to analog output only, the same degradation of copies will occur thereby reducing some of the risks to the makers of programming by causing the copies to be less desirable than the originals. While devices comprising DRS Arrays that are addressed via serially loaded counters could be limited to analog output only, they could still include means for reading DRS Arrays in other formats (i.e., DRS Arrays directly addressed via many address lines), however, devices comprising DRS Arrays that are directly addressed via many address lines and which give digital access to the information stored therein would not include means for reading DRS Arrays that are addressed via serially loaded counters.

It is believed that minor flaws in the semiconductor wafer will mostly impact the operation of the metal-on-silicon junction rectifiers when they are reverse biased by lowering the reverse breakdown voltage. Since the DRS Arrays are expected to be operated at low voltage levels, large reverse voltages are considered unlikely in normal operation. As a result, the impact of these minor flaws are not expected to impact the operation of the device and high device manufacturing yields are anticipated. However, the addressing transistors will likely be adversely affected by such flaws. There will likely be a trade-off between the increased cost of manufacture resulting from lowered device yields (as a result of the impact of semiconductor flaws on the increased complexity of the addressing circuit) and the savings on packaging (as a result of reducing the number of device leads).

The selection of a line by disabling all undesired lines could be utilized in many related electronic devices. The rectifiers at the storage locations could be fabricated as Light Emitting Diodes (LED's) with such a rectifier present at every storage location. In this way, the device could be used as a display panel where a given display pixel could be turned on by selecting that bit location; the display panel would be scanned, selecting and illuminating bit locations in sequence while skipping bit locations that are to remain dark. Also, using a technique such as pulse width modulation, which is well known to one skilled in the art, one could even control the duration of a pulse of light emitted at any given pixel location and thereby control the perception of the intensity of the light emitted.

The high expected storage densities come from the symmetry of the design—the Storage Bit Sensing Rectifiers, The the Addressing Rectifiers, and the Storage Rectifiers are all constructed in the same way. The result of this is that they can all be made at the same time with the same semiconductor manufacturing steps. By using metal-on-silicon junction rectifiers, the primary components in the circuit are essentially constructed vertically on the semiconductor's surface instead of horizontally as might conventionally be done resulting in a very efficient use of the semiconductor “real estate”. The scaling up of the device is expected to be easily accomplished. For example, on a one inch square chip, if the Anode Lines and the Cathode Lines are placed at roughly 0.45 micron center to center spacing, then a DRS Array that is roughly 65,536 by 65,536 Lines could be made. This is the equivalent of about 4,294,967,296 bits or about 536,870,912 bytes or about the capacity of a present day CD ROM. State of the art technology at the time of this writing is below 1 micron line widths. It is envisioned that the present invention could be used anywhere that one would use a CD-ROM drive or player or anywhere a large amount of information is needed.

The foregoing description of an example of the preferred embodiment of the invention and the variations thereon have been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

1. A digital logic device comprising one or more electronic information storage means, and addressing means for accessing said storage means, wherein each said electronic information storage means comprises:

a plurality of generally parallel conductive means;

a second plurality of generally parallel conductive means that is generally perpendicular to and overlapping with the first said plurality of generally parallel conductive means;

a plurality of bits of potential information storage where a bit of said plurality of bits is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of generally parallel conductive means with each conductive means of the second said plurality of generally parallel conductive means, and where the state of any said bit is determined by the presence or absence of a rectifying conductive means at each said general vicinity of said point of intersection;

means for selecting a conductive means of one plurality of generally parallel conductive means, and means for biasing the generally parallel conductive means of the other plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means to a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased;

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled; and

2. The digital logic device of claim 1, wherein said means for selecting a conductive means of one plurality of generally parallel conductive means comprises:

means for biasing the generally parallel conductive means of the said one plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled.

3. The digital logic device of claim 1, further comprising means for detecting a conducted current through said rectifying conductive means if present at said point of intersection.

4. The digital logic device circuit of claim 1 31, wherein one of said plurality of generally parallel conductive means the sets of conductive lines is a plurality of generally parallel doped regions within a semiconductor material.

5. The digital logic device circuit of claim 4 31, wherein the other of said plurality of generally parallel conductive means one of the sets of conductive lines is a plurality of generally parallel metalized regions.

6. The digital logic device circuit of claim 1 31, wherein said addressing means circuitry comprises means circuitry to sequentially select addressed storage locations.

7. The digital logic device circuit of claim 1 31, wherein said addressing means circuitry comprises means circuitry to randomly select addressed storage locations.

8. The digital logic device circuit of claim 1 31, further comprising display means for displaying alphanumeric or graphic information to its a user.

9. The digital logic device circuit of claim 1 31, further comprising input means to enable its user to alter its operation.

10. The digital logic device circuit of claim 1 31, wherein part or all of said one more electronic storage means are circuit is removable or replaceable.

11. The digital logic device circuit of claim 1 31, wherein output from the device circuit is in a digital format.

12. The digital logic device circuit of claim 1 31, wherein output from the device circuit is in an analog format.

13. The digital logic device circuit of claim 1 31, wherein output from the device circuit is in either a digital format or an analog format.

14. An electronic information storage device comprising:

a plurality of generally parallel conductive means;

a second plurality of generally parallel conductive means that is generally perpendicular to and overlapping with the first said plurality of generally parallel conductive means;

a plurality of bits of potential information storage where a bit of said plurality of bits is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of generally parallel conductive means and each conductive means of the second said plurality of generally parallel conductive means, and where the state of any said bit is determined by the presence or absence of a rectifying conductive means at each said general vicinity of said point of intersection;

means for selecting a conductive means of one plurality of generally parallel conductive means, and means for biasing the generally parallel conductive means of the other plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled.

15. The storage device of claim 14, wherein said means for selecting a conductive means of one plurality of generally parallel conductive means comprises:

means for biasing the generally parallel conductive means of the said one plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled.

16. The storage device of claim 14, further comprising means for detecting a conducted current through said rectifying conductive means if present at said point of intersection.

17. The storage device of claim 14, wherein one of said plurality of generally parallel conductive means is a plurality of generally parallel doped regions within a semiconductor material.

18. The storage device circuit of claim 17 5, wherein said rectifying conductive means between said plurality of generally parallel doped regions and a plurality of generally parallel metalized regions is nonlinear elements are of the metal-on-semiconductor junction type.

19. The storage device circuit of claim 17 5, wherein said rectifying conductive means between said plurality of generally parallel doped regions and a plurality of generally parallel metalized regions is nonlinear elements are of the p-n junction type.

20. The storage device of claim 14, wherein one of said plurality of generally parallel conductive means is a plurality of generally parallel metalized regions.

21. The storage device circuit of claim 14 31, wherein said rectifying conductive means is comprised by a transistor as the base-emitter junction nonlinear elements comprise base-emitter junctions of transistors.

22. The storage device circuit of claim 14 31, further comprising means for retaining the address of the information to be accessed.

23. The storage device circuit of claim 22, further comprising means for incrementing the retained address.

24. The storage device circuit of claim 22, further comprising means for setting the retained address.

25. An electronic information storage device comprising a plurality of storage means where each storage means comprises:

a plurality of generally parallel conductive means;

a second plurality of generally parallel conductive means that is generally perpendicular to and overlapping with the first said plurality of generally parallel conductive means;

a plurality of bits of potential information storage where a bit of said plurality of bits is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of generally parallel conductive means and each conductive means of the second said plurality of generally parallel conductive means, and where the state of any said bit is determined by the presence or absence of a rectifying conductive means at each said general vicinity of said point of intersection;

means for selecting a conductive means of one plurality of generally parallel conductive means, and means for biasing the generally parallel conductive means of the other plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled;

26. The storage device of claim 25, wherein said means for selecting a conductive means of one plurality of generally parallel conductive means comprises:

means for biasing the generally parallel conductive means of the said one plurality of generally parallel conductive means such that each said rectifying conductive means present between a conductive means of said biased plurality of generally parallel conductive means and a conductive means of the other said plurality of generally parallel conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of generally parallel conductive means by shifting the voltage of those biased conductive means that are to be disabled.

27. A semiconductor information storage device comprising:

a plurality of generally parallel conductive means;

a second plurality of generally parallel conductive means that is generally perpendicular to and overlapping with the first said plurality of generally parallel conductive means where one of said two pluralities of generally parallel conductive means is generally a surface layer of the semiconductor; and

a plurality of bits of potential information storage where a bit of said plurality of bits is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of generally parallel conductive means and each conductive means of the second said plurality of generally parallel conductive means, and where the state of any said bit is determined by the presence or absence of a rectifying conductive means at each said general vicinity of said point of intersection, and where any said presence or absence of a rectifying conductive means is determined by the leaving in place or the removal, respectively, of a portion of the surface layer conductive means.

28. An electronic array of selectable points comprising:

a plurality of conductive means;

a second plurality of conductive means;

a plurality of selectable points where a point of said plurality of selectable points is present in the general vicinity of each point of intersection of each conductive means of the first said plurality of conductive means and each conductive means of the second said plurality of conductive means;

means for selecting a conductive means of one plurality of conductive means, and means for biasing the conductive means of the other plurality of conductive means such that each said selectable point present between a conductive means of said biased plurality of conductive means and a conductive means of the other said plurality of conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of conductive means by shifting the voltage of those biased conductive means that are to be disabled.

29. The electronic array of selectable points of claim 28, wherein said means for selecting a conductive means of one plurality of generally parallel conductive means comprises:

means for biasing the conductive means of the said one plurality of conductive means such that each said selectable point present between a conductive means of said biased plurality of conductive means and a conductive means of the other said plurality of conductive means is potentially forward biased; and

means for selecting a biased conductive means by electronically disabling conductive means within said biased plurality of conductive means by shifting the voltage of those biased conductive means that are to be disabled.

30. The electronic array of selectable points of claim 28, wherein said each selectable point comprises a light emitting diode (LED) which will emit light when forward biased.

31. An information-storage circuit, the circuit comprising:

first and second sets of conductive lines overlapping with each other and defining storage locations at overlap regions;

a pattern of information-defining nonlinear elements, each nonlinear element connected to the first and second sets of conductive lines at an overlap region, presence or absence of a nonlinear element connection at a storage location defining a bit state at the location; and

address circuitry comprising a first pattern of rectifiers directly connected between the first set of conductive lines and a first set of address signal lines, application of an address to the first set of address signal lines causing the first pattern of rectifiers to disable all but one of the first set of conductive lines.

32. The circuit of claim 31 further comprising sensing circuitry for sensing the presence or absence of an information-defining nonlinear element connected to the selected one of the first set of conductive lines and at least a selected one of the second set of conductive lines to thereby determine the bit state at each storage location defined by selected conductive lines.

33. The circuit of claim 32 wherein the sensing circuitry is configured to sense current when said information-defining nonlinear element is not connected to the selected one of the first set of conductive lines and the selected one of the second set of conductive lines.

34. The circuit of claim 33 wherein the sensing circuitry comprises an output line connected to each of the first set of conductive lines by a sensing nonlinear element.

35. The circuit of claim 34 wherein the address circuitry comprises a first set of selectable disabling lines fewer in number than and connected to the first set of conductive lines by the first pattern of rectifiers, and circuitry for applying a second voltage to at least some of the first set of disabling lines to thereby disable all but one of the first set of conductive lines, the information-storage circuit further comprising additional address circuitry which itself comprises (i) a second set of selectable disabling lines fewer in number than and connected to the second set of conductive lines by a second pattern of rectifiers, and (ii) circuitry for applying a first voltage to at least some of the second set of disabling lines to thereby disable all but one of the second set of conductive lines, all of the rectifiers having a threshold activation voltage associated therewith, application of the threshold activation voltage across the rectifiers allowing current to flow therethrough.

36. The circuit of claim 35 further comprising a first series of voltage-drop elements connecting the first set of conductive lines to a circuitry for applying a first voltage and a second series of voltage drop elements connecting the second set of conductive lines to a circuitry for applying a second voltage.

37. The circuit of claim 36 wherein the first and second series of voltage drop elements are resistors.

38. The circuit of claim 36 wherein the first and second series of voltage drop elements are nonlinear elements.

39. The circuit of claim 38 wherein the nonlinear elements are rectifiers.

40. The circuit of claim 39, wherein the first and second sets of conductive lines are disposed on an integrated circuit chip, and the circuitry for applying the first voltage and the circuitry for applying the second voltage are disposed off of the integrated circuit chip and connected thereto.

41. The circuit of claim 36 wherein the second voltage is approximately a ground voltage.

42. The circuit of claim 32 further comprising a first series of voltage-drop elements connecting the first set of conductive lines to a circuitry for applying a first voltage and a second series of voltage drop elements connecting the second set of conductive lines to a circuitry for applying a second voltage.

43. The circuit of claim 42 wherein the first and second series of voltage drop elements are resistors.

44. The circuit of claim 42 wherein the first and second series of voltage drop elements are nonlinear elements.

45. The circuit of claim 44 wherein the nonlinear elements are rectifiers.

46. The circuit of claim 45, wherein the first and second sets of conductive lines are disposed on an integrated circuit chip, and the circuitry for applying the first voltage and the circuitry for applying the second voltage are disposed off of the integrated circuit chip and connected thereto.

47. The circuit of claim 42 wherein the second voltage is approximately a ground voltage.

48. The circuit of claim 31 wherein the all but one of the first set of conductive lines is disabled by shifting a voltage thereon.

49. The circuit of claim 31 further comprising additional address circuitry for disabling all but a selected one of the second set of conductive lines.

50. The circuit of claim 49 wherein the all but one of the second set of conductive lines is disabled by shifting a voltage thereon.

51. The circuit of claim 49 wherein:

the information-defining nonlinear elements have a threshold activation voltage associated therewith;

the address circuitry comprises circuitry for setting all but the selected one of the first set of conductive lines to a first voltage; and

the additional address circuitry comprises circuitry for setting all but the selected one of the second set of conductive lines to a second voltage, the first and second voltages differing by at least the threshold activation voltage.

52. The circuit of claim 51 wherein:

the address circuitry further comprises a first set of selectable disabling lines fewer in number than and connected to the first set of conductive lines by the first pattern of rectifiers, and circuitry for applying a third voltage to at least some of the first set of disabling lines to thereby disable all but one of the first set of conductive lines; and

the additional address circuitry further comprises a second set of selectable disabling lines fewer in number than and connected to the second set of conductive lines by a second pattern of rectifiers, and circuitry for applying a fourth voltage to at least some of the second set of disabling lines to thereby disable all but one of the second set of conductive lines.

53. The circuit of claim 52 wherein the third voltage is substantially equal to the second voltage and the fourth voltage is substantially equal to the first voltage.

54. The circuit of claim 53 wherein all of the rectifiers have said threshold activation voltage associated therewith, application of the threshold activation voltage across the rectifiers allowing current to flow therethrough.

55. The circuit of claim 54 wherein all of the nonlinear elements are rectifiers having an associated voltage drop corresponding to the threshold activation voltage, the first and second voltages differing by at least the rectifier voltage drop.

56. The circuit of claim 51 wherein the information-defining nonlinear elements are rectifiers having an associated voltage drop corresponding to the threshold activation voltage, the first and second voltages differing by at least the rectifier voltage drop so that an information-defining rectifier, if connected to the selected conductive lines, is forward biased.

57. The circuit of claim 51 wherein the second voltage is approximately a ground voltage.

58. The circuit of claim 31 further comprising a first series of voltage-drop elements connecting the first set of conductive lines to a circuitry for applying a first voltage and a second series of voltage drop elements connecting the second set of conductive lines to a circuitry for applying a second voltage.

59. The circuit of claim 58 wherein the first and second series of voltage drop elements are resistors.

60. The circuit of claim 58 wherein the first and second series of voltage drop elements are nonlinear elements.

61. The circuit of claim 60 wherein the nonlinear elements are rectifiers.

62. The circuit of claim 61, wherein the first and second sets of conductive lines are disposed on an integrated circuit chip, and the circuitry for applying the first voltage and the circuitry for applying the second voltage are disposed off of the integrated circuit chip and connected thereto.

63. The circuit of claim 58 wherein the second voltage is approximately a ground voltage.

64. The circuit of claim 31 wherein the circuit operates as a random access memory.

65. The circuit of claim 31 wherein the circuit operates as a read only memory.

66. The circuit of claim 31 wherein the circuit operates as a one-time-programmable read only memory.