There is disclosed a semiconductor device having an MOS gate for reducing variations in threshold voltage (Vth) with time wherein a surface protective film is not formed in a device area including channels but only in a device peripheral area, thereby reducing the amount of hydrogen atoms migrating to a silicon-silicon oxide interface in a cell area and, accordingly, reducing the number of Si—H chemical bonds at the interface.
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1. A semiconductor device comprising:
a first semiconductor layer having a first doping state of a first conductivity type and having first and second major surfaces;
a first semiconductor region of a second conductivity type formed selectively in said first major surface of said first semiconductor layer so that said first semiconductor layer is exposed in remains in the first doping state along a peripheral portion of said first major surface, and said first semiconductor layer is exposed in remains in the first doping state in the a form of an insular region in a planar view in a central portion of said first major surface;
a second semiconductor region of the first conductivity type formed in a surface of said first semiconductor region, with a channel region provided between said second semiconductor region and said insular region of said first semiconductor layer;
a gate insulating film formed on a surface of said channel region;
a first gate electrode from a plurality of gate electrodes formed on said gate insulating film;
an interlayer insulating film formed at least on said first gate electrode;
a first main electrode formed over a surface of said interlayer insulating film and covering a surface of said second semiconductor region, said first main electrode being electrically connected to said second semiconductor region and having an end extending to a boundary between the peripheral portion of said first major surface and the central portion of said first major surface;
a second main electrode formed on said second major surface of said first semiconductor layer; and
an integral semi-insulating plasma cvd nitride film covering at least the peripheral portion of said first major surface other than the central portion of said first major surface and not extending to an upper portion of said first gate above any gate electrode, said integral semi-insulating plasma cvd nitride film having a conductivity which does not lose function as an insulating film and stabilizes breakdown voltage characteristics of the semiconductor device.
12. A semiconductor device comprising:
a first semiconductor layer having a first doping state of a first conductivity type and having first and second major surfaces;
at least one first semiconductor region of a second conductivity type formed selectively in said first major surface of said first semiconductor layer so that said first semiconductor layer is exposed in remains in the first doping state along a peripheral portion of said first major surface, and said first semiconductor layer is exposed in region remains in the first doping state in the a form of a plurality of insular regions in a planar view in a central portion of said first major surface;
a plurality of second semiconductor regions of the first conductivity type formed in a surface of said at least one first semiconductor region, with channel regions provided between said second semiconductor regions and said insular regions of said first semiconductor layer;
a gate insulating film formed on a surface of said channel regions;
a first gate electrode from a plurality of gate electrodes formed on said gate insulating film;
an interlayer insulating film formed at least on said first gate electrode;
a first main electrode formed over a surface of said interlayer insulating film and covering a surface of said second semiconductor region, said first main electrode being electrically connected to said plurality of second semiconductor regions, said first main electrode further having an end extending to a boundary between the peripheral portion of said first major surface and the central portion of said first major surface;
a second main electrode formed on said second major surface of said first semiconductor layer; and
an integral semi-insulating plasma cvd nitride film for covering at least the peripheral portion of said first major surface other than the central portion of said first major surface and not extending to an upper portion of said first gate above any gate electrode, said integral semi-insulating plasma cvd nitride film having a conductivity which does not lose function as an insulating film and stabilizes breakdown voltage characteristics of the semiconductor device.
2. The semiconductor device of
said plasma cvd nitride film extends from the peripheral portion of said first major surface to a surface of said first main electrode at said end.
3. The semiconductor device of
a second gate electrode from the plurality of gate electrodes not covered with said first gate main electrode; and
a gate interconnection line formed selectively on a surface of said second gate electrode,
wherein a trench is formed between said first main electrode and said gate interconnection line for electrical isolation between said first main electrode and said gate interconnect line, and
wherein said first gate electrode and said second gate electrode are integrally formed and electrically connected by said gate interconnection line to each other.
4. The semiconductor device of
said plasma cvd nitride film further extends from a surface of said gate interconnection line through said trench to a portion of a surface of said first main electrode.
5. The semiconductor device of
said plasma cvd nitride film is a semi-insulation film having a conductivity ranging from 1×10−14 to 1×10−10 (1/Ωcm).
6. The semiconductor device of
said plasma cvd nitride film is a semi-insulation film having a conductivity ranging from 1×10−13 to 1×10−11 (1/Ωcm).
7. The semiconductor device of
a second semiconductor layer of the second conductivity type formed between said second major surface of said first semiconductor layer and said second main electrode.
8. The semiconductor device of
a second gate electrode from the plurality of gate electrodes not covered with said first main electrode; and
a gate interconnection line formed selectively on a surface of said second gate electrode,
wherein a trench is formed between said first main electrode and said gate interconnection line for electrical isolation between said first main electrode and said gate interconnect line, and
wherein said first gate electrode and said second gate electrode are integrally formed and electrically connected by said gate interconnection line to each other.
9. The semiconductor device of
said surface protective film plasma cvd nitride film further extends from a surface of said gate interconnection line through said trench to a portion of a surface of said first main electrode.
10. The semiconductor device of
said plasma cvd nitride film is a semi-insulation film having a conductivity ranging from 1×10−14 to 1×10−10 (1/Ωcm).
11. The semiconductor device of
said plasma cvd nitride film is a semi-insulation film having a conductivity ranging from 1×10−13 to 1×10−11 (1/Ωcm).
13. The semiconductor device of
said plasma cvd nitride film extends from the peripheral portion of said first major surface to a surface of said first main electrode at said end.
14. The semiconductor device of
a second gate electrode from the plurality of gate electrodes not covered with said first main electrode; and
a gate interconnection line formed selectively on a surface of said second gate electrode,
wherein a trench is formed between said first main electrode and said gate interconnection line for electrical isolation between said first main electrode and said gate interconnect line, and
wherein said first gate electrode and said second gate electrode are integrally formed and electrically connected by said gate interconnection line to each other.
15. The semiconductor device of
said plasma cvd nitride film further extends from a surface of said gate interconnection line through said trench to a portion of a surface of said first main electrode.
16. The semiconductor device of
said plasma cvd nitride film is a semi-insulation film having a conductivity ranging from 1×10−14 to 1×10−10 (1/Ωcm).
17. The semiconductor device of
said plasma cvd nitride film is a semi-insulation film having a conductivity ranging from 1×10−13 to 1×10−11 (1/Ωcm).
18. The semiconductor device of
a second semiconductor layer of the second conductivity type formed between said second major surface of said first semiconductor layer and said second main electrode.
19. The semiconductor device of
a second gate electrode from the plurality of gate electrodes not covered with said first main electrode; and
a gate interconnection line formed selectively on a surface of said second gate electrode,
wherein a trench is formed between said first main electrode and said gate interconnection line for electrical isolation between said first main electrode and said gate interconnect line, and
wherein said first gate electrode and said second gate electrode are integrally formed and electrically connected by said gate interconnection line to each other.
20. The semiconductor device of
said plasma cvd nitride film further extends from a surface of said gate interconnection line through said trench to a portion of a surface of said first main electrode.
21. The semiconductor device of
said plasma cvd nitride film is a semi-insulation film having a conductivity ranging from 1×10−14 to 1×10−10 (1/Ωcm).
22. The semiconductor device of
said plasma cvd nitride film is a semi-insulation film having a conductivity ranging from 1×10−13 to 1×10−11 (1/Ωcm).
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1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the invention relates to a device structure for reducing variations in threshold voltage Vth of a power semiconductor device having an MOS gate with time to stabilize electrical characteristics, and a method of fabricating the same.
2. Description of the Background Art
In
The reference numeral 5 designates a P+ base layer; 6 designates an N+ emitter layer; 7 designates a gate insulating film made of silicon oxide; 8 designates a gate electrode of polysilicon; 9 designates a gate interconnection line of Al; 10 designates an emitter electrode; 11 designates guard rings; 12 designates a passivation film for isolation between the gate electrode 8 and the emitter electrode 10; 13 designates an emitter wire bonding region; 14 designates a surface protective film of silicon nitride for covering the IGBT surface except the emitter wiring bonding region 13 and a gate bonding pad (not shown) which is a part of the gate interconnection line designates and 161 designate a silicon oxide film; 17 designates a polysilicon film; 18 designates a passivation film; and 19 designates a collector electrode serving as a second main electrode.
Referring to
As the number of channels opposed to the gate electrode 8 increases, gate potentials opposed to the respective channels are not necessarily uniform in the gate electrode 8. To provide uniform gate potentials, the gate interconnection line 9 of aluminum is provided to connect the portions of the gate electrode 8 opposed to the respective channels (FIGS. 1 and 2). The gate interconnection line 9 extends to the center of the device and is connected to a gate bonding pad (not shown) in the center of the device. Connection lines to the exterior are bonded to the gate bonding pad. An area in which the gate interconnection line 9 and the bonding pad are provided is a gate wiring area 32.
The emitter electrode 10 is formed on the surface of the gate electrode 8 except the portion where the gate interconnection line 9 is formed, with the passivation film 12 formed therebetween. The emitter electrode 10 short-circuits the P+ base layer 5 and the N+ emitter layer 6 on the surface of the semiconductor body 4 and is electrically isolated from the gate interconnection line 9 by a trench. An area in which the emitter electrode 10 is formed is a cell area 31 (FIGS. 1 and 2).
The N− layer 3 is exposed in a peripheral portion surrounding the surface of the semiconductor body 4. The peripheral portion generally corresponds to a device peripheral area 30 on the surface of the semiconductor body 4 other than the gate wiring area 32 and the cell area 31.
The plurality of annular guard rings 11 are formed in the N− layer 3 in the peripheral portion to surround the outer periphery of the cell area 31. The channel stopper 15 which is an N+ diffusion region is formed on the outermost edge of the N− layer 3 in the peripheral portion to surround the guard rings 11. The inner periphery of the channel stopper 15 is adapted such that the channel stopper 15 are generally equally spaced from the outermost guard ring 11 over the entire circumference. The surface protective film 14 which is a semi-insulation film of silicon nitride directly covers the surface of the channel stopper 15, and covers the surfaces of the N− layer 3 in the peripheral portion and the outer peripheral portion of the P+ base layer 5, with the silicon oxide film 16 and passivation film 18 formed therebetween. The surface protective film 14 is integrally formed such that an inner peripheral end thereof overlapping and covering the outer peripheral portion of the emitter electrode 10 and an outer peripheral end thereof extends to the outer end of the channel stopper 15 to prevent the surface of the passivation film 18 from being exposed. An area in which the surface protective film 14 is formed is the device peripheral area 30.
An MOSFET is similar in construction to the IGBT except that the MOSFET does not include the P+ substrate 1 of the IGBT. That is, the MOSFET is constructed such that the P+ substrate 1 of the IGBT is removed and the N+ layer 2 of the IGBT is replaced with an N+ substrate on which a drain electrode is formed.
A method of fabricating a semiconductor device will now be described hereinafter.
Referring to FIG. 5 and
The silicon oxide film 16 is formed on the surface of the semiconductor body 4 and is then etched by photolithography, and the P wells and the P+ base layer 5 are formed by diffusion (FIG. 7).
The oxide film 16 is then etched, if necessary, after photolithography process, and the gate insulating film 7 and silicon oxide film 161 of silicon oxide is are formed by thermal oxidation. The gate electrode 8 of polysilicon is formed on the surface of the gate insulating film 7 after photolithography process (FIG. 8).
Photolithography process and thermal diffusion process are performed to form the N+ emitter layer 6 in the P+ base region 5 and the channel stopper 15 in the peripheral portion surface of the N− layer 3 (FIG. 9).
The passivation films 15 12 and 18 of PSG are formed on the top surface, and electrode contact portions are etched (FIG. 10).
The gate interconnection line 9 and the emitter electrode 10 are formed by Al—Si sputtering (FIG. 11).
For the IGBT, radiation for lifetime control and heat treatment for elimination of distortion generated in portions subjected to the radiation are performed, and the surface protective film 14 is formed on the device top surface. The order of the process steps is the feature of the method of fabricating the IGBT according to the present invention.
Specifically, according to the present invention, the radiation for lifetime control is performed first. Then the heat treatment is performed to eliminate the distortion generated in the portions subjected to the radiation. Finally, the surface protective film 14 is formed on the top surface of the device.
The heat treatment for distortion elimination is performed, for example, at a temperature of about 300 to 400° C. The final P-CVD process in an atmosphere of a mixed silane-ammonia gas is performed at a temperature slightly lower than the heat treatment temperature for distortion elimination. The film may be formed at a temperature of about 300° C. with the current state of the art.
To form the surface protective film 14, a semi-insulation silicon nitride film is formed over the device surface by the P-CVD process, and a mask is formed by photolithography, and then plasma etching is performed in an atmosphere of CF4 and O2 to remove the silicon nitride film in the cell area 31 centrally of the device and in the gate wiring area 32 is removed, with the silicon nitride film left only in the device peripheral area 30. This completes the fabrication process (FIG. 12).
In the above described method, the radiation for lifetime control, the heat treatment for distortion elimination, and the step of leaving the silicon nitride film only in the device peripheral area 30 by the P-CVD process are carried out in this order. Only the arrangement in which the silicon nitride film is left only in the device peripheral area 30 can considerably reduce the variations in threshold voltage Vth. Thus, the above-described process may be replaced with a process of forming the electrode by Al—Si sputtering (FIG. 11), forming the semi-insulation silicon nitride film only in the device peripheral area 30 by the P-CVD process, performing the radiation for lifetime control, and then performing the heat treatment for distortion elimination.
Such a method can provide an electrically highly stable IGBT with a satisfactory breakdown voltage characteristic by using a conventional fabrication line without a new fabrication line.
A method of fabricating an MOSFET is similar to the method of fabricating the IGBT except that the radiation for lifetime control and the heat treatment for distortion elimination are not performed.
Operation will be described below.
The above stated IGBT according to the present invention includes the semi-insulation silicon nitride film formed by the P-CVD process only in the device peripheral area 30 other than the gate wiring area 32 and cell area 31. Hydrogen atoms to be bonded to dangling bonds at the silicon-silicon oxide interface are contained only in the silicon nitride film in the device peripheral area 30. The hydrogen atoms, if moved, migrate to the silicon-silicon oxide interface under the surface protective film 14, and fewer hydrogen atoms migrate up to the cell area 31. This decreases the number of hydrogen atoms bonded to the dangling bonds at the silicon-silicon oxide interface in the channel regions under the gate electrode 8 in the cell area 31 and, accordingly, reduces the number of Si—H chemical bonds generated at the silicon-silicon oxide interface, to prevent an unstable interface state. Therefore, the phenomenon in which the threshold voltage Vth varies over a long time period and requires long time to be saturated is difficult to occur.
Operation of the MOSFET is similar to that of the IGBT when the silicon nitride film is formed only in the device peripheral area 30.
For the IGBT, the radiation for lifetime control and the heat treatment for distortion elimination are essential. If the formation of the silicon nitride film by the P-CVD process after the two process steps increases the number of defects at the silicon-silicon oxide interface due to the radiation to increase the dangling bonds, the subsequent heat treatment reduces the number of defects at the silicon-silicon oxide interface to reduce the number of dangling bonds and, accordingly, the number of Si—H chemical bonds generated at the silicon-silicon oxide interface, preventing the unstable interface state. The influence of the radiation is eliminated, and the acceleration of the Vth variations due to the radiation is difficult to occur.
The use of the semi-insulation silicon nitride film as the surface protective film 14 causes a slight current to flow between the emitter and channel stopper to produce an electric field shield effect in the device peripheral area 30. This provides a shield against external impurity ions, to improve the breakdown voltage characteristic of the device. For example, an IGBT having a breakdown voltage as high as 1700 V requires the electric field shield effect using the semi-insulation silicon nitride film.
To simply examine the evaluation of the Vth variations for an MIS structure (metal insulator semiconductor structure) as the premise of the present invention, a C-V test (capacitance-voltage test) was performed under various conditions.
In
The C-V test employs the test piece as above described for measuring a voltage and capacitance between the aluminum electrode 41 and the N-type silicon layer 43, with the voltage varied, to determine a flat-band voltage VFB between the thermal oxidation film 42 and the N-type silicon layer 43. There is a correlation between the flat-band voltage VFB and the threshold voltage Vth. The value of variation ΔVFB of the flat-band voltage VFB is determined under various conditions such as the presence/absence of the surface protective film 40 of the test piece and processing conditions. On the basis of the value ΔVFB is evaluated and examined the value of variation ΔVth of the threshold voltage Vth of the surface protective film 14 of a device having an MOS gate.
As the test piece for the C-V test was used a (100) crystal plane oriented N-type silicon on which was formed a silicon thermal oxidation film of about 1000 Å in thickness, with aluminum sputtered on the surface thereof for use as an electrode. After the aluminum electrode 41 was formed, the surface protective film 40 was formed. A P-CVD nitride film containing a large amount of hydrogen atoms and an LP-CVD oxide film containing a small amount of hydrogen atoms were selected as the surface protective film 40. For hydrogen sintering, heat treatment was performed in a high-temperature furnace in an atmosphere of hydrogen at a temperature of 400° C. for 30 minutes. The radiation is an electron beam irradiation which is a conventional IGBT carrier lifetime control process, followed by heat treatment for distortion elimination.
TABLE 1
ΔVth
radiation
(normal-
hydrogen
& heat
ization
judge-
spec.
protective film
sintering
treatment
value)
ment
A
no film
not done
not done
0.10
∘
B
LP-CVD oxide film
not done
not done
0.10
∘
C
P-CVD nitride film
not done
not done
0.50
Δ
D
no film
done
not done
0.45
Δ
E
LP-CVD oxide film
not done
done
0.10
∘
F
P-CVD nitride film
not done
done
1.00
x
G
no film
done
done
0.90
x
H
hydrogen sintering after
0.10
∘
radiation & heat treatment
Table 1 illustrates the conditions and results of the C-V test.
Additional explanation of Table 1 will be described below.
Referring to
Therefore, it will be understood that:
An electrically highly stable MOSFET with a satisfactory breakdown voltage characteristic is accomplished by the provision of the surface protective film 14 which is the semi-insulation silicon nitride film formed by the P-CVD process only in the device peripheral area 30 other than the gate wiring area 32 and the cell area 31.
Referring to
It will be appreciated from the graph of
Second Preferred Embodiment
Referring to
The emitter electrode 10 is electrically isolated from the gate interconnection line 9 by a narrow trench. The emitter electrode 10 and the gate interconnection line 9 which are Al—Si sputtering film are easily scratched, for example, when the semiconductor device is handled by a handling device during the fabrication process, resulting in shorting of the emitter electrode 10 and the gate interconnection line 9. However, such a failure is prevented by the surface protective film 14 extending to the surface of the narrow trench. In addition, since there is no channel regions serving as cells under the gate wiring area 32, the covering of the semi-insulation surface protective film 14 of silicon nitride formed by the P-CVD process and containing a large amount of hydrogen atoms does not cause the Vth variations. Therefore, an electrically highly stable IGBT is accomplished, with shorting of the emitter electrode 10 and the gate interconnection line 9 being prevented, like the first preferred embodiment.
Further, an electrically highly stable MOSFET is accomplished, with shorting of the emitter electrode 10 and the gate interconnection line 9 being prevented, like the first preferred embodiment by the provision of the surface protective film 14 in the gate wiring area 32 and the device peripheral area 30 of the MOSFET.
Third Preferred Embodiment
The third preferred embodiment according to the present invention includes an IGBT device structure identical with the conventional structure of
Specifically, the third preferred embodiment is similar to the first preferred embodiment in the process steps between the formation of the semiconductor body 4 (
The surface protective film 14 on the device top surface is a semi-insulation silicon nitride film formed by the P-CVD process to cover the IGBT surface except the emitter wire bonding region 13, the gate interconnection line, and the gate bonding pad which is a part of the gate interconnection line.
As concluded from the C-V test result that (iii) the introduction of hydrogen atoms is permitted after the radiation for lifetime control and heat treatment for distortion elimination in the IGBT performing lifetime control, the use of the fabrication method of the third preferred embodiment allows defects generated due to the radiation to be reduced by the heat treatment to reduce the number of dangling bonds at the silicon-silicon oxide interface. The Si—H chemical bonds becomes difficult to generate at the silicon-silicon oxide interface.
For this reason, if the P-CVD nitride film containing a large amount of hydrogen atoms is provided in the cell area 31, the number of Si—H chemical bonds is reduced at the silicon-silicon oxide interface in the cell area 31, providing a stable interface state. Thus, there is provided an electrically highly stable IGBT of the conventional construction with a small amount of long-term Vth variations, wherein shorting of the emitter electrode 10 and gate interconnection line 9 is prevented, like the first preferred embodiment.
Referring to
In this manner, the first, second and third preferred embodiments achieve the electrically highly stable semiconductor device with the MOS gate having a satisfactory breakdown voltage characteristic.
The above-mentioned preferred embodiments describe the power semiconductor device having the MOS gate. However, the present invention is also applicable to semiconductor integrated circuit devices, such as memories, having an MOS gate.
While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.
Yano, Mitsuhiro, Mochizuki, Kouichi
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