A single input pin (48) provides multi-functional features for programming a power supply (10). By connecting the appropriate interface circuit (92, 100, or 112) to the single input pin (48), the power supply (10) is programmed for specific behaviors during power up and toggling of an on/off switch (96, 108). In one mode of operation a light emitting diode (106) in the interface circuit (100) is optically coupled to a microprocessor for signaling the closure of the on/off switch (108), allowing the microprocessor to control the power supply (10) through an opto-coupler (102). In another mode of operation, the single on/off switch (96) controls the power supply (10). In yet another mode of operation, Zener diode (118) in the interface circuit (112) controls the power supply (10) during brown-out and black-out conditions.
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0. 50. A method of controlling an operational state of a power conversion control circuit, comprising:
receiving an operating potential to the power conversion control circuit on a first terminal;
regulating the power conversion control circuit in response to a feedback signal;
receiving an external disable control signal on a second terminal for selecting an on-state or an off-state of the power conversion control circuit;
comparing the external disable control signal to first and second reference values; and
setting the power conversion control circuit to a plurality of operational states depending on whether the external disable control signal is greater than the first reference value, or the external disable control signal is between the first and second reference values, or the external disable control signal is less than the second reference value.
0. 28. A power supply regulator circuit, comprising:
a terminal adapted for receiving a mode control signal which controls an on-state and off-state of the power supply regulator circuit;
a first comparator having an input coupled to the terminal for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a first reference value;
a second comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a second reference value different from the first reference value;
a logic circuit having a first input coupled to the output of the first comparator, and a second input coupled to the output of the second comparator; and
a control circuit having a first input coupled for receiving a feedback signal, a second input coupled for receiving an operating potential, an output for providing a switching signal in response to the feedback signal, and a control input coupled to an output of the logic circuit for setting the power supply regulator circuit to an operational state or non-operational state.
0. 26. A power supply regulator circuit, comprising:
a terminal coupled for receiving a mode control signal which controls on-state and off-state of the power supply regulator circuit; and
a regulator circuit having a first input coupled for receiving a feedback signal, and an output for providing a pulse-width modulated switching signal in response to the feedback signal, the regulator circuit including,
(a) a first comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a first reference value,
(b) a second comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a second reference value different from the first reference value, and
(c) a logic circuit having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, the logic circuit decoding the outputs of the first and second comparators and setting the regulator circuit to a non-operational off-state, wherein the regulator circuit is provided in a monolithic integrated circuit package and the terminal is coupled to a pin of the monolithic integrated circuit package.
0. 34. A power supply regulator circuit, comprising:
a multi-function terminal coupled for receiving a mode control signal which controls a plurality of operational modes of the power supply regulator circuit;
a regulator circuit having a first input coupled for receiving a feedback signal, a second input coupled for receiving an operating potential, and an output for providing a switching signal in response to the feedback signal; and
a chip disable circuit having an input coupled for receiving the mode control signal, the chip disable circuit including,
(a) a first comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a first reference value,
(b) a second comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a second reference value different from the first reference value, and
(c) a logic circuit having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output coupled to a control input of the regulator circuit, wherein the logic circuit decodes output states of the first and second comparators to select an operational mode of the regulator circuit.
0. 41. A power supply regulator circuit, comprising:
a terminal adapted for receiving an external disable control signal;
a pulse width modulated (PWM) regulator circuit having a first input coupled for receiving a feedback signal, a second input coupled for receiving an operating potential, and an output for providing a switching signal in response to the feedback signal; and
a chip disable circuit having an input coupled for receiving the external disable control signal for disabling operation of the PWM control circuit in response to the external disable control signal, the chip disable circuit including,
(a) a first comparator having an input coupled for receiving the external disable control signal, and an output having first or second states depending on a comparison between the external disable control signal and a first reference value,
(b) a second comparator having an input coupled for receiving the external disable control signal, and an output having first or second states depending on a comparison between the external disable control signal and a second reference value different from the first reference value, and
(c) a logic circuit having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output coupled to a control input of the PWM regulator circuit;
wherein the chip disable circuit sets the power supply regulator circuit to a non-operational state to conserve energy for an extended period of time as determined by the external disable control signal.
0. 21. A power supply regulator circuit, comprising:
a terminal adapted for receiving a mode control signal having a latchable state, wherein the latchable state of the mode control signal controls an operational on-state or a non-operational off-state of the power supply regulator circuit; and
a pulse width modulated (PWM) regulator circuit having a first input coupled for receiving a feedback signal, and an output for providing a PWM switching signal in response to the feedback signal, the PWM regulator circuit including,
(a) a first comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a first reference value,
(b) a second comparator having an input coupled for receiving the mode control signal, and an output having first or second states depending on a comparison between the mode control signal and a second reference value different from the first reference value, and
(c) a logic circuit having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, the logic circuit decoding the outputs of the first and second comparators and setting the PWM regulator circuit to the non-operational off-state to conserve energy for an extended period of time as determined by the latchable state of the mode control signal, wherein the regulator circuit is provided in a monolithic integrated circuit package and the terminal is coupled to a pin of the monolithic integrated circuit package.
0. 46. A semiconductor die having at least four external connections, comprising:
a first electrical connection terminal coupled for receiving a feedback signal;
a second electrical connection terminal for providing a switching signal;
a third electrical connection terminal coupled to an external ground reference;
a fourth electrical connection terminal coupled for receiving an external disable control signal;
a switching regulator circuit having a first input coupled to the first electrical connection terminal for receiving the feedback signal, a second input coupled for receiving an operating potential, an output coupled to the second electrical connection terminal for providing the switching signal in response to the feedback signal, and an internal ground coupled to the third electrical connection terminal; and
a chip disable circuit having an input coupled for receiving the external disable control signal for disabling operation of the switching regulator circuit in response to the external disable control signal, the chip disable circuit including,
(a) a first comparator having an input coupled for receiving the external disable control signal, and an output having first or second states depending on a comparison between the external disable control signal and a first reference value,
(b) a second comparator having an input coupled for receiving the external disable control signal, and an output having first or second states depending on a comparison between the external disable control signal and a second reference value different from the first reference value, and
(c) a logic circuit having a first input coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output coupled to a control input of the switching regulator circuit to disable operation of the semiconductor chip.
0. 1. A power conversion integrated circuit, comprising:
a state circuit having an output that supplies a mode signal, wherein the state circuit includes
a comparator having a first input coupled for receiving a control signal and a second input coupled for receiving a first reference signal, and
a memory circuit having a first input coupled to an output of the comparator for setting an output state of the memory circuit according to a value of the control signal; and
a control circuit coupled for receiving the mode signal that sets a mode of operation, where the control circuit is responsive to a feedback signal for providing a pulse-width modulated control signal.
0. 2. The power conversion integrated circuit of
a first comparator having a first input coupled for receiving the control signal, a second input coupled for receiving the first reference signal, and an output coupled to the first input of the memory circuit; and
a second comparator having a first input coupled for receiving the control signal, a second input coupled for receiving a second reference signal, and an output coupled to a second input of the memory circuit.
0. 3. The power conversion integrated circuit of
0. 4. The power conversion integrated circuit of
a first resistor having first and second terminals, the first terminal of the first resistor coupled to a first power supply conductor;
a second resistor having first and second terminals, the first terminal of the second resistor coupled to the second terminal of the first resistor and serving as the first output of the resistor divider network; and
a third resistor having first and second terminals, the first terminal of the third resistor coupled to the second terminal of the second resistor and serving as the second output of the resistor divider network, and the second terminal of the third resistor coupled to a second power supply conductor.
0. 5. The power conversion integrated circuit of
0. 6. The power conversion integrated circuit of
0. 7. The power conversion integrated circuit of
0. 8. A semiconductor chip having at least four external electrical connections, comprising:
an internal regulator; a state circuit having an output coupled to a control input of the internal regulator;
a first electrical connection terminal for coupling an external ground reference to an internal ground reference of the internal regulator;
a second electrical connection terminal for providing a pulse-width modulated output signal from an output of the internal regulator;
a third electrical connection terminal coupled for receiving a feedback signal at an input of the internal regulator to control the pulse-width modulated output signal; and
a fourth electrical connection terminal coupled for receiving a control signal which is applied to the state circuit to set a mode of operation of the internal regulator.
0. 9. The semiconductor chip of
0. 10. A programmable power supply, comprising:
a transformer receiving a rectified signal at a primary side of the transformer;
a state circuit having an input and an output for setting a mode of operation of the programmable power supply, wherein the state circuit includes,
a comparator circuit having a first input coupled to the input of the state circuit for receiving a control signal and a second input coupled for receiving a first reference signal, and
a memory circuit having a first input coupled to an output of the comparator for setting an output state of the memory circuit according to a value of the control signal where the output state of the memory circuit controls the mode of operation;
a control circuit coupled for receiving the output state of the memory circuit and wherein the control circuit is responsive to a feedback signal for providing a pulse-width modulated control signal; and
a transistor having a control terminal for receiving the pulse-width modulated control signal, a first conduction terminal coupled to the primary side of the transformer, and a second conduction terminal coupled to ground.
0. 11. The programmable power supply of
a first comparator having a first input coupled for receiving the control signal, a second input coupled for receiving the first reference signal, and an output coupled to the first input of the memory circuit; and
a second comparator having a first input coupled for receiving the control signal, a second input coupled for receiving a second reference signal, and an output coupled to a second input of the memory circuit.
0. 12. The programmable power supply of
0. 13. The programmable power supply of
a first resistor having first and second terminals, the first terminal of the first resistor coupled to a first power supply conductor;
a second resistor having first and second terminals, the first terminal of the second resistor coupled to the second terminal of the first resistor and serving as the first output of the resistor divider network; and
a third resistor having first and second terminals, the first terminal of the third resistor coupled to the second terminal of the second resistor and serving as the second output of the resistor divider network, and the second terminal of the third resistor coupled to a second power supply conductor.
0. 14. A method for controlling a mode of operation of a power converter, comprising the steps of:
controlling a pulse-width modulated output signal of the power converter in response to a feedback signal; and
setting a memory state according to a comparison between a control signal and a first reference signal where the memory state controls the mode of operation of the power converter.
0. 15. The method of
monitoring a signal at an input pin; and
maintaining a same operating state when the input pin receives a voltage about midway between an operating potential and a ground reference.
0. 16. The method of
0. 17. The method of
0. 18. The method of
0. 19. The method of
0. 20. The method of
0. 22. The power supply regulator circuit of
0. 23. The power supply regulator circuit of
0. 24. The power supply regulator circuit of
0. 25. The power supply regulator circuit of
0. 27. The power supply regulator circuit of
0. 29. The power supply regulator circuit of
0. 30. The power supply regulator circuit of
0. 31. The power supply regulator circuit of
0. 32. The power supply regulator circuit of
0. 33. The power supply regulator circuit of
0. 35. The power supply regulator circuit of
0. 36. The power supply regulator circuit of
0. 37. The power supply regulator circuit of
0. 38. The power supply regulator circuit of
0. 39. The power supply regulator circuit of
0. 40. The power supply regulator circuit of
0. 42. The power supply regulator circuit of
0. 43. The power supply regulator circuit of
0. 44. The power supply regulator circuit of
0. 45. The power supply regulator circuit of
0. 47. The semiconductor die of
0. 48. The semiconductor die of
0. 49. The semiconductor die of
0. 51. The method of
0. 52. The method of
0. 53. The method of
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More than one reissue application has been filed for the reissue of U.S. Pat. No. 5,859,768. The reissue applications are application Ser. Nos. 10/946,611 and 09/709,893, now U.S. Pat. No. RE39,933, all of which are divisional reissues of U.S. Pat. No. 5,859,768.
The present invention relates, in general, to integrated circuits and, more particularly, to a power conversion integrated circuit.
A power supply is controlled to be either on or off by a mechanical switch or a relay. Typically, additional discrete components that are external to the integrated circuit adapt the power supply for use in applications such as cable converters for television sets, computer monitors, video cassette recorders (VCRs), battery chargers for portable communications devices, computer printers, and other electronic systems.
Depending on the particular application, the on/off circuitry of a power supply control circuit includes components such as opto-couplers, latches, resistors, and capacitors. Monolithic circuit integration minimizes the number of components external to the integrated circuit and reduces the cost of power supplies. The number and types of external components along with the cost of the integrated circuit package provide functionality that differentiates among different power supplies. Typically, a switching regulator without on/off circuitry is manufactured in a three pin package. A drawback of these three pin package configurations is that they offer limited functionality within the package.
Accordingly, it would be advantageous to have an inexpensive integrated power supply controller that is capable of operating with many different power supplies. It would be of further advantage for the power supply controller to have a minimal number of discrete external components for controlling the power supply on/off switch circuitry.
Generally, the present invention provides a circuit with at least four modes of operation for controlling the on/off features of a power supply. By connecting an appropriate interface circuit to a state input pin, the power supply is programmed for specific behaviors when power is applied or when the interface circuitry is activated. Thus, the multifunctionality provided by a state circuit that is integrated with a control circuit is a cost effective solution for controlling the power supply.
Transformer 16 has a primary side or winding 18 having two terminals, a secondary winding 20 having two terminals, and a secondary winding 30 having two terminals. In particular, one terminal of primary winding 18 is connected to the output of full-wave bridge rectifier 12, and the other terminal of primary winding 18 is connected to a switch output pin 40 of power converter circuit 44.
Secondary winding 20 has a first terminal connected to an anode of a diode 22. A cathode of diode 22 is commonly connected to a first terminal of capacitor 24 and to a terminal 26. The second terminal of capacitor 24 is commonly connected to the second terminal of secondary winding 20 and to a terminal 28. Compensated error amplifier 42 has an input connected to terminal 26, an input connected to terminal 28, and an output connected to feedback pin 46.
Secondary winding 30 has a first terminal connected to an anode of diode 32. A cathode of diode 32 is commonly connected to a first terminal of capacitor 34 and to a bias pin 36 of power converter circuit 44. The second terminal of capacitor 34 is commonly connected to the second terminal of secondary winding 30 and to a potential such as, for example, ground.
Power converter circuit 44 is a switched mode power supply integrated circuit or a power conversion integrated circuit having five electrical connection terminals: (1) a bias pin 36, (2) a ground pin 38, (3) a feedback pin 46, (4) a state pin 48, and (5) a switch output pin 40. Power converter circuit 44 is a semiconductor chip that includes a state circuit 50, a control circuit 52 having an internal regulator, and a transistor 54. State circuit 50 has an input connected to bias pin 36 and another input coupled to state pin 48 of power converter circuit 44. Another input of state circuit 50 is connected to an output of control circuit 52 and receives a logic under-voltage control signal (LOGIC). Another input of state circuit 50 receives an analog under-voltage control signal (ANALOG) and is connected to a second output of control circuit 52. An output of state circuit 50 provides a signal MODE and is connected to a control input of control circuit 52. Control circuit 52 has an input connected to bias pin 36 and another input connected to feedback pin 46 of power converter circuit 44. An output of control circuit 52 is connected to a gate of transistor 54. Both state circuit 50 and control circuit 52 are connected to ground pin 38. A drain of transistor 54 is connected to switch output pin 40 and a source is connected to ground pin 38. As those skilled in the art are aware, a gate of a transistor serves as a control terminal and the drain and source of a transistor serve as current conduction terminals. It should be noted that transistor 54 can be an insulated gate bipolar transistor (IGBT), a bipolar transistor, etc.
In operation, the line voltage, e.g., 110 VAC, is rectified by full-wave bridge rectifier 12 and filtered by capacitor 14. Secondary winding 20 provides a signal that is used to supply the operating power to electronic systems such as cable converters, computer monitors, video cassette recorders (VCRs), battery chargers, computer printers, etc. Compensated error amplifier 42 provides a feedback signal to power converter circuit 44 that is proportional to the DC output signal. The output of compensated error amplifier 42 may be optically, electrically, magnetically, mechanically, or other means coupled to feedback pin 46 of power converter circuit 44.
The feedback signal is used by control circuit 52 for altering the pulse width of the signal that is supplied to the control terminal of transistor 54. Thus, compensated error amplifier 42 alters the pulse width of the output signal at switch output pin 40 in accordance with the voltage developed across terminals 26 and 28. The variable pulse width modifies the current in transformer 16, thereby regulating the voltage of the DC output signal. In addition, the bias voltage developed at bias pin 36 from secondary winding 30 can used as the operating supply voltage of state circuit 50 and control circuit 52. The bias voltage developed at bias pin 36 can alternately be derived from secondary winding 20. It should be noted that compensated error amplifier 42 can be replaced with a high gain comparator, or the like.
The resistors 62, 64, 66, 68, 70, and 72 of reference generator 60 (
Positive detector circuit 76 includes a comparator 77 having a non-inverting input connected to an input of positive detector circuit 76, and thus to node 67 of reference generator 60. An inverting input of comparator 77 is connected to an input of positive detector circuit 76 and thus to state pin 48 of reference generator 60. An output of comparator 77 is connected to an output of positive detector circuit 76. Negative detector circuit 78 includes a comparator 80 connected to a pulse filter 82. Comparator 80 has a non-inverting input connected to an input of negative detector circuit 78 and thus to node 71 of reference generator 60. An inverting input of comparator 80 is connected to an input of negative detector circuit 78 and thus to state pin 48 of reference generator 60. An output of comparator 80 is coupled to an output of negative detector circuit 78 through pulse filter 82.
Reset circuit 65 receives an input signal LOGIC UNDER-VOLTAGE and has an output connected to state pin 48.
Mode memory circuit 90 includes a two-input NAND gate 84, a logic circuit 86, and a positive edge triggered toggle flip-flop 88. In particular, two-input NAND gate 84 has an input connected to the output of positive detector circuit 76, the other input is coupled for receiving the signal LOGIC UNDER-VOLTAGE. When the voltage Vcc begins to ramp from a starting voltage of zero volts, the signal LOGIC UNDER-VOLTAGE has an initial logic zero value that is switched to a logic one value at a predetermined voltage. By way of example, the predetermined voltage is a voltage potential that is sufficiently high to allow logic circuitry to properly operate. In other words, the signal LOGIC UNDER-VOLTAGE has a logic one value when the voltage Vcc is sufficiently above the predetermined voltage and a logic zero value when below the predetermined voltage.
Logic circuit 86 has an input
It should be noted that when a signal having a logic zero value is received at the input
Toggle flip-flop 88 has an input S connected to the output of NAND gate 84, an input CLK connected to the output of logic circuit 86, and an output that also serves as the output of state circuit 50. It should be noted that the output signal of toggle flip-flop 88 can be set to a logic one value when the input S receives a logic one signal. Otherwise, the stored value of the output signal changes output state in response to logic transitions at input CLK, i.e., the stored value is toggled when the input CLK transitions from a logic zero value to a logic one value. It should be noted that if the signal at the input CLK transitions while the signal at input S is a logic one, then flip-flop 88 responds to a logic one signal at input S and ignores the signal at the input CLK.
In operation, the power supply conductor Vcc initially starts at a voltage of about zero volts and ramps to a higher voltage value, increasing in voltage to a voltage greater than 5.8 volts. As the voltage Vcc begins to ramp from zero volts, the signals LOGIC UNDER-VOLTAGE and ANALOG UNDER-VOLTAGE initially have logic zero values. The signal LOGIC UNDER-VOLTAGE is set to a logic one when the voltage Vcc exceeds about 3.5 volts. The signal ANALOG UNDER-VOLTAGE is set to a logic one value when the voltage Vcc exceeds about 4.8 volts.
In a first operating mode, no external components are connected to state pin 48. With the application of the line voltage, the voltage for Vcc increases from zero volts. The signal LOGIC UNDER-VOLTAGE has a logic zero value when the voltage Vcc is in the range of about 0 volts to about 3.5 volts. The logic zero value for the signal LOGIC UNDER-VOLTAGE causes both the output of logic circuit 86 to have a logic zero value and the output of toggle flip-flop 88 to have a logic one value. When the signal LOGIC UNDER-VOLTAGE is at a logic zero value, input state pin 48 is pulled to ground through reset circuit 65. When the voltage Vcc increases above a voltage of about 3.5 volts the output of reset circuit 65 becomes a high impedance output. With no external components, the voltage at state pin 48 is determined by the values of resistors 62 and 64. In this first mode of operation the voltage on state pin 48 is between the reference voltages at nodes 67 and 71, the signal at the output of comparator 77 has a logic one value, and the output of comparator 80 has a logic zero value. Thus, the signal MODE is a logic one and power supply 10 (
The reference voltage or reference signal at node 67 is transmitted to the non-inverting input of comparator 77 and the voltage at state pin 48 is transmitted to the inverting input of comparator 77. If the voltage at state pin 48 is less than the reference voltage at node 67, the output of comparator 77 is a logic one value. On the other hand, if the voltage at state pin 48 is greater than the reference voltage at node 67, the output of comparator 77 is a logic zero value. The reference voltage or reference signal at node 71 is transmitted to the non-inverting input of comparator 80 and the voltage at state pin 48 is transmitted to the inverting input of comparator 80. If the voltage at state pin 48 is greater than the reference voltage at node 71, the output of comparator 80 is a logic zero value. On the other hand, if the voltage at state pin 48 is less than the reference voltage at node 71, the output of comparator 80 is a logic one value. Together, comparators 77 and 80 determine whether the voltage at state pin 48 is between the reference voltages at nodes 67 and 71.
In the second mode of operation, switch 96 allows for manually controlling whether power supply 10 (
With the application of the line voltage to full-wave bridge rectifier 12, the voltage Vcc (see
When switch 96 is closed, capacitor 98 is discharged through switch 96 and resistor 94. The voltage at state pin 48 drops below the reference voltage at node 71 causing comparator 80 to provide a logic one to input S of logic circuit 86. The output of logic circuit 86 transitions to a logic one value causing toggle flip-flop 88 to change states such that the signal MODE is a logic one value and power supply 10 is in an on state. With each closure of switch 96 the output of logic circuit 86 transitions from a logic zero to a logic one causing the stored data in toggle flip-flop 88 to change state, provided that capacitor 98 was charged above the reference voltage at node 71.
In the third mode of operation, state circuit 50 is powered on such that the signal MODE has a logic zero value. Capacitor 110 delays the charging of state pin 48 so that the output of comparator 80 has a logic one value, which turns off power supply 10. The momentary closure of switch 108 causes LED 106 to emit light and transmit a signal to, for example, a microprocessor (not shown). When switch 108 is closed, state pin 48 is pulled high through switch 108, LED 106, and resistor 104. The voltage at state pin 48 is clamped by voltage clamp circuit 74 such that LED 106 is always forward biased and emitting light when switch 108 is closed. When switch 108 is closed the output of comparator 77 becomes a logic zero value signifying that the voltage on state pin 48 is above the reference voltage established at node 67 by the resistor divider network. The logic zero value sets the signal MODE to a logic one value for turning on power supply 10 (FIG. 1).
When the signal MODE is a logic one and power supply 10 is on, another momentary closure of switch 108 signals the microprocessor through light emitted by LED 106 of a request to shut down power supply 10. The microprocessor can signal through opto-coupler 102 a confirmation to shut down power supply 10. If signaled by the microprocessor, opto-coupler 102 pulls state pin 48 to ground and the output of comparator 80 becomes a logic one signifying that the voltage on state pin 48 is below the reference voltage at node 71 of reference generator 60. The output of logic circuit 86 transitions to a logic one value causing toggle flip-flop 88 to change states such that the signal MODE is a logic zero value and power supply 10 is off. The microprocessor “reads” each momentary closure of switch 108 by the light emitted from LED 106. The state of toggle flip-flop 88 is changed in accordance with the signal received by opto-coupler 102. Thus, the momentary closure of switch 108 allows the microprocessor to control when power supply 10 is turned on or turned off.
In the fourth mode of operation, state circuit 50 is powered on and the signal MODE is at a logic one value. The output of comparator 77 has a logic zero value indicating that the voltage on state pin 48 has a value above the reference voltage at node 67. The logic zero value at the input of NAND gate 84 causes the signal MODE to have a logic one value and power supply 10 (
State circuit 50, interface circuits 92 and 100 have been described with references with respect to ground. It should be noted that logic in state circuit 50 and interface circuits 92 and 100 can be reconfigured to function with respect to the reference voltage Vcc. It should be further noted that state circuit 50 can also be reconfigured to function with opposite polarity logic at state pin 48.
It should be noted that capacitors 98, 110, and 120 as described in
By now it should be appreciated that a structure and method have been provided for controlling the on/off status of a programmable power supply. The integrated power supply controller is inexpensive and provides a cost effective system solution for switching power supplies by reducing the number of external components. It has further been shown that additional functionality has been provided through a multi-functional input for controlling the on/off switching function of a power supply.
Hall, Jefferson W., Alberkrack, Jade H.
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May 30 1997 | HALL, JEFFERSON W | Motorola, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032483 | /0109 | |
May 30 1997 | ALBERKRACK, JADE H | Motorola, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032483 | /0109 | |
Apr 14 2000 | Motorola, Inc | Semiconductor Components Industries, LLC | CORRECTIVE ASSIGNMENT TO CORRECT THE INCLUDE SCHEDULE A PREVIOUSLY RECORDED AT REEL: 015826 FRAME: 0538 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT | 039363 | /0821 | |
Dec 14 2001 | Motorola, Inc | Semiconductor Components Industries, LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 015826 | /0538 | |
Sep 20 2004 | Semiconductor Components Industries, LLC | (assignment on the face of the patent) | / | |||
Jan 18 2005 | Semiconductor Components Industries, LLC | JPMORGAN CHASE BANK, N A | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 016183 | /0001 | |
Dec 14 2009 | Semiconductor Components Industries, LLC | JPMORGAN CHASE BANK, N A , AS COLLATERAL AGENT | SECURITY AGREEMENT | 023826 | /0725 | |
May 11 2010 | JPMORGAN CHASE BANK, N A | Semiconductor Components Industries, LLC | RELEASE OF SECURITY INTEREST | 033379 | /0623 |
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