Methods for built-in self-test (bist) testing and circuitry for testing a content addressable memory (cam) core are provided. In one example, the bist circuit includes a search port for enabling searches of the cam core and a maintenance port for enabling addressing of locations of the cam core. The maintenance port includes writing logic for writing to locations of the cam core. The bist circuit also includes a bist controller for coordinating bist testing of the cam core. The bist controller is capable of performing a bist search on the cam core on every cycle through the search port and performing a bist write at selected times to the cam core. Thus, the bist write is capable of being performed in a same cycle as the bist search permitting at-speed bist. The bist controller, performs bist testing in a manner that limits the number of rows in the cam that match at any given cycle, thus allowing a low-power bist operation. The bist controller can also be configured to coordinate simultaneous bist testing of two or more cam cores.
|
0. 61. An apparatus, comprising:
one or more cam cores;
means for performing a built-in self test bist coupled to one or more of the cam cores and capable of testing each of the one or more cam cores; and
means for controlling said means for performing the bist.
0. 67. An apparatus for performing built-in self-test (bist) testing on a content addressable memory (cam) core, comprising:
means for enabling searches of the cam core;
means for enabling addressing of locations of the cam core, said addressing enabling means further including means for writing to locations of the cam core; and
means for coordinating bist testing of the cam core, said bist testing coordinating means being capable of performing a bist search and a bist write on the cam core at the same time.
0. 64. An apparatus for performing built-in self-test (bist) testing on a content addressable memory (cam) core, comprising:
means for writing test data to memory addresses in the cam core;
means for searching for test data in the cam core, the searching being capable of being continuously performed one cycle after another, or the writing of the test data capable of being performed in a same cycle as one or more search performed during the searching, or combinations thereof, wherein the cam core is a ternary cam core.
0. 43. An apparatus for testing a content addressable memory (cam) core, comprising:
means for enabling searches of the cam core;
means for enabling addressing of locations of the cam core, said addressing enabling means further including means for writing to locations of the cam core; and
means for coordinating bist testing of the cam core, said bist testing coordinating means being capable of performing a bist search on the cam core on every cycle through said search enabling means and performing a bist write at selected times to the cam core, wherein the bist write is capable of being performed in a same cycle as the bist search.
0. 55. An apparatus for testing a content addressable memory (cam) core, comprising:
means for enabling searches of the cam core;
means for enabling addressing of locations of the cam core, said addressing enabling means further including means for writing to locations of the cam core;
means for coordinating bist testing of the cam core, said bist testing coordinating means being capable of performing a bist search and a bist write on the cam core at the same time, wherein the bist search is capable of being performed on every cycle and the bist write can be performed at any cycle including a cycle in which the bist search is performed.
0. 53. An apparatus for testing a content addressable memory (cam) core, comprising:
means for enabling searches of the cam core;
means for enabling addressing of locations of the cam core, said addressing enabling means further including means for writing to locations of the cam core; and
means for coordinating bist testing of the cam core, said bist testing coordinating means being capable of performing a bist search on the cam core on every cycle through said search enabling means and performing a bist write at selected times to the cam core, wherein the bist write is capable of being performed in a same cycle as the bist search wherein the cam core is a ternary cam core that is capable of storing three states.
0. 52. An apparatus for testing a content addressable memory (cam) core, comprising:
means for enabling searches of the cam core;
means for enabling addressing of locations of the cam core, said addressing enabling means further including means for writing to locations of the cam core; and
means for coordinating bist testing of the cam core, said bist testing coordinating means being capable of performing a bist search on the cam core on every cycle through said search enabling means and performing a bist write at selected times to the cam core, the bist write is capable of being performed in a same cycle as the bist search, wherein bist testing of the bist circuit does not generate matches on one or more rows in the cam core so as to enable lower-power bist operation.
30. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core, comprising:
a maintenance port for enabling addressing of locations of the cam core, the maintenance port further including writing logic for writing to locations of the cam core;
a bist controller for coordinating bist testing of the cam core, the bist controller being capable of performing a bist write at selected times to the cam core, wherein the bist controller is capable of performing a bist search on the bist write on the cam core at the same time; and
a maintenance port comparator being coupled between the bist controller and a data output of the maintenance port, the maintenance port comparator being configured to compare an expected data generated by the bist controller with actual data provided from the data output of the maintanance port.
35. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core, comprising:
a maintenance port for enabling addressing of locations of the cam core, the maintenance port further including writing logic for writing to locations of the cam core;
a bist controller for coordinating bist testing of the cam core, the bist controller being capable of performing a bist write at selected times to the cam core and performing another operation on the cam core, the bist write is capable of being performed in a same cycle as the another operation; and
a maintenance port comparator being coupled between the bist controller and a data output of the maintanance port, the maintenance port comparator being configured to compare an expected data generated by the bist controller with actual data provided from the data output of the maintenance port.
32. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core, comprising:
a maintenance port for enabling addressing of locations of the cam core, the maintanance port further including writing logic for writing to locations of the cam core;
a bist controller for coordinating bist testing of the cam core, the bist controller being capable of performing a bist write at selected times to the cam core and performing a bist search on the cam core, and wherein the bist controller is capable of performing the bist search and the bist write in a same cycle; and
a maintanance port comparator being coupled between the bist controller and a data outpupt of the maintanance port, the maintanance port comparator being configured to compare an expected data generated by the bist controller with actual data provided from the data output of the maintenance port.
0. 51. An apparatus for testing a content addressable memory (cam) core, comprising:
means for enabling searches of the cam core;
means for enabling addressing of locations of the cam core, said addressing enabling means further including means for writing to locations of the cam core;
means for coordinating bist testing of the cam core, said bist testing coordinating means being capable of performing a bist search on the cam core on every cycle through said search enabling means and performing a bist write at selected times to the cam core, the bist write is capable of being performed in a same cycle as the bist search; and
means for communicating test data to the cam core, said test data communicating means having a capability to expand two bits of data from said bist testing coordinating means to a required width, the capability to expand being capable of limiting a number of needed global wires.
0. 50. An apparatus for testing a content addressable memory (cam) core, comprising:
means for enabling searches of the cam core;
means for enabling addressing of locations of the cam core, said addressing enabling means further including means for writing to locations of the cam core;
means for coordinating bist testing of the cam core, said bist testing coordinating means being capable of performing a bist search on the cam core on every cycle through said search enabling means and performing a bist write at selected times to the cam core, wherein the bist write is capable of being performed in a same cycle as the bist search; and
means for receiving test data, tag data, or control signals, or combinations thereof capable of receiving one bit of test data from said bist testing coordinating means, other bits being generated internally to said receiving means, and capable of limiting a number of required global wires.
0. 39. An apparatus for testing a content addressable memory (cam) core, comprising:
means for enabling searches of the cam core;
means for enabling addressing of locations of the cam core, said addressing enabling means further comprising means for writing to locations of the cam core;
means for coordinating bist testing of the cam core, said bist testing coordinating means being capable of performing a bist search on the cam core on every cycle through said search enabling means and performing a bist write at selected times to the cam core, wherein the bist write is capable of being performed in a same cycle as the bist search; and
maintenance port comparing means for comparing an expected data generated by said bist testing coordinating means with actual data provided from a data output of said addressing enabling means, said maintenance port comparing means being coupled between said bist testing coordinating means and the data output of said addressing enabling means.
0. 1. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core, comprising:
a search port for enabling searches of the cam core;
a maintenance port for enabling addressing of locations of the cam core, the maintenance port further including writing logic for writing to locations of the cam core;
a bist controller for coordinating bist testing of the cam core, the bist controller being capable of performing a bist search on the cam core on every cycle through the search port and performing a bist write at selected times to the cam core, the bist write is capable of being performed in a same cycle as the bist search; and
a maintenance port comparator being coupled between the bist controller and a data output of the maintenance port, the maintenance port being configured to compare an expected data generated by the bist controller with actual data provided from the data output of the maintenance port.
0. 2. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
a search port interface for receiving test data, tag data and control signals from the bist controller during bist testing, the search port interface being coupled to the search port.
0. 3. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
a search port comparator being coupled to the search port and the bist controller, the search port comparator being configured to,
compare search addresses generated from the search port in response to bist search and expected addresses generated by the bist controller and communicated to the maintenance port, and
compare expected hit and multiple hit data generated by the bist controller with generated hit and multiple hit data output through the search port.
0. 4. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
a bist maintenance interface for communicating test data to the cam core.
0. 5. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core, comprising:
a search port for enabling searches of the cam core;
a maintenance port for enabling addressing of locations of the cam core, the maintenance port further including writing logic for writing to locations of the cam core; and
a bist controller for coordinating bist testing of the cam core, the bist controller being capable of performing a bist search on the cam core on every cycle through the search port and performing a bist write at selected times to the cam core, the bist write is capable of being performed in a same cycle as the bist search.
0. 6. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
0. 7. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
0. 8. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
0. 9. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
0. 10. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
a search port comparator;
a search port interface;
a maintenance port comparator; and
a maintenance port interface;
wherein the search port interface, the maintenance port interface, the search port comparator, and the maintenance port comparator are each distributed and have expansion capabilities, which limits a number of global wires required to communicate read/write and search data and results.
0. 11. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
0. 12. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core, comprising:
a search port for enabling searches of the cam core;
a maintenance port for enabling addressing of locations of the cam core, the maintenance port further including writing logic for writing to locations of the cam core;
a bist controller for coordinating bist testing of the cam core, the bist controller being capable of performing a bist search on the cam core on every cycle through the search port and performing a bist write at selected times to the cam core, the bist write is capable of being performed in a same cycle as the bist search; and
a search port interface that receives only 1 bit of test data from the bist controller, other bits being generated internally to the search port interface, so as to limit a number of required global wires.
0. 13. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core, comprising:
a search port for enabling searches of the cam core;
a maintenance port for enabling addressing of locations of the cam core, the maintenance port further including writing logic for writing to locations of the cam core;
a bist controller for coordinating bist testing of the cam core, the bist controller being capable of performing a bist search on the cam core on every cycle through the search port and performing a bist write at selected times to the cam core, the bist write is capable of being performed in a same cycle as the bist search; and
a bist maintenance interface for communicating test data to the cam core, the bist maintenance interface having a capability to expand 2 bits of data from the bist controller to a required width, the capability to expand being configured to limit a number of needed global wires.
0. 14. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core, comprising:
a search port for enabling searches of the cam core;
a maintenance port for enabling addressing of locations of the cam core, the maintenance port further including writing logic for writing to locations of the cam core; and
a bist controller for coordinating bist testing of the cam core, the bist controller being capable of performing a bist search on the cam core on every cycle through the search port and performing a bist write at selected times to the cam core, the bist write is capable of being performed in a same cycle as the bist search, wherein bist testing of the bist circuit does not generate matches on all rows in the cam core so as to enable low-power bist operation.
0. 15. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core, comprising:
a search port for enabling searches of the cam core;
a maintenance port for enabling addressing of locations of the cam core, the maintenance port further including writing logic for writing to locations of the cam core; and
a bist controller for coordinating bist testing of the cam core, the bist controller being capable of performing a bist search on the cam core on every cycle through the search port and performing a bist write at selected times to the cam core, the bist write is capable of being performed in a same cycle as the bist search, wherein the cam core is a ternary cam core that is capable of storing three states.
0. 16. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
0. 17. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core, comprising:
a search port for enabling searches of the cam core;
a maintenance port for enabling addressing of locations of the cam core, the maintenance port further including writing logic for writing to locations of the cam core;
a bist controller for coordinating bist testing of the cam core, the bist controller being capable of performing a bist search and a bist write on the cam core at the same time, wherein the bist search can be performed on every cycle and the bist write can be performed at any cycle including a cycle in which the bist search is performed.
0. 18. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
0. 19. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
0. 20. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
a search port interface for receiving test data, tag data and control signals from the bist controller during bist testing, the search port interface being coupled to the search port; and
a search port comparator being coupled to the search port and the bist controller, the search port comparator being configured to,
compare search addresses generated from the search port in response to bist search and expected addresses generated by the bist controller and communicated to the maintenance port, and
compare expected hit and multiple hit data generated by the bist controller with generated hit and multiple hit data output through the search port.
0. 21. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
a bist maintenance interface for communicating test data to the cam core, the bist maintenance interface having an expansion capability; and
a maintenance port comparator being coupled between the bist controller and a data output of the maintenance port, the maintenance port being configured to compare an expected data generated by the bist controller with actual data provided from the data output of the maintenance port.
0. 22. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
0. 23. content addressable memory (cam) circuitry with bist testing capabilities, comprising:
a plurality of cam cores;
a plurality of bist circuits coupled to each of the cam cores; and
a single bist controller being capable of controlling bist testing of each of the plurality of cam cores.
0. 24. content addressable memory (cam) circuitry with bist testing capabilities as recited in
0. 25. content addressable memory (cam) circuitry with bist testing capabilities as recited in
(a) a bist search interface;
(b) a search port comparator;
(c) a maintenance port comparator; and
(d) a bist maintenance interface.
0. 26. A method for performing built-in self-test (bist) testing on a content addressable memory (cam) core, comprising:
writing test data to memory addresses in the cam core;
searching for test data in the cam core, the searching being continuously performed one cycle after another and the writing of the test data capable of being performed in a same cycle as one or more search performed during the searching, wherein the cam core is a ternary cam core.
0. 27. A method for performing built-in self-test (bist) testing on a content addressable memory (cam) core as recited in
selecting one row of the cam core to be valid during the searching, such that matches only occur in the one row in one of the cycles.
0. 28. A method for performing built-in self-test (bist) testing on a content addressable memory (cam) core as recited in
0. 29. A method for performing built-in self-test (bist) testing on a content addressable memory (cam) core, comprising:
a search port for enabling searches of the cam core;
a maintenance port for enabling addressing of locations of the cam core, the maintenance port further including writing logic for writing to locations of the cam core; and
a bist controller for coordinating bist testing of the cam core, the bist controller being capable of performing a bist search and a bist write on the cam core at the same time.
31. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
a bist maintanance interface for communicating test data to the cam core.
33. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
34. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
a search port for enabling searches the cam core.
36. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
37. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
38. A built-in self-test (bist) circuit for testing a content addressable memory (cam) core as recited in
(a) between bist row and block addresses and functional mode row and block addresses; and
(b) between bist write data and functional mode write data.
0. 40. The apparatus as claimed in
means for receiving test data, tag data, or control signals, or combinations thereof, from said bist testing coordinating means during bist testing, said receiving means being coupled to said search enabling means.
0. 41. The apparatus as claimed in
search port comparing means for comparing search data being coupled to said search enabling means and said bist testing coordinating means, said search port comparing means being capable of:
comparing search addresses generated from said search enabling means in response to bist search and expected addresses generated by said bist testing coordinating means and communicated to said addressing enabling means; and
comparing expected hit and multiple hit data generated by said bist testing coordinating means with generated hit and multiple hit data output through said search enabling means.
0. 42. The apparatus as claimed in
means for communicating test data to the cam core.
0. 44. The apparatus as claimed in
0. 45. The apparatus as claimed in
0. 46. The apparatus as claimed in
0. 47. The apparatus as claimed in
0. 48. The apparatus as claimed in
search port comparing means for comparing search data;
means for receiving test data, tag data, or control signals, or combinations thereof;
maintenance port comparing means for comparing maintenance data; and
means for interfacing a means for enabling addressing of locations of the cam core;
wherein said receiving means, said means for interfacing an addressing enabling means, said search port comparing means, or said maintenance port comparing means, or combinations thereof, are distributed and have expansion capabilities, and being capable of limiting a number of global wires required to communicate read/write or search data or results, or combinations thereof.
0. 49. The apparatus as claimed in
0. 54. The apparatus as claimed in
0. 56. The apparatus as claimed in
0. 57. The apparatus as claimed in
0. 58. The apparatus as claimed in
means for receiving test data, tag data, or control signals, or combinations thereof, from said bist testing coordinating means during bist testing, said receiving means being coupled to said search enabling means; and
search port comparing means for comparing search data being coupled to said search enabling means and said bist testing coordinating means, said search port comparing means being capable of:
comparing search addresses generated from said search enabling means in response to bist search and expected addresses generated by said bist testing coordinating means and communicated to said addressing enabling means; and
comparing expected hit or multiple hit data, or combinations thereof, generated by said bist testing coordinating means with generated hit or multiple hit data or combinations thereof, output through said search enabling means.
0. 59. The apparatus as claimed in
means for communicating test data to the cam core, said test data communicating means having an expansion capability; and
maintenance port comparing means for comparing maintenance data being coupled between said bist testing coordinating means and a data output of said addressing enabling means, said maintenance port comparing means being configured to compare an expected data generated by said bist testing coordinating means with actual data provided from the data output of said addressing enabling means.
0. 60. The apparatus as claimed in
0. 62. The apparatus as claimed in
0. 63. The apparatus as claimed in
means for interfacing said controlling means;
search port comparing means for comparing search data;
maintenance port comparing means for comparing maintenance data; and
means for communicating test data to one or more cam cores.
0. 65. The apparatus as claimed in
means for selecting one row of the cam core to be valid during the searching, such that matches occur in the one row in one of the cycles.
0. 66. The apparatus as claimed in
|
This application More than one reissue application has been filed for the reissue of U.S. Pat. No. 6,609,222. The present application is a continuation reissue application of U.S. patent application Ser. No. 11/208,134 filed Aug. 19, 2005, which is a reissue application of U.S. Pat. No. 6,609,222, which claims priority from to U.S. Provisional Patent Application No. 60/153,388 filed Sep. 10, 1999, and entitled “Content Addressable Memory Circuitry.” This provisional application is incorporated herein by reference.
1. Field of the Invention
The present invention relates generally to memory circuits, and more particularly to built-in self test (BIST) circuitry for content addressable memory (CAM) circuits.
2. Description of the Related Art
Modern computer systems and computer networks utilize memory devices for storing data and providing fast access to the data stored therein. A content addressable memory (CAM) is a special type of memory device often used for performing fast destination searches for data stored in the CAM. For example, Internet routers often include a CAM for searching the address of specified data. Thus, the use of CAMs allows routers to perform address searches to facilitate more efficient communication between computer systems over computer networks. Besides routers, CAMs are also utilized in other areas where fast-searches are required such as databases, network adapters, image processing, voice recognition applications, etc.
Conventional CAMs typically include a two-dimensional row and column content addressable memory core array of cells. In such an array, each row typically stores an address, pointer, or bit pattern entry. In a read/write configuration, a CAM may perform “read” and “write” operations at specific addresses as is done in conventional random access memories (RAMs). In another configuration, CAMs unlike RAMs, can perform data “search” operations that simultaneously compare a bit pattern of data against an entire list (i.e., column) of prestored entries (i.e., rows).
As with most memory devices, the conventional CAMs may fail to operate properly due to any number of faults. For example, bit cells of the CAM array may become stuck at some value. Another type of fault occurs when bit cells become electrically coupled during write operations. In such cases, when a specific value is written to one bit cell, the other bit cell in the same row or a different row acquires the same value. Another type of fault is a transition fault, which prevents a bit cell from transitioning from one state into another state. Yet another example is when an address decoding fault occurs, thus causing a wrong cell or cells to be addressed, thereby resulting in the access of data in the wrong location.
Still another type of fault occurs when electrical shorts or other defects cause circuit or memory elements to be stuck-at some value, thereby preventing proper operation of the CAM. Such faults may occur in a CAM itself or its peripheral circuitry. Another fault occurs when CAM circuits operate at a slower speed than expected due to variations in such factors as IC fabrication process, temperature, or voltage. As can be appreciated, such dynamic faults cause undesired delays that can degrade performance of CAM circuits.
To guard against such faults, one approach is to implement a built-in self-test (BIST) technique for detecting some of these types of faults. For example, U.S. Pat. No. 5,107,501 by Yervant Zorian, which is incorporated herein by reference, discloses a BIST technique for testing the data bits in a conventional binary CAM using write and read-match operations. While such method detects faults such as electrical short and open faults and stuck-at faults, it is not well suited for detecting faults in ternary CAMs. Specifically, the bit cells in ternary CAMs are characterized not only by binary states of “0” and “1,” but also by a “don't care” state, which denotes that the state of the associated bit cell is not relevant to a particular CAM search. Consequently, not all functional aspects of a ternary CAM can be tested using the teachings of Zorian.
Also, Zorian can only perform writes to set up searches when search operations are not being performed. Consequently, there will be cases in which BIST searching cannot be performed for several cycles until write operations are complete. This, of course, slows down BIST testing and does not allow the BIST testing to be at the functional speed. Furthermore, the BIST technique described by Zorian tests the CAM rows simultaneously. This technique triggers matches in all rows of the CAM and results in very high power consumption. In essence, the Zorian design is impractical for today's larger CAM implementations. Practical CAM devices with large storage capacities are designed to be used only in a manner that does not cause matches in more than some limited number of rows simultaneously.
In view of the foregoing, what is needed is a method for BIST testing of CAM circuitry and associated BIST testing circuitry.
The present invention fills this need by providing an architecture for performing built-in self-test (BIST) for CAMS. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several embodiments of the present invention are described below.
In one embodiment, a built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core is disclosed. The BIST circuit includes a search port for enabling searches of the CAM core and a maintenance port for enabling addressing of locations of the CAM core. The maintenance port includes writing logic for writing to addresses of the CAM core. The BIST circuit also includes a BIST controller for coordinating BIST testing of the CAM core. The BIST controller is capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core. Thus, the BIST write is capable of being performed in a same cycle as the BIST search.
In another embodiment, a built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core is disclosed. The BIST circuit includes a search port for enabling searches of the CAM core and a maintenance port for enabling addressing of addresses of the CAM core. The maintenance port further includes writing logic for writing to addresses of the CAM core. A BIST controller for coordinating BIST testing of the CAM core is also provided. The BIST controller is capable of performing a BIST search and a BIST write on the CAM core at the same time.
In another embodiment, the search port and maintenance port are distributed and are not part of the BIST controller, so as to reduce the number of global wires required to communicate read/write/search data and results to the CAM core.
In yet another embodiment, content addressable memory (CAM) circuitry with BIST testing capabilities is disclosed. The circuitry includes a plurality of CAM cores and a plurality of BIST circuits that are coupled to each of the CAM cores. A single BIST controller is also included and is capable of controlling BIST testing of each of the plurality of CAM cores. Preferably, the single BIST controller is configured to perform BIST searches on each of the plurality of CAM cores during each cycle and is further configured to perform BIST writing during any cycle including a cycle in which the BIST search occurs.
In still a further embodiment, a method for performing built-in self-test (BIST) testing on a content addressable memory (CAM) core is disclosed. The method includes: (a) writing test data to memory addresses in the CAM core; and (b) searching for test data in the CAM core, the searching being continuously performed one cycle after another and the writing of the test data capable of being performed in a same cycle as one or more search performed during the searching. In one aspect of this embodiment, the method can further include an operation of selecting one row of the CAM core to be valid during the searching, such that matches only occur in the one row in one of the cycles. This aspect enables low power BIST testing.
The advantages of the present invention are numerous. Most notably, the BIST testing architecture enables testing of a CAM core separate from the testing of priority encoders (PEs). In one embodiment, separately testing the CAM core is configured to further enable the testing of one row of the CAM core at a time. This capability will reduce the power consumption during BIST testing. A further advantage of the present invention is the ability of the BIST testing architecture (e.g., by way of the BIST controller) to execute uninterrupted searches at each cycle while simultaneously performing writes that set up subsequent searches. For example, the BIST controller is capable simultaneously accessing the search port and the maintenance port of a CAM core. This functionality enables BIST testing of a CAM core at more realistic speeds which resemble realistic CAM operation.
Other advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements.
An invention for the built-in self-test (BIST) of a content addressable memory (CAM) core with ternary storage (including a don't care state) is disclosed. In one embodiment, the ternary CAM also contains binary valid and tag bits. The testing of CAM cores in accordance with the present invention is configured to test the CAM cores separate from priority encoders (PE). Separating the testing of the CAM core from the testing of PE enables BIST testing of one row of the CAM core at a time. By doing this, lower power operation can be achieved during BIST testing. A further feature of the present invention is the ability of the BIST testing architecture to execute uninterrupted searches at each cycle while simultaneously performing writes that set up subsequent searches. This functionality enables BIST testing of a CAM core at more realistic speeds which resemble the functional CAM speed. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be understood, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
During a search, whether it be during BIST operation or functional operation, search data is provided by way of the search port 114 and the matches are communicated from the CAM core 112 to the priority encoder 116. In this example, the CAM core 112 has 4096 rows, and each row is coupled by way of a bus to the priority encoder 116. Thus, the priority encoder 116 will have 4096 entries with entry 0 having the highest priority and entry 4095 having the lowest priority for a search result. Consequently, the priority encoder 116 is charged with outputting a search result, which represents the match having the highest priority.
For illustration purposes,
In this example, the CAM core consists of 4096 rows of 32 ternary data bits 202, 4 binary tag bits 208, and 2 binary valid bits 206 each. Since the CAM is ternary, each row of 32 ternary data bits is implemented as 2 sub-rows of 32 binary bits each.
For read/write operations, the row decoder is designed to address each sub-row individually. Thus, the read/write ports on the CAM have 32 data bits, 2 tag bits, and 1 valid bit. For search operations however, both sub-rows are compared simultaneously against the search port data. Since the search port data is also ternary, it is encoded similarly as above, and thus consists of 64 bits of search data and 4 bits of tag data. Valid bits are not provided since the search is restricted over valid rows only, in this example.
The BIST circuitry further includes the BIST search interface (SIF) 312, a BIST controller 314, a BIST maintenance interface 316, the search port comparator 340, and a maintenance port comparator 318. The BIST controller 314, in one embodiment, is a state machine that executes the CAM BIST algorithm of the present invention, and will be described in greater detail with reference to FIGS. 5. The CAM BIST algorithm processed by the BIST controller 314 can be defined by Verilog® code (i.e., register transfer level description), which can then be synthesized into gates. Also provided is an IEEE 1149.1 controller, which is commercially available in Verilog® form. When operating in BIST mode, the BIST search interface (SIF) 312 will provide 64 bits of search data, to the search port 304 by way of a bus 313. The 64 bits of search data are generated by a shift register in the SIF 312, which receives a 1 bit data input from the BIST controller 314. The bus 313 will also be used to communicate 4 tag bits provided by the BIST SIF 312 to the search port. The BIST SIF 312 will also receive control signals controlling the shift register, including a set and a reset signal from the BIST controller 314. As mentioned earlier, the multiplexer 320 will therefore communicate the 64 bits of search data and 4 bits of tag to the CAM core 302 when the multiplexer 320 operates in BIST mode. The BIST controller 314 is configured to write in different sequences of bits to different locations in the CAM core 302. The writing performed by the BIST controller 314 is facilitated by the multiplexer 322 and the multiplexer 324 of the maintenance port 306. In accordance with the present invention, it is possible for the BIST controller 314 to perform writes to the CAM core 302 at the same time searches are performed. That is, searches can be performed in each cycle and the writes can be performed at the same time (e.g., writes can be performed to set up the searches performed during BIST testing). For example, the BIST controller 314 communicates BIST row addresses and BIST block addresses 902 to each of the multiplexers 322 and 324. At the same time, since the BIST operates on one row at a time, the BIST row addresses and the BIST block addresses 902 are communicated to the search port comparator 340 as the expected row and block addresses for searches.
The BIST controller 314 is also shown receiving signals 952 and 954 from the search port 340. The signals 952 and 954 represent “hit” (i.e., a CAM row matches the search data) and multiple hit (referred to as “mult” since more than 1 CAM row matches the search data) results obtained from a search. As shown, signals 952 and 954 originate from the search port 304. During a BIST search, the search port comparator 340 will also be receiving the search addresses by way of bus 904 from the search port 304. In the search port comparator 340, the expected search addresses 902 are compared to the search addresses 904 to produce a search result that is communicated by way of bus 906 to the BIST controller 314. The search port comparator 340 will also compare hit and mults 952 and 954 to expected hits and mults 980 and 982 to produce search results that are also communicated over bus 906. If the search comparator 340 generates a match between 902 and 904, between 952 and 980, or between 954 and 982, then for each match a logic 1 will be produced (otherwise, a logic 0 will be produced if no match occurs). In BIST mode, the BIST controller 314 will also be communicating 2 data bits, 2 tag bits, and 1 valid bit via bus 908 to the BIST maintenance interface 316. In one embodiment, only 4 types of data are written into the CAM, so 2 data bits are sufficient to express the data. The BIST maintenance interface 316 is capable of performing well known expansion operations on the data. In this case, the data from the BIST controller is replicated to generate 32 data bits, 2 tag bits, and 1 valid bit over a bus 910 which communicates with the multiplexer 326. This scheme greatly reduces the number of global wires required to communicate BIST data, greatly simplifying chip routing.
The maintenance port comparator 318 is configured to receive 2 bits of expected data, 2 bits of expected tag and 1 bit of expected valid over bus 916. In one embodiment, there are four types of expected data, and therefore, 2 bits are sufficient to express the expected data. As shown, the maintenance port comparator 318 will receive the output Q for a search from the read/write port 390 over bus 356. The result of the comparison in the maintenance port comparator 318 (i.e., between 916 and 356) is then communicated over bus 914 to the BIST controller 314. If matches are obtained, a logic 1 is generated, otherwise a logic 0 is produced. As shown, the BIST controller 314 is also connected to the IEEE 1149.1 controller 360 in order to communicate control and status signals to the external world. The IEEE 1149.1 standard is herein incorporated by reference.
With the foregoing in mind, the method begins at an operation 500 where all cells in the CAM core are initialized to logic 0 by writing successively to all locations in the CAM. That is, during the initialization, the tag bits, data bits, and valid bits are all initialized to zero. Once initialized, the method moves to an operation 502 where the built-in self-test (BIST) testing will begin with valid bit testing and start at a particular address. The particular address may be any location in the CAM core. Typically BIST testing begins at one point in the CAM core and will proceed address-by-address until the entire CAM core has been tested using the BIST algorithm. Valid bit testing begins at an operation 504 where logic 1 is written to the valid bit of a subrow 0. Simultaneously, a search is performed where the search data and search tag bits are all logic 0, and the expected result is a miss. As mentioned earlier, searching can be performed at each cycle and writing can be performed at the same time searches are being performed.
In one implementation of a CAM, a write operation takes effect only at the end of the cycle in which the operation is initiated, while a search operation takes effect at the beginning of the cycle. Thus when a search and a write are initiated in the same cycle, the write data is not included in the current search, but in a search initiated in a subsequent cycle. Moving from operation 504 to operation 506, it is determined in operation 506 whether a miss occurred, knowing that a miss was expected in operation 504. If a miss did not occur as expected, the method proceeds to an operation 507 where a flag is set indicating that the BIST test failed.
Once the flag is set, the method proceeds to the next operation and moves to A of FIG. 5B. At operation 508, a write of the logic 1 is performed to the valid bit of subrow 1, and simultaneously, a search is performed with the data and tag bits set at logic 0. The expected result will be a miss for operation 508. In operation 506, it is determined whether the miss occurred. If the miss did not occur as expected, the flag will be set indicating that the BIST test failed and the method will proceed to the next operation. Alternatively, if a miss did occur, the method will proceed to operation 510 where a search is performed for data bits and tag bits where the search data and search tag bits are all at logic 0, and the expected result will be a hit.
In response to the search of 510, the method will proceed to operation 512 where it is determined whether a hit occurred. If a hit does not occur as expected, a flag will be set indicating that the BIST test failed in operation 507. Otherwise, the method will proceed to B of
In operation 514, BIST testing continues with tag testing which starts at the same particular address as the valid bit testing began. Now, the method moves to operation 516 where tag bits are written in subrow 0 to 01, and a search is performed with data set to 0's, and the tag bits set to 01 and 01. The expected result will be a miss. Accordingly, the method will move to operation 506 where it is determined whether a miss occurred. If a miss does not occur, the method will proceed again to operation 507 where the flag is set indicating that the BIST lest failed. Otherwise, if the miss did occur, the method proceeds to C of FIG. 5D and the operation 518. In operation 518, tag bits are written in subrow 1 to 01 and a search is performed with data set to 0's, and tag bits set to 00 and 01. The expected result will now be a hit. In operation 512, it is determined whether a hit occurred. If a hit does not occur, the flag will set indicating that the BIST testing failed. Otherwise, the method will move to an operation 520 where a search of data bits and tag bits is performed where the search data is logic 0, and the tag bits are logic 01 and 01. The expected result for the search should be a hit.
From operation 520, the method moves to a decision operation 512 where it is determined whether the hit occurred. If the hit does not occur, the flag will be set indicating that the BIST testing failed. Otherwise, the method will move to D of
In operation 506, it will be determined whether a miss occurred, and if no miss occurred, the flag will be set indicating that the BIST test failed. Otherwise, the method will move to operation 528. In operation 528, the search is performed of data bits and tag bits where the search data is logic 0, and the tag bits are logic 01 and 11. The expected result should be a miss. In operation 506, it is determined whether a miss occurred. If a missdid not occur, the method will move to operation 507 where a flag is set indicating that the BIST testing failed. If a miss did occur, the method will move to F and operation of 530 of FIG. 5G. In operation 530, a search is performed of data bits and tag bits where the search data is logic 0, and the tag bits are logic 01 and 00, and the expected result is a miss. If it is determined that a miss did not occur in operation 506, the method will move to operation 507, where a flag is set indicating that the BIST test failed. Otherwise, the method will move to operation 532 where tag bits in subrow 0 are written to 11 and the search is performed with data set to 0's and tag bits set to 11, and 11. The expected result will be a miss.
In operation 506, it will be determined whether the miss occurred. If the miss did not occur, the method again proceeds to operation 507 where a flag is set indicating that the BIST test failed. Otherwise, the method will move to G of
In operation 542, a search is performed of data bits and tag bits where the search data is logic 0, and the tag bits are logic 10 and 11. The expected results should be a miss. If a miss does not occur, the flag will be set indicating that the BIST testing failed in operation 507. Otherwise, the method will move to operation 544 where a search of data bits and tag bits is performed where the search data is logic 0, and the tag bits are logic 11 and 01, and the expected result is a miss. If a miss does not occur, the method will move to operation 507 where a flag is set indicating that BIST test failed. Otherwise, the method will move to J of FIG. 5K and operation 546. In operation 546, a search is performed of data bits and tag bits where the search data is logic 0 and the tag bits are logic 11 and 10, and the expected result is a miss. If a miss does not occur, the method will proceed to operation 507 where a flag is set indicating the BIST testing failed. Otherwise, if a miss does occur, the method will proceed to operation 548 where a writing of tag bits in subrow 0 to 10, and a search is performed with data set to 0's and the tag bits set to 10 and 10. The expected result should be a miss. If a miss does not occur, the flag will be set indicating that the BIST test failed. If miss does occur, the method will move to K of FIG. 5L and operation 550.
In operation 550, tag bits are written in subrow 1 to 10 and a search is performed with data set to 0's, and tag bits set to 11 and 10, and the expected result is a hit. In operation 512, it is determined whether a hit occurred. If a hit does not occur, this flag will be set indicating that the BIST test failed. Otherwise, the method will proceed to operation 552 where a search of data bits and tag bits is performed where the search data is logic 0, and the tag bits are logic 10 and 10. The expected result should be a hit. If a miss does not occur in operation 506, the method will proceed to operation 507 where a flag is set indicating that the BIST test failed. Otherwise, the method will proceed to L of
In operation 554, a search if performed for data bits and tag bits where the search data is logic 0, and the tag bits are logic 11 and 10, and the expect result is a miss. If a miss does not occur, the flag will be set indicating that the BIST test failed. Otherwise, the method will proceed to operation 556 where a search of data bits and tag bits is performed where the search data is logic 0, and the tag bits are logic 00 and 10. The expected result will be a miss. If a miss does not occur in operation 506, the flag will be set indicating that the BIST test failed, otherwise, the method will proceed to operation 557 where a search of data bits and tag bits is performed where the search data is logic 0 and the tag bits are logic 11 and 10. The expected result should be a miss. If a miss does not occur in operation 506, the method will proceed to operation 507 where a flag is set indicating the BIST has failed. Otherwise, the method will proceed to M of FIG. 5N and operation 558. In operation 558, a search is performed of data bits and tag bits where the search data is logic 0, and the tag bits are logic 10 and 00. The expected result should be a miss. If a miss does not occur in operation 506, the method will proceed to operation 507 where a flag is set indicating that the BIST testing failed. Otherwise, the method will proceed to operation 560 where a search of data bits and tag bits is performed for the search data is logic 0, and the tag bits are logic 10 and 11. The expected result should be a miss. If a miss does not occur, the method will proceed to 507 where a flag is set indicating that the BIST testing failed. Otherwise, the method will proceed to N of FIG. 5O and operation 562.
In operation 562, tag bits are written in subrow 0 to 00, and a search is performed with the data set to 0's and the tag bits set to 00 and 00. The expected result should be a miss. If a miss does not occur, the method will proceed to operation 507 where a flag is set indicating that the BIST test failed. Otherwise, the method will proceed to operation 564. In operation 564, tag bits are written in subrow 1 to 00, and a search is performed with the data set to 0's, and the tag bits set to 10 and 00, where the expected result is a hit. If a hit does not occur, the method will proceed to operation 507 where a flag is set indicating that the BIST test failed. Otherwise, the method will proceed to O of FIG. 5P and operation 566. In operation 566, a search is performed of data bits and tag bits where the search data is logic 0 and the tag bits are logic 00 and 00. The expected result is a hit. If it is determined that a hit does not occur in operation 512, the method will proceed to operation 507 where a flag is set indicating that the BIST test failed.
If a hit did occur, the method proceeds to operation 568 where a search is performed of data bits and tag bits where the search data is logic 0, and the tag bits are logic 10 and 00, and the expected result is a miss. If the result is not a miss, the method will move to operation 507 where the flag is set indicating that the. BIST test failed. Otherwise, the method will proceed to P of FIG. 5Q and operation 570. In operation 570, a search will be performed of data bits and tag bits where the search data is logic 0 and the tag bits are logic 10 and 00. The expected result will be a miss. If a miss does not occur in operation 506, the method will proceed to an operation 507 where a flag is set indicating that the BIST test failed. If a miss does occur, the method will proceed to operation 572 where a search is performed of data bits and tag where the search data is logic 0, and the tag bits are logic 01 and 00, and the expected result is a miss. If a miss does not occur, the flag will be set indicating that the BIST test failed in operation 507. Otherwise, the method will proceed to Q of FIG. 5R and operation 574.
In operation 574, a search will be performed of data bits and tag bits where the search data is logic 0, and the tag bits are logic 00 and 10. The expected result will be a miss. If a miss does not occur, the method will proceed to operation 507 where a flag is set indicating that the BIST test failed. Otherwise, the method will proceed to an operation 576 where a search will be performed of data bits and tag bits where the search data is logic 0, and the tag bits are logic 00 and 01. The expected result should be a miss. If a miss does not occur, the flag will be set in operation 507 indicating that BIST test failed. Otherwise, the method will proceed to R of FIG. 5S. At this point, tag testing will be complete.
The method now moves to R of
In operation 582, “SIF_data” is set to logic 1 and a search is performed simultaneously. A miss is expected in operation 582. The method now moves to operation 506 where it is determined whether a miss occurred. If a miss does not occur, the flag is set indicating that the BIST test failed. Otherwise, the method moves to operation 584 where “SIF_data” is set to logic 0, and a search is simultaneously performed expecting a miss. If it is determined in operation 506 that a miss did not occur, the method proceeds to operation 507 where a flag is set indicating that the BIST test failed. Otherwise, the method moves to operation 586 where “SIF_data” is set to logic 0, and a search is performed expecting a miss. If a miss does not occur, the flag will be set indicating that the BIST test failed in operation 507. If a miss did occur, the method moves to S of FIG. 5P and operation 588.
In operation 588, “SIF_data” is set to logic 0. At the same time, a search is performed and a miss will be expected. In operation 506, it is determined whether the miss occurred. If a miss did not occur, a flag will be set indicating that BIST test failed in operation 507. If a miss did occur, the method will move to operation 589 where the method will repeat operations 586 through 588 “30” more times with SIF_data set to 0 throughout. This is performed 30 more times since each search word is 64 bits long, and operations 582 through 588 together with operation 589 have the effect of walking a 1 through a background of zeros in the search data. Of course, if the words were of different sizes, this operation would be repeated as many times as needed to operate on all data bits.
Once these operations have been repeated, the method will move to operation 590 where data bits are written in subrow 0 to logic 1. At the same time, a search is performed with the data bits at logic 0, and the expected results being a hit. In operation 512, it is determined whether a hit occurred. If a hit did not occur, the flag is set indicating that the BIST test failed. Otherwise, the method will move to operation 592 where data bits are written in subrow 1 to logic 1, and a search is simultaneously performed with the data bits at logic 0, and the expected result being a miss. If a miss did not occur, the flag will be set indicating that the BIST test failed. Otherwise, the method will move to P of FIG. 5U and operation 594. In operation 594, data bits are written in subrow 0 to logic 0, and the valid bit is written as 0, and a search is performed with the data bits at logic 1, and the expected result is a hit.
If a hit does not occur, the method will move to operation 507 where the flag is set indicating that the BIST test failed. Otherwise, the method will move to operation 596. In operation 596, data bits are written in subrow 0 to logic 0, and the valid bit is written as 0, and the search is performed with the data bits at logic 1, and the expected result being a miss. If a miss did not occur, the method moves to 507 where the flag is set indicating that the BIST test failed. If a miss did occur, the method moves to operation 598 where it is determined if there are anymore addresses to test. If there are more addresses to test, the method will go to operation 599 where the method proceeds to the next address and repeats the preceding operations starting at 502 and ending at 598. If all of the memory addresses have been tested, then the method will move to operation 600 where the memory is reset and the method will end.
As mentioned above, the algorithm is configured to perform BIST testing on one row at a time. This is enabled by making only the row being tested “valid,” thus enabling searches during testing only in the valid rows. Of course, a search will always be performed over the entire CAM core, although, testing for matches will only occur in the valid row. This provides a substantial savings in power, thus making the BIST testing a low power test. Furthermore, the BIST testing executed by the BIST controller is capable of operating searches through the search port at the same time as writes are performed through the maintenance port. This, as mentioned above, improves testing efficiency in that searches can be executed at every cycle, and thus searches need not be stopped to enable writes.
In addition to being able to use one BIST controller 314 to execute BIST testing of the CAM cores 302, it is also important to note that the BIST controller 314 can simultaneously perform searches by way of the search ports 304 and writes by way of the maintenance ports 306. The other advantages described above with regard to a single CAM core therefore also apply to embodiments where more than one CAM core is tested using the BIST controller 314.
The present invention may be implemented using any type of integrated circuit logic, state machines, or software driven computer-implemented operations. By way of example, a hardware description language (HDL) based design and synthesis program may be used to design the silicon-level circuitry necessary to appropriately perform the data and control operations in accordance with one embodiment of the present invention. By way of example, a VHDL® hardware description language available from IEEE of New York, N.Y. may be used to design an appropriate silicon-level layout. Although any suitable design tool may be used, another layout tool may include a hardware description language “Verilog®” tool available from Cadence Design Systems, Inc. of Santa Clara, Calif.
The invention may employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. Further, the manipulations performed are often referred to in terms, such as producing, identifying, determining, or comparing.
Any of the operations described herein that form part of the invention are useful machine operations. The invention also relates to a device or an apparatus for performing these operations. The apparatus may be specially constructed for the required purposes, or it may be a general purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general purpose machines may be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations.
Additionally, the various block diagrams may be embodied in any form which may include, for example, any suitable computer layout, semiconductor substrate, semiconductor chip or chips, printed circuit boards, packaged integrated circuits, or software implementations. Accordingly, those skilled in the art will recognize that the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
Gupta, Sanjay, Gibson, Randall
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
4376974, | Mar 31 1980 | SYMBIOS, INC | Associative memory system |
4475194, | Mar 30 1982 | International Business Machines Corporation | Dynamic replacement of defective memory words |
4532606, | Jul 14 1983 | SAMSUNG ELECTRONICS CO , LTD | Content addressable memory cell with shift capability |
4559618, | Sep 13 1982 | Data General Corp. | Content-addressable memory module with associative clear |
4622653, | Oct 29 1984 | Texas Instruments Incorporated | Block associative memory |
4646271, | Dec 23 1983 | Hitachi, Ltd. | Content addressable memory having dual access modes |
4670858, | Jun 07 1983 | Tektronix, Inc.; TEKTRONIX, INC , A COR OF OR | High storage capacity associative memory |
4723224, | Jan 02 1986 | MOTOROLA, INC , A CORP OF DE | Content addressable memory having field masking |
4758982, | Jan 08 1986 | Advanced Micro Devices, Inc. | Quasi content addressable memory |
4794559, | Jul 05 1984 | American Telephone and Telegraph Company, AT&T Bell Laboratories | Content addressable semiconductor memory arrays |
4845668, | Dec 10 1987 | Raytheon Company | Variable field content addressable memory |
4996666, | Aug 12 1988 | Apple Inc | Content-addressable memory system capable of fully parallel magnitude comparisons |
5051949, | Nov 15 1989 | Intersil Corporation | Content addressable memory device |
5053991, | Oct 06 1989 | Lockheed Martin Corporation | Content-addressable memory with soft-match capability |
5107501, | Apr 02 1990 | AT&T Bell Laboratories | Built-in self-test technique for content-addressable memories |
5173909, | Jul 13 1990 | OpNext Japan, Inc | Wavelength tunable laser diode |
5185888, | Aug 22 1984 | Hitachi, Ltd.; Yuzuru, Tanaka | Method and apparatus for data merging/sorting and searching using a plurality of bit-sliced processing units |
5226005, | Nov 19 1990 | Unisys Corporation; UNISYS CORPORATION, A DE CORP | Dual ported content addressable memory cell and array |
5257220, | Mar 13 1992 | Research Foundation of the State Univ. of N.Y. | Digital data memory unit and memory unit array |
5319589, | Apr 17 1992 | Renesas Electronics Corporation | Dynamic content addressable memory device and a method of operating thereof |
5319590, | Dec 04 1992 | Fujitsu, Ltd | Apparatus for storing "Don't Care" in a content addressable memory cell |
5327372, | Jan 17 1992 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device |
5351208, | Apr 27 1992 | CITICORP USA, INC , AS ADMINISTRATIVE AGENT; CITIBANK, N A , AS ADMINISTRATIVE AGENT | Content addressable memory |
5467319, | Sep 20 1993 | Codex, Corp. | CAM array and method of laying out the same |
5535164, | Mar 03 1995 | GLOBALFOUNDRIES Inc | BIST tester for multiple memories |
5555397, | Jan 10 1992 | KAWASAKI MICROELECTRONICS, INC | Priority encoder applicable to large capacity content addressable memory |
5568415, | Feb 19 1993 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Content addressable memory having a pair of memory cells storing don't care states for address translation |
5592407, | Feb 25 1994 | KAWASAKI MICROELECTRONICS, INC | Associative memory |
5608662, | Jan 12 1995 | SOLIDUM SYSTEMS CORPORATION | Packet filter engine |
5619446, | Jan 10 1992 | KAWASAKI MICROELECTRONICS, INC | Hierarchical encoder including timing and data detection devices for a content addressable memory |
5699288, | Jul 18 1996 | International Business Machines Corporation | Compare circuit for content-addressable memories |
5752260, | Apr 29 1996 | International Business Machines Corporation | High-speed, multiple-port, interleaved cache with arbitration of multiple access addresses |
5784709, | Feb 19 1993 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Translating buffer and method for translating addresses utilizing invalid and don't care states |
5787458, | Aug 31 1995 | NEC Corporation | Content addressable memory of a simple construction capable of retrieving a variable word length data |
5818786, | May 24 1995 | KAWASAKI MICROELECTRONICS, INC | Layout method of semiconductor memory and content-addressable memory |
5828593, | Nov 14 1996 | ZARBAÑA DIGITAL FUND LLC | Large-capacity content addressable memory |
5848074, | Dec 25 1995 | Mitsubishi Denki Kabushiki Kaisha | Method and device for testing content addressable memory circuit and content addressable memory circuit with redundancy function |
5859791, | Feb 06 1997 | FOOTHILLS IP LLC | Content addressable memory |
6000008, | Mar 11 1993 | Extreme Networks, Inc | Method and apparatus for matching data items of variable length in a content addressable memory |
6006306, | Jul 02 1997 | WSOU Investments, LLC | Integrated circuit with stage-implemented content-addressable memory cell |
6044005, | Feb 03 1999 | FOOTHILLS IP LLC | Content addressable memory storage device |
6069573, | Jun 17 1996 | SAMSUNG ELECTRONICS CO , LTD | Match and match address signal prioritization in a content addressable memory encoder |
6081440, | Nov 05 1998 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Ternary content addressable memory (CAM) having fast insertion and deletion of data values |
6199140, | Oct 30 1997 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Multiport content addressable memory device and timing signals |
6199149, | Jan 30 1998 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Overlay counter for accelerated graphics port |
6230236, | Aug 28 1997 | FOOTHILLS IP LLC | Content addressable memory system with cascaded memories and self timed signals |
6243281, | Jun 14 2000 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Method and apparatus for accessing a segment of CAM cells in an intra-row configurable CAM system |
6253280, | Mar 19 1999 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Programmable multiple word width CAM architecture |
6272588, | May 30 1997 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Method and apparatus for verifying and characterizing data retention time in a DRAM using built-in test circuitry |
6275406, | Sep 10 1999 | INNOMEMORY LLC | Content address memory circuit with redundant array and method for implementing the same |
6286116, | Mar 26 1999 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Built-in test method for content addressable memories |
6339539, | Sep 10 1999 | INNOMEMORY LLC | Content addressable memory having read/write capabilities that do not interrupt continuous search cycles |
6362990, | Sep 10 1999 | INNOMEMORY LLC | Three port content addressable memory device and methods for implementing the same |
6392910, | Sep 10 1999 | INNOMEMORY LLC | Priority encoder with multiple match function for content addressable memories and methods for implementing the same |
6496950, | Aug 11 1999 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Testing content addressable static memories |
6553453, | Sep 10 1999 | INNOMEMORY LLC | Variable width content addressable memory device for searching variable width data |
6591331, | Dec 06 1999 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Method and apparatus for determining the address of the highest priority matching entry in a segmented content addressable memory device |
6609222, | Sep 10 1999 | Xylon LLC | Methods and circuitry for built-in self-testing of content addressable memories |
EP491498, | |||
EP899668, | |||
WO9923664, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Aug 31 2000 | GUPTA, SANJAY | SIBERCORE TECHNOLOGIES, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019687 | 0443 | |
Sep 01 2000 | GIBSON, G F RANDALL | SIBERCORE TECHNOLOGIES, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019687 | 0443 | |
Dec 17 2004 | SIBERCORE TECHNOLOGIES, INC | SIBERCORE TECHNOLOGIES INCORPORATED FORMERLY 6320848 CANADA INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019687 | 0445 | |
Aug 18 2005 | SIBERCORE TECHNOLOGIES, INC | Core Networks LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 019687 | 0450 | |
Aug 13 2015 | Core Networks LLC | Xylon LLC | MERGER SEE DOCUMENT FOR DETAILS | 036876 | 0519 | |
Nov 01 2018 | Xylon LLC | INTELLECTUAL VENTURES ASSETS 97 LLC | NUNC PRO TUNC ASSIGNMENT SEE DOCUMENT FOR DETAILS | 047782 | 0379 | |
Nov 30 2018 | INTELLECTUAL VENTURES ASSETS 97 LLC | INNOMEMORY LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 048036 | 0968 |
Date | Maintenance Fee Events |
Jan 19 2011 | ASPN: Payor Number Assigned. |
Feb 11 2011 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Dec 31 2014 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Dec 07 2013 | 4 years fee payment window open |
Jun 07 2014 | 6 months grace period start (w surcharge) |
Dec 07 2014 | patent expiry (for year 4) |
Dec 07 2016 | 2 years to revive unintentionally abandoned end. (for year 4) |
Dec 07 2017 | 8 years fee payment window open |
Jun 07 2018 | 6 months grace period start (w surcharge) |
Dec 07 2018 | patent expiry (for year 8) |
Dec 07 2020 | 2 years to revive unintentionally abandoned end. (for year 8) |
Dec 07 2021 | 12 years fee payment window open |
Jun 07 2022 | 6 months grace period start (w surcharge) |
Dec 07 2022 | patent expiry (for year 12) |
Dec 07 2024 | 2 years to revive unintentionally abandoned end. (for year 12) |