An integrated circuit processes communication packets and comprises a pointer cache and control logic. The pointer cache store pointers that correspond to external buffers that are external to the integrated circuit and configured to store the communication packets. The control logic allocates the external buffers as the corresponding pointers are read from the pointer cache and de-allocates the external buffers as the corresponding pointers are written back to the pointer cache.

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Patent
   RE42092
Priority
Aug 17 1999
Filed
May 16 2008
Issued
Feb 01 2011
Expiry
Aug 16 2020
Inventors
Snyder, II…
Assg.orig
Conexant S…
Assg.curr
BICAMERAL …
Entity
Large
Referenced by
5
References
28
Maint.:
all paid
0. 33. An integrated circuit that processes communication packets, the integrated circuit comprising:
processing facilities configured to create a plurality of external buffers that are external to the integrated circuit and configured to store the communication packets where each external buffer is associated with a pointer that corresponds to the external buffer; and
a pointer cache configured to store the pointers that correspond to the external buffers,
wherein the processing facilities are further configured to:
allocate the external buffers as the corresponding pointers are read from the pointer cache and de-allocate the external buffers as the corresponding pointers are written back to the pointer cache,
transfer an exhaustion signal if a number of the pointers to the de-allocated buffers reaches a minimum threshold, and
create additional external buffers and their corresponding pointers in response to the exhaustion signal.
1. An integrated circuit that processes communication packets, the integrated circuit comprising:
a core processor configured to create a plurality of external buffers that are external to the integrated circuit and configured to store the communication packets where each external buffers is associated with a pointer that corresponds to the external buffer;
a pointer cache configured to store the pointers that correspond to the external buffers;
control logic configured to allocate the external buffers as the corresponding pointers are read from the pointer cache and de-allocate the external buffers as the corresponding pointers are written back to the pointer cache wherein the control logic is configured to transfer an exhaustion signal if a number of the pointers to the de-allocated buffers reaches a minimum threshold; and
the core processor configured to create additional external buffers and their corresponding pointers in response to the exhaustion signal.
17. A method of operating an integrated circuit that processes communication packets, the method comprising:
creating a plurality of external buffers that are external to the integrated circuit and that are configured to store the communication packets, ;
creating a plurality of pointers where each pointer corresponds to one of the plurality of external buffers;
storing a subset of the plurality of pointers in a pointer cache in the integrated circuit;
allocating the external buffers as the corresponding pointers are read from the pointer cache;
de-allocating the external buffers as the corresponding pointers are written back to the pointer cache;
transferring an exhaustion signal if a number of the pointers to the de-allocated buffers reaches a minimum threshold; and
in response to the exhaustion signal, creating additional external buffers and their corresponding pointers where the additional external buffers are external to the integrated circuit and are configured to store the communication packets.
0. 34. An integrated circuit that processes communication packets, the integrated circuit comprising:
processing facilities configured to create a plurality of external buffers that are external to the integrated circuit and configured to store the communication packets where each external buffer is associated with a pointer that corresponds to the external buffer; and
a pointer cache configured to store the pointers that correspond to the external buffers,
wherein the processing facilities are further configured to:
allocate the external buffers by modifying the pointer cache to indicate that pointers in the pointer cache corresponding to the external buffers are in use and de-allocate the external buffers by modifying the pointer cache to indicate that pointers in the pointer cache corresponding to the external buffers are unused,
transfer an exhaustion signal if a number of the pointers in the pointer cache corresponding to the external buffers indicated to be unused reaches a minimum threshold, and
create additional external buffers and their corresponding pointers in response to the exhaustion signal.
0. 51. A method of operating an integrated circuit that processes communication packets, the method comprising:
creating a plurality of external buffers that are external to the integrated circuit and that are configured to store the communication packets;
creating a plurality of pointers where each pointer corresponds to one of the plurality of external buffers;
storing a subset of the plurality of pointers in a pointer cache in the integrated circuit;
allocating the external buffers by modifying the pointer cache to indicate that pointers in the pointer cache corresponding to the external buffers are in use;
de-allocating the external buffers by modifying the pointer cache to indicate that pointers in the pointer cache corresponding to the external buffers are unused;
transferring an exhaustion signal if a number of the pointers indicated to be unused reaches a minimum threshold; and
in response to the exhaustion signal, creating additional external buffers and their corresponding pointers where the additional external buffers are external to the integrated circuit and are configured to store the communication packets.
2. The integrated circuit of claim 1 wherein the control logic is configured to track a number of the pointers to the de-allocated external buffers.
3. The integrated circuit of claim 1 wherein the control logic is configured to transfer additional pointers to the pointer cache if a number of the pointers to the de-allocated buffers reaches a minimum threshold.
4. The integrated circuit of claim 1 wherein the control logic is configured to transfer an excess portion of the pointers from the pointer cache if the number of the pointers to the de-allocated buffers reaches a maximum threshold.
5. The integrated circuit of claim 1 wherein the external buffers are distributed among at least two pools.
6. The integrated circuit of claim 1 wherein the external buffers and the pointers to the external buffers are distributed among a plurality of classes.
7. The integrated circuit of claim 6 wherein the control logic is configured to track a number of the pointers to the de-allocated external buffers for at least one of the classes.
8. The integrated circuit of claim 6 wherein the control logic is configured to track a number of the pointers to the allocated external buffers for at least one of the classes.
9. The integrated circuit of claim 6 wherein the control logic is configured to borrow at least some of the pointers from a first one of the classes for use by a second one of the classes.
10. The integrated circuit of claim 6 wherein the control logic is configured to redistribute at least some of the pointers from a first one of the classes to a second one of the classes.
11. The integrated circuit of claim 6 wherein the control logic is configured to transfer an exhaustion signal if a number of the pointers to the de-allocated buffers in one of the classes reaches a minimum threshold.
12. The integrated circuit of claim 6 wherein the control logic is configured to track a number of the pointer distributed to one of the classes.
13. The integrated circuit of claim 6 wherein at least one of the classes is associated only with constant bit rate packets.
14. The integrated circuit of claim 6 wherein at least one of the classes is associated only with available bit rate packets.
15. The integrated circuit of claim 6 wherein at least one of the classes is associated only with variable bit rate packets.
16. The integrated circuit of claim 6 wherein at least one of the classes is associated only with unspecified bit rate packets.
18. The method of claim 17 further comprising tracking a the number of the pointers to the de-allocated external buffers.
19. The method of claim 17 further comprising transferring additional pointers to the pointer cache if a number of the pointers to the de-allocated buffers reaches a minimum threshold.
20. The method of claim 17 further comprising transferring an excess portion of the pointers from the pointer cache if the number of the pointers to the de-allocated buffers reaches a maximum threshold.
21. The method of claim 17 wherein the external buffers are distributed among at least two pools.
22. The method of claim 17 wherein the external buffers and the pointers to the external buffers are distributed among a plurality of classes.
23. The method of claim 22 further comprising tracking a number of the pointers to the de-allocated external buffers for at least one of the classes.
24. The method of claim 22 further comprising tracking a number of the pointers to the allocated external buffers for at least one of the classes.
25. The method of claim 22 further comprising borrowing at least some of the pointers from a first one of the classes for use by a second one of the classes.
26. The method of claim 22 further comprising re-distributing at least some of the pointers from a first one of the classes to a second one of the classes.
27. The method of claim 22 further comprising tracking a number of pointers distributed to one of the classes.
28. The method of claim 22 wherein at least one of the classes is associated only with constant bit rate packets.
29. The method of claim 22 wherein at least one of the classes is associated only with available bit rate packets.
30. The method of claim 22 wherein at least one of the classes is associated only with variable bit rate packets.
31. The method of claim 22 wherein at least one of the classes is associated only with unspecified bit rate packets.
0. 32. The integrated circuit of claim 6 wherein at least one of the classes is associated with a set of one or more types of network traffic.
0. 35. The integrated circuit of claim 34 wherein the processing facilities are configured to track the number of the pointers to the de-allocated external buffers.
0. 36. The integrated circuit of claim 34 wherein the processing facilities are configured to transfer additional pointers to the pointer cache if the number of the pointers to the de-allocated buffers reaches a minimum threshold.
0. 37. The integrated circuit of claim 34 wherein the processing facilities are configured to transfer an excess portion of the pointers from the pointer cache if the number of the pointers to the de-allocated buffers reaches a maximum threshold.
0. 38. The integrated circuit of claim 34 wherein the external buffers are distributed among at least two pools.
0. 39. The integrated circuit of claim 34 wherein the external buffers and the pointers to the external buffers are distributed among a plurality of classes.
0. 40. The integrated circuit of claim 39 wherein the processing facilities are configured to track the number of the pointers to the de-allocated external buffers for at least one of the classes.
0. 41. The integrated circuit of claim 39 wherein the processing facilities are configured to track the number of the pointers to the allocated external buffers for at least one of the classes.
0. 42. The integrated circuit of claim 39 wherein the processing facilities are configured to borrow at least some of the pointers from a first one of the classes for use by a second one of the classes.
0. 43. The integrated circuit of claim 39 wherein the processing facilities are configured to redistribute at least some of the pointers from a first one of the classes to a second one of the classes.
0. 44. The integrated circuit of claim 39 wherein the processing facilities are configured to transfer an exhaustion signal if the number of the pointers to the de-allocated buffers in one of the classes reaches a minimum threshold.
0. 45. The integrated circuit of claim 39 wherein the processing facilities are configured to track the number of the pointers distributed to one of the classes.
0. 46. The integrated circuit of claim 39 wherein at least one of the classes is associated only with constant bit rate packets.
0. 47. The integrated circuit of claim 39 wherein at least one of the classes is associated only with available bit rate packets.
0. 48. The integrated circuit of claim 39 wherein at least one of the classes is associated only with variable bit rate packets.
0. 49. The integrated circuit of claim 39 wherein at least one of the classes is associated with a set of one or more types of network traffic.
0. 50. The integrated circuit of claim 39 wherein at least one of the classes is associated only with unspecified bit rate packets.
0. 52. The method of claim 51 further comprising tracking the number of the pointers to the de-allocated external buffers.
0. 53. The method of claim 51 further comprising transferring additional pointers to the pointer cache if the number of the pointers to the de-allocated buffers reaches a minimum threshold.
0. 54. The method of claim 51 further comprising transferring an excess portion of the pointers from the pointer cache if the number of the pointers to the de-allocated buffers reaches a maximum threshold.
0. 55. The method of claim 51 wherein the external buffers are distributed among at least two pools.
0. 56. The method of claim 51 wherein the external buffers and the pointers to the external buffers are distributed among a plurality of classes.
0. 57. The method of claim 56 further comprising tracking the number of the pointers to the de-allocated external buffers for at least one of the classes.
0. 58. The method of claim 56 further comprising tracking the number of the pointers to the allocated external buffers for at least one of the classes.
0. 59. The method of claim 56 further comprising borrowing at least some of the pointers from a first one of the classes for use by a second one of the classes.
0. 60. The method of claim 56 further comprising re-distributing at least some of the pointers from a first one of the classes to a second one of the classes.
0. 61. The method of claim 56 further comprising tracking the number of pointers distributed to one of the classes.
0. 62. The method of claim 56 wherein at least one of the classes is associated only with constant bit rate packets.
0. 63. The method of claim 56 wherein at least one of the classes is associated only with available bit rate packets.
0. 64. The method of claim 56 wherein at least one of the classes is associated only with variable bit rate packets.
0. 65. The method of claim 56 wherein at least one of the classes is associated only with unspecified bit rate packets.
0. 66. The method of claim 56 wherein at least one of the classes is associated with a set of one or more types of network traffic.
5 6 is a table that illustrates buffer classes in an example of the invention. In the example of FIG. 3 6, there are 16 classes with 500 external buffers each for a total of 8,000 external buffers. Each class has a type: static, exclusive, or shared. Static classes use their own external buffers without sharing. Exclusive classes use their own external buffers first, and then borrow external buffers from the fail-over classes. De-allocated external buffers from a given exclusive class are credited to the associated fail-over class until the number of borrowed external buffers is zero. Shared classes use their own external buffers and comprise the fail-over external buffers for the exclusive classes.

Buffer classes are used to differentiate services among traffic streams by assigning different streams to different classes of external buffers. Traffic streams offering a higher quality-of-service are typically provided with greater access to external buffers. Bursty traffic may need an elastic exclusive/shared class arrangement. A class may be associated with only one type of traffic, such as Constant Bit Rate (CBR), Available Bit Rate (ABR), Variable Bit Rate (VBR), or Unspecified Bit Rate (UBR). CBR traffic without bursts typically uses static classes. ABR traffic uses exclusive and shared external buffer classes to respectively handle minimum cell rates and bursts. VBR and UBR traffic typically use shared buffer classes.

The external buffers are separated into two separately managed pools A and B. Pools can be used for service differentiation. Pools are also helpful when the external buffers are located in separate memory devices, so each device may have its own independently managed pool.

For each class, control logic 524 tracks the number of pointers in pointer cache 523 that point to the de-allocated external buffers and the number of pointers in pointer cache 523 that point to the allocated external buffers. If the number of pointers to the de-allocated external buffers in one of the classes reaches a minimum threshold for that class, control logic 524 transfers an exhaustion signal for that class to core processor 104. If the class is exclusive, control logic 524 may also borrow pointers from the corresponding fail-over class for use by the exclusive class, although conditions and thresholds may be used to limit the amount of borrowing. Control logic 524 tracks the number of pointers distributed to each class and may re-distribute pointers from one class to another based on certain conditions, such as traffic loads. In addition, more ABR traffic may require more exclusive buffers at the expense of shared buffers where more UBR traffic has the opposite effect.

Scheduler Circuitry—FIGS. 7-9

FIGS. 7-9 depict a specific example of scheduler circuitry in accord with the present invention. Those skilled in the art will appreciate numerous variations from this example that do not depart from the scope of the invention. Those skilled in the art will also appreciate that various features could be combined to form multiple variations of the invention. Those skilled in the art will appreciate that some conventional aspects of FIGS. 7-9 have been simplified or omitted for clarity.

FIG. 7 is a block diagram that illustrates scheduler 105 in an example of the invention. Scheduler 105 comprises a hardware circuitry engine that is firmware-programmable in that it operates in response to state bits and register content. In contrast, core processor 104 is a micro-processor that executes application software. Scheduler 105 operates in parallel with core processor 104 to conserve core processor capacity by off-loading numerous tasks from the core processor.

Scheduler 105 comprises control logic 730, scheduling boards 731-732, and context RAM 735. Board 731 is vertically separated into time periods 741-745 where a “1” indicates a reservation at that time period and a “0” indicates no reservation at that time period. Board 731 is horizontally separated into priority levels 751-754 that are ranked from high at priority level #1 to low at priority level #4. Board 732 is similar to board 731, but has two priority levels and ten time periods. Control logic 730 process boards 731-732 independently of one another.

Context RAM 735 has entries 736 that each hold one of thousands of possible channel descriptor identifiers. The channel descriptors that correspond to these identifiers describe how packet transmission should be handled for a channel. For example, a channel descriptor indicates where packets for the channel are stored and how frequently they should be transmitted. Boards 731-732 are each associated with a different portion of context RAM 735. As indicated by the arrows, each time period at each priority level on each board is associated with its own one of the context RAM entries 736, and thus, with a possibly unique channel descriptor. To serve a reservation, control logic 730 sends a request that identifies the corresponding channel descriptor to co-processor circuitry 107.

In some examples of the invention, there are 64,000 channel descriptors, and thus, 64,000 corresponding board time periods. The 64,000 time periods can be distributed among boards in various combinations of 2,000, 4,000, 8,000, 16,000, 32,000, or 64,000 time periods per board. Boards can be separated into 1, 2, or, 4 priority levels that run concurrently in time. Each priority level uses up time periods, so an 8,000 time period board with four priority levels has 2,000 time periods per priority level that run concurrently. The minimum number of reservations in a given priority level is 512.

FIGS. 8-9 are block diagrams that illustrate scheduling board 731 in an example of the invention. Board 731 includes five time periods 741-745 and four priority levels 751-754. Fence 860 indicates the time period that control logic 730 is currently processing in each priority level. Control logic 730 processes board 731 to serve reservations and initiate packet transmissions at regular time intervals. At each time interval, referred to as a “GET”, control logic 730 gets one reservation and advances fence 860. At a GET, fence 860 may advance in some priority levels but not others. As a result, fence 860 may be at different time periods in different priority levels.

At a GET, control logic 730 serves the highest priority reservation at fence 860. Control logic 860 then advances fence 860 to the next time period in the priority level that is served. Control logic 860 also advances fence 860 to the next time period in other priority levels that did not have a reservation at fence 860. Control logic 860 does not advance fence 860 at priority levels that had an un-served reservation at fence 860.

On FIG. 8, fence 860 is at time period 3 for all priority levels, and priority level 1 is served, priority level 2 is un-served, and priority levels 3 and 4 are not reserved. As a result and as shown on FIG. 9, fence 860 is advanced to time period 4 at priority levels 1, 3, and 4, but not at priority level 2. Priority level 2 will have the highest priority reservation at the next GET, because fence 860 remains at time period 3 in priority level 2, and priority level 1 has no reservation at time period 4.

The various scheduling boards and priority levels provide a robust mechanism for differentiating services between traffic streams based on service level agreements. For example, the highest priority level of board 732 could be traffic with a guaranteed bandwidth rate, and the lower priority level could be traffic without any bandwidth guarantee. Board 731 has four priority levels and may have Constant Bit Rate (CBR) traffic at the highest priority, real time Variable Bit Rate (VBR) traffic at the second-highest priority, non-real-time VBR traffic at the third-highest priority level, and Available Bit Rate (ABR) traffic at the fourth and lowest priority level. Traffic can also be allocated among boards to provide expensive high-quality service from one board, and cheap moderate-quality service from another board. Prioritization circuitry within co-processor circuitry 107 can assign channels on the high-quality board to the highest priority queue to core processor 104 and assign channels on the moderate-quality board to the highest priority queue to core processor 104.

A board stall occurs when a higher priority level starves a lower priority level, and a reservation at the lower priority level will never get served. In a board stall, control logic 730 does not advance fence 860 until the stall is cured. If a force option is selected, the indicated priority level is serviced at the next GET. If a scan option is selected, the above-described board processing is modified. All reservations in the highest priority level are serviced before any lower priority levels are serviced. In lower priority levels during this time, fence 860 is advanced at a GET if the time period is not reserved. The scan process repeats for the next highest priority level down through the lowest priority level.

Control logic 730 schedules a reservation in response to a “PUT” generated by core processor 104 or scheduler 105. Control logic 730 schedules the reservation by determining a start position. The start position is a number of time periods from the current fence location where the search starts for an available time period for the reservation. The start position may be specified in the PUT, or it may be calculated by control logic 730.

To calculate the start position, control logic 730 first retrieves scheduling parameters from the proper context buffer in co-processor circuitry 107 using a pointer in the PUT. Control logic 730 also increments the in-use count for the context buffer. Control logic 730 then executes dual Guaranteed Cell Rate (GCR) scheduling algorithms based on the scheduling parameters to determine the start position.

The scheduling parameters include a scheduling board indicator, first choice priority level, and second choice priority level that is a higher priority than the first choice. If the first priority level does not work for some reason, then the second priority level is attempted in a priority promotion. In a priority promotion, the control logic 730 tries to find a reservation based on the Minimum Cell Rate (MCR), and if nothing is available, then control logic 730 tries to find a reservation based on the Peak Cell Rate (PCR).

The scheduling parameters also include usage values that determine how the dual algorithms are used. Based on the usage values, algorithm 1 and algorithm 2 are respectively be used for:

    • PCR/nothing
    • MCR/PCR, or
    • Sustained Cell Rate (SCR)/PCR.
      For algorithm 1 and algorithm 2, the scheduling parameters respectively include:
    • Theoretical Arrival Times (TAT1/TAT2),
    • Inter-Cell Intervals (ICI1/ICI2), and
    • limits (L1/L2).
      The TATs are the expected arrival times, and the ICIs are the transmit frequencies. TATs are re-initialized if a reservation has been inactive for a long time (about one second).

The two scheduling algorithms are specified by the following psuedocode where PTt is the present time, TAT1t-1, TAT2t-1 are old times read from the context buffer, and TAT1t, TAT2t are new times written to the context buffer.
if (PUT w/ no update instruction) {
ICI1 = 0
ICI2 = 0
PIPELAT = 0
} // else PUT with update; use the ICIs as provided
TAT2t = max (TAT2t−1 + ICI2, PTt + ICI2)
if (ALG==MCR/PCR)
TAT1start = max (PTt − L1, min (TAT1t−1 + ICI1, PTt + L1))
else TAT1start = max (TAT1t−1 + ICI1, PTt + ICI1)
if (ALG==PCR/none) {
start position = max (0, TAT1t − L1 − PTt)
} else if (ALG==SCR/PCR) {
start position = max (0, TAT2t − L2 − PTt, TAT1t − L1 − PTt)
} else if (ALG==MCR/PCR) {
start position = max (0, TAT2t − L2 − PTt)
}
TAT2t = max (TAT2start, landing position + PTt)
if (ALG==MCR/PCR) TAT1t = TAT1start
else TAT1t = max (TAT1start, landing position + PTt)
if (PUT with write instruction) {
write TAT1t, TAT2t, back to context buffer
}
decrement in-use count.

In addition to determining the starting position, control logic 730 determines the board configuration, fence location, and the oldest reservation at the fence in each priority level. Control logic 730 locates the start position from the fence at the selected priority level and on the selected scheduling board. Control logic 730 then searches for an available reservation time period. If the time period at the start time is already reserved, then the next available time period is reserved.

The number of time periods between the fence and the reserved time period is referred to as the landing position. The landing position must be smaller than the board to avoid wrapping around the board and reserving a time period that is improperly close to the fence. It may be the case that the priority level is full and reservations only open up as the fence is advanced. In this situation, any PUT will be reserved just behind the advancing fence.

Once the reservation is made, the applicable channel descriptor identifier is placed in the corresponding entry in context RAM 735. The scheduling parameters may also be updated and written back to the context buffer. The in-use count for the context buffer is decremented.

Those skilled in the art will appreciate variations of the above-described embodiments that fall within the scope of the invention. As a result, the invention is not limited to the specific examples and illustrations discussed above, but only by the following claims and their equivalents.

INVENTORS:

Snyder, II, Wilson P., Tompkins, Joseph B., Lussier, Daniel J.

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