Data transform processing apparatus and method

Abstract

A data transform processing apparatus comprising a first lossless transform circuit to perform two step ladder operation processings of receiving unweighted normalized data then outputting weighted nonnormalized rotation-transformed data, and a second lossless transform circuit to perform two step ladder operation processings of receiving the weighted nonnormalized rotation-transformed data from the first lossless transform circuit then performing inverse weighting and outputting unweighted normalized rotation-transformed data, wherein the outputs from the first lossless transform circuit are interchanged and supplied to the second lossless transform circuit.

Description

Y1=(aX0−a²X1+X2−aX3)/(1+a²)
Y2=(aX0+X1−a²X2−aX3)/(1+a²)
Y3=(a²X0+aX1+aX2+X3)/(1+a²)  [Expression 1]

Assuming that the multiplication coefficients for the input data are vectors, all the four vectors corresponding to the four transform expressions are orthogonal to each other (the inner product is “0”). Further, as the absolute vector value is “1”, a 4-point normal orthogonal transform is realized.

In the conventional 4-point normal orthogonal transform using four rotation processings, even if the four rotation processings have the same rotational angle, the respective rotation processings are replaced with three-step ladder operations, so that the transform is realized by total 12 ladder operations. However, in the present embodiment, the transform can be realized by eight step ladder operations.

In the conventional lossless transform, as rounding processing is performed in each ladder operation, 12 rounding processings are necessary. On the other hand, according to the second embodiment, only 8 rounding processings are performed as shown in FIG. 7, thus the transform errors regarding the linear transforms can be reduced.

First Modification to Second Embodiment

The two lossless 2-point transforms may be those in FIGS. 5A and 6A. As the rotational directions in FIG. 6A are inverse of those in FIG. 5A, the two data inputted to the FIG. 6A side are interchanged as shown in FIG. 8.

FIG. 8 is a block diagram showing the lossless 4-point orthogonal transform according to a first modification to the second embodiment of the present invention.

The modification means that the lossless 4-point orthogonal transform can be realized with two lossless 2-point transforms having inverse rotational directions.

The transform expressions of the 4-point orthogonal transform obtained by the structure in FIG. 8 are as follows. Note that the rounding processings are ignored and the transforms are expressed as liner transforms. It is understood from a comparison with the transform expressions in FIG. 7 that the third and the fourth expressions are interchanged in correspondence with the interchanged input data and the inverse directions of the rotation processings.
Y0=(X0−aX1−aX2+a²X3)/(1+a²)
Y1=(aX0−a²X1+X2−aX3)/(1+a²)
Y2=(a²X0+aX1+aX2+X3)/(1+a²)
Y3=(aX0+X1−a²X2−aX3)/(1+a²)  [Expression 2]

Second Modification to Second Embodiment

Further, in a case where the structure in FIG. 7 is modified as a structure in FIG. 9, the number of rounding processings can be reduced and the transform errors can be further reduced.

FIG. 9 is a block diagram showing the lossless 4-point orthogonal transform according to second modification to the second embodiment.

In FIG. 9, the rounding processing in the second step ladder operation in the lossless transform 501 and the rounding processing in the first step ladder operation in the lossless transform 504 in FIG. 7 are integrated. That is, losslessness can be maintained even in a case where the results of multiplications are added then rounding processing is performed once and the result is added to data as the subject of addition.

Further, the rounding processing in the second step ladder operation in the transform 503 and the rounding processing in the first step ladder operation in the transform 502 in FIG. 7 can be integrated.

Next, the integrated rounding processing is shifted to a position after the third addition processing in the ladder operation. FIG. 9 shows such shifted rounding processors denoted by numerals 801 and 803. The rounding processing can be shifted since, assuming that round( ) is a rounding function, R, a real number, and N, an integer, the following relation can be established.
round (R)+N=round (R+N)  [Expression 3]

Note that the left side corresponds to the rounding before the shift, and the right side, to the rounding after the shift. The expression 3 indicates that the result of rounding processing performed after addition of a real number to an integer is the same as that of rounding processing performed before addition of rounded result to the integer. The real number corresponds to the sum of the results of multiplications in the second step and third step ladder operation respectively, before the new rounding processors 801 and 803. Note that the rounding processing of the embodiment may be a most general rounding off (to the nearest whole number), or may be rounding up or rounding down.

Third Modification to Second Embodiment

The structure in FIG. 7 may be modified as shown in FIG. 10.

FIG. 10 is a block diagram showing the lossless 4-point orthogonal transform according to a third modification to the second embodiment.

In FIG. 10, the multiplication with the multiplication coefficient {a/(1+a²)} in FIG. 7 is commonalized. This modification can be easily understood by those skilled in the art. Numeral 901 denotes a commonalized multiplication processor, numeral 903 denotes a subtraction processor to integrate data for commonality of multiplication, numeral 905 denotes a rounding processor to obtain an integer from the result of multiplication by the multiplication processor 901, and numerals 907 and 909 denote addition processor to add integer data to other data. The other processors are the same as those described above.

The feature of the structure in FIG. 10 is that the operation scale of the lossless 4-point orthogonal transform is smaller than that of two lossless 2-point orthogonal transforms (although one subtraction processing is added, one multiplication as a more complicated operation is eliminated. This is a great difference in hardware).

In the case of the modification in FIG. 10, it cannot be say that all the processing is made only with ladder operations. However, it can be interpreted that the structure in FIG. 10 is also made with all the ladder operations by expanding the ladder operations as follows.

A normal ladder operation is a 1-input 1-output operation, however, in this modification, the structure in FIG. 10 including processors 901, 903, 905, 907 and 909 is considered as a 2-input 2-output ladder operation. Further, an n-input m-output ladder operation can be made. In this case, the number of multiplication processor is limited to one. Further, the expanded ladder operation needs an addition/subtraction processor for integration of plural input data to the one multiplication processor.

By introducing this expanded ladder operation, it can be said that the structure in FIG. 10 has four 1-input 1-output ladder operations and one 2-input 2-output ladder operation.

In a case where the rounding processings are removed from the structure in FIG. 10, a liner 4-point orthogonal transform (lossy transform) can be realized with a small amount of operation. That is, the five rounding processors are removed from FIG. 10 as shown in FIG. 11.

As the structure in FIG. 11 is similar to that in FIG. 10, the structure in FIG. 11 is included in this embodiment, however, the structure in FIG. 11 is advantageous as a high-speed liner orthogonal transform operation method having higher versatility than a lossless transform. Further, the structure in FIG. 11 can be modified as shown in FIG. 18, in which the number of multiplication processings in the ladder operations can be finally reduced to four. In FIG. 18, a lossless transform can also be realized by carefully introducing rounding processing. Note that in FIG. 18, numeral 1801 denotes a multiplier for multiplication by a coefficient a; numeral 1803 denotes an adder; and numeral 1805 denotes a subtracter.

Fourth Modification to Second Embodiment

Further, in FIG. 7, when a=TAN(θ)=1 holds, the 4-point orthogonal transform becomes a lossless 4-point Hadamard transform.

Generally, upon Hadamard transform, input data are rearranged (for example, a butterfly operation is performed between X0 and X3), however, the input data rearrangement is not performed but the output data are rearranged.

In the structure in FIG. 7, on the assumption that a=1 holds, the output rearrangement is performed as shown in FIG. 12.

FIG. 12 is a block diagram showing the lossless 4-point orthogonal transform according to a fourth modification to the second embodiment.

In a case where the multiplication coefficient in the ladder operation is an integer value, as the value below decimal point is “0”, the rounding processing is not necessary, therefore the number of rounding processings is reduced. Further, as the multiplication coefficient (½) can be realized only by bit shift, the multiplier can be omitted.

The structure in FIG. 12 can be modified as in the case of the second modification (FIG. 9) and the third modification (FIG. 10). The structure of the modification as in the case of FIG. 10 having a significant meaning will be described with reference to FIG. 13.

FIG. 13 is a block diagram showing the lossless 4-point orthogonal transform in a case where a=1 holds in FIG. 10.

In the structure in FIG. 13, the lossless 4-point orthogonal transform can be realized with a bit shift (½) 1300, one rounding processing 1301 and seven addition/subtraction processings 1302 to 1308. The amount of operation is smaller than that when the transform is realized using butterfly operation as a high-speed operation in a linear Hadamard transform.

On the other hand, the following document 2 shows the structure of lossless 4-point Hadamard transform. In the document 2, to realize the lossless transform, a 4-point Hadamard matrix is divided into triangular matrices and replaced with ladder operations. In this complicated structure, the number of addition processings is larger than that in the structure in FIG. 12 obtained from the fourth modification to the second embodiment by one, that is, eight addition/subtraction processings are required. In use of the second embodiment, a particular solution of generalized lossless 4-point orthogonal transform can be obtained, and further, the number of addition/subtraction processors can be minimized by slight modification.

(Document 2) Shinji Fukuma, Kohichi Ohyama, Masahiro Iwahashi and Nori Kanbayashi, “Lossless 8-Point High-Speed Discrete Cosine Transform Utilizing Lossless Hadamard Transform”, Singaku Gihou, IE99-65, pp. 37-44, October 1999

Application of Second Embodiment

In the 4-point DCT operation shown in FIG. 2, rotation processing at (3π/8) is required. The rotational angle (3π/8) may be changed to rotation processing at (π/8) by interchange of transform space axes or sign inversion, however, in this example, the rotation processing at (3π/8) without any change is performed. In a case where the 4-point DCT is changed to two-dimensional operation and the order of a part of horizontal processing and the order of a part of vertical processing are interchanged, the following operation locally appears as intermediate processing. $\begin{array}{cc}\left[\begin{array}{cc}\cos \frac{3\pi }{8}& \sin \frac{3\pi }{8}\\ -\sin \frac{3\pi }{8}& \cos \frac{3\pi }{8}\end{array}\right]\left[\begin{array}{cc}{X}_{11}& X_{12}\\ X_{21}& X_{22}\end{array}\right]\left[\begin{array}{cc}\cos \frac{3\pi }{8}& -\sin \frac{3\pi }{8}\\ \sin \frac{3\pi }{8}& \cos \frac{3\pi }{8}\end{array}\right]& \left[\mathrm{Expression}4\right]\end{array}$

In the expression 4, components X₁₁, X₁₂, X₂₁, and X₂₂ are data in the middle of operation. If the left side transform matrix is subjected to the horizontal processing, the right side transform matrix corresponds to the vertical processing. Both transform matrices express rotation processing at (3π/8). In a linear transform, any of the transform processings can be performed first (at this time, as rounding processing for lossless transform is not inserted, the transform is not a lossless transform but a linear transform), however, in this example, the left transform matrix is first subjected to processing.

More specifically, the rotation processing at (3π/8) is performed on two pairs of data, (X₁₁, X₂₁) and (X₁₂, X₂₂), then the results of transform is transposed, for example, a part of the data are interchanged and the rotation processing at (3π/8) is performed again. This processing is realized as a lossless transform in the structures in FIGS. 5 to 9 where θ=3π/8 holds.

Third Embodiment

In this embodiment, orthogonal transform processing capable of selection between the 2-point orthogonal transform and the 4-point orthogonal transform is provided by using the structures in FIGS. 5A and 5B described in the first embodiment, and a data selector. The structure for the processing is as shown in FIG. 14.

FIG. 14 is a block diagram showing the lossless 4-point orthogonal transform according to a third embodiment of the present invention.

In this structure, a new constituent element is a data selector 1201. If the data flow is changed by the data selector 1201, the lossless 4-point orthogonal transform is realized, whereas if the data flow is not changed by the data selector 1201, the two lossless 2-point orthogonal transforms are realized.

Modification to Third Embodiment

In the above-described second embodiment, the structure in FIG. 7 can be simplified to the structure in FIG. 10, however, in the third embodiment, as two types of functions are realized, such simplification cannot be attained. However, the structure can be modified to a structure as shown in FIG. 15.

FIG. 15 is a block diagram showing the lossless 4-point orthogonal transform according to a modification to the third embodiment.

In FIG. 15, the multipliers for multiplication by the coefficient {a/(1+a²)} and the multipliers for multiplication by the coefficient {−a/(1+a²)} in FIG. 14 are respectively integrated, thereby the number of multiplications is reduced to six, the same as the number of multiplications by two lossless 2-point orthogonal transforms.

Fourth Embodiment

In this embodiment, image data or the like is encoded by quantizing and Huffman coding the DCT coefficients, obtained by the lossless two-dimensional DCT transform to which the above-described ladder operation is applied.

Generally, an 8×8 block sized two-dimensional DCT in JPEG compression or the like is used, however, in this example, a 4×4 lossless two-dimensional DCT transform is-used. The 4×4 two-dimensional DCT can be expanded to an 8×8 two-dimensional DCT by a well-known technique.

The 4-point DCT transform matrix Mdct is expressed as follows. $\begin{array}{cc}\mathrm{Mdct}=\frac{1}{2}\left[\begin{array}{cccc}1& 1& 1& 1\\ C1& C3& -C3& -C1\\ 1& -1& -1& 1\\ C3& -C1& C1& -C3\end{array}\right]=\left[\begin{array}{cccc}1& 0& 0& 0\\ 0& \alpha & 0& \beta \\ 0& 0& 1& 0\\ 0& -\beta & 0& \alpha \end{array}\right]\frac{1}{2}\left[\begin{array}{cccc}1& 1& 1& 1\\ 1& 1& -1& -1\\ 1& -1& -1& 1\\ 1& -1& 1& -1\end{array}\right]\mathrm{Ci}=\sqrt{2}\cos \frac{i\pi }{8},\alpha =\cos \frac{\pi }{8},\beta =\sin \frac{\pi }{8}& \left[\mathrm{Expression}5\right]\end{array}$

Assuming that the original 4×4 data are represented as d₀₀, d₀₁, d₀₂, . . . , d₃₂ and d₃₃, the 4×4 two-dimensional DCT is expressed as follows. $\begin{array}{cc}{M}_{\mathrm{dct}}\left[\begin{array}{cccc}{d}_{00}& d_{01}& d_{02}& d_{03}\\ d_{10}& d_{11}& d_{12}& d_{13}\\ d_{20}& d_{21}& d_{22}& d_{23}\\ d_{30}& d_{31}& d_{32}& d_{33}\end{array}\right]M_{\mathrm{dct}}^T=\left[\begin{array}{cccc}1& 0& 0& 0\\ 0& \alpha & 0& \beta \\ 0& 0& 1& 0\\ 0& -\beta & 0& \alpha \end{array}\right][\begin{array}{cccc}{x}_{00}& x_{01}& x_{02}& x_{03}\\ x_{10}& x_{11}& x_{12}& x_{13}\\ x_{20}& x_{21}& x_{22}& x_{23}\\ x_{30}& x_{31}& x_{32}& x_{33}\end{array}][\begin{array}{cccc}1& 0& 0& 0\\ 0& \alpha & 0& \beta \\ 0& 0& 1& 0\\ 0& -\beta & 0& \alpha \end{array}]& \left[\mathrm{Expression}6\right]\end{array}$

In the above expression, the components x₀₀x₀₁, x₀₂, . . . , x₃₂ and X₃₃ indicate data obtained by a two-dimensional Hadamard transform on original data.

The horizontal lossless rotational transform and the vertical lossless rotational transform performed on the data resulted from the lossless two-dimensional Hadamard transform equals a lossless two-dimensional DCT transform. The horizontal lossless rotational transform is performed on four pairs of data, x₀₁ and x₀₃, x₁₁ and x₁₃, x₂₁ and x₂₃, and x₃₁ and x₃₃, while the vertical lossless rotational transform is performed on the four pairs of data, x₁₀ and x₃₀, x₁₁ and X₃₁, x₁₂ and x₃₂, and x₁₃ and X₃₃, which are results from horizontal transform.

FIG. 16 is a block diagram showing a 4×4 lossless two-dimensional DCT transform according to the fourth embodiment of the present invention.

In FIG. 16, lossless rotational transforms 1601 and 1602 only in the horizontal direction are performed on two pairs of data, x₀₁ and x₀₃, and x₂₁ and x₂₃, and lossless rotational transforms 1603 and 1604 only in the vertical direction are performed on two pairs of data, x₁₀ and x₃₀, and x₁₂ and x₃₂, and further, a lossless two-dimensional rotational transform 1605 in the horizontal and vertical directions is performed on two pairs of data, x₁₁ and x₁₃, and x₃₁ and X₃₃.

The horizontal or vertical lossless rotational transforms 1601 to 1604 are realized with a conventional three step ladder operation as shown in FIG. 3, and the lossless two-dimensional rotational transform 1605 is realized with a ladder operation of the structure as shown in FIG. 9 or FIG. 10. Regarding the other data x₀₀ and x₀₂, and x₂₀ and x₂₂ not subjected to any rotational transform, the lossless two-dimensional Hadamard transform coefficients are used as lossless two-dimensional DCT transform coefficients.

FIG. 17 is a block diagram showing coding processing capable of lossless coding according to the fourth embodiment.

First, a lossless two-dimensional DCT transform processing 1701 as shown in FIG. 16 is performed, then quantization processing 1702 and Huffman coding processing 1703 are performed, thereby coded data can be obtained. If all the values of quantization steps are “1”, lossless coding can be performed. That is, in a case where a lossless two-dimensional inverse DCT transform, inverse of the lossless two-dimensional DCT transform 1605 in FIG. 16, is performed in decoding processing, the original data can be completely decoded if all the values of quantization steps are “1”.

Accordingly, by setting the quantization steps upon coding processing, the quality of compressed/decompressed image can be continuously controlled by lossless coding to nonlossless (lossy) high-efficiency compression with degradation.

Other Embodiment

Further, the object of the present invention can also be achieved by providing a storage medium holding software program code for performing the aforesaid processes to a system or an apparatus, reading the program code with a computer (e.g., CPU, MPU) of the system or apparatus from the storage medium, then executing the program. In this case, the program code read from the storage medium realizes the functions according to the embodiments, and the storage medium holding the program code constitutes the invention. Further, the storage medium, such as a floppy disk (registered trademark), a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a DVD, a magnetic tape, a non-volatile type memory card, and ROM can be used for providing the program code.

Furthermore, besides aforesaid functions according to the above embodiments are realized by executing the program code which is read by a computer, the present invention includes a case where an OS (operating system) or the like working on the computer performs a part or entire actual processing in accordance with designations of the program code and realizes functions according to the above embodiments.

Furthermore, the present invention also includes a case where, after the program code read from the storage medium is written in a function expansion card which is inserted into the computer or in a memory provided in a function expansion unit which is connected to the computer, CPU or the like contained in the function expansion card or unit performs a part or entire process in accordance with designations of the program code and realizes functions of the above embodiments.

As described above, the present invention provides lossless 4-point orthogonal transform processing and apparatus capable of transformation with a reduced amount of operation and with high transform accuracy. More particularly, a lossless 4-point orthogonal transform can be realized as five multiplications and five rounding processings with an optimized structure.

Further, the number of multiplications can be reduced to ⅓ of a conventional case where twelve multiplications and twelve rounding processings or fifteen multiplications and five rounding processings are required, even with approximately the same transform accuracy (with the same number of rounding processings).

The present invention is not limited to the above embodiments and various changes and modifications can be made within the spirit and scope of the present invention. Therefore, to appraise the public of the scope of the present invention, the following claims are made.

Claims

1. A data transform apparatus for converting four items of input data X0, X1, X2 and X3 into four items of data in a frequency space, wherein the input data X0, X1, X2 and X3 are integers, the apparatus comprising:

a first multiplier configured to multiply the input data X1 by a first coefficient;

a second multiplier configured to multiply the input data X2 by a second coefficient;

a first rounding processor configured to perform rounding processing on an output of said first multiplier;

a second rounding processor configured to perform rounding processing on an output of said second multiplier;

a first calculator configured to add an output of said first rounding processor to the input data X0;

a second calculator configured to add an output of said second rounding processor to the input data X3;

a third rounding processor configured to obtain difference data between an output of said first calculator and an output of said second calculator, to multiply the difference data by a third coefficient and to perform rounding processing on the result of multiplication of the difference data by the third coefficient;

a third calculator configured to add an output of said third rounding processor to the input data X1;

a fourth calculator configured to add an output of said third rounding processor to the input data X2;

a fourth multiplier configured to multiply an output of said third calculator by the second coefficient;

a fifth multiplier configured to multiply an output of said fourth calculator by the first coefficient;

a fourth rounding processor configured to perform rounding processing on an output of said fourth multiplier;

a fifth rounding processor configured to perform rounding processing on an output of said fifth multiplier;

a fifth calculator configured to add an output of said fourth rounding processor to an output of said second calculator; and

a sixth calculator configured to add an output of said fifth rounding processor to an output of said first calculator,

wherein the outputs of said third, fourth, fifth and sixth calculators are output as the four items of data in the frequency space.

2. A data transform method of converting four items of input data X0, X1, X2 and X3 into four items of data in a frequency space, wherein the input data X0, X1, X2 and X3 are integers, the method comprising:

a first multiplying step of multiplying the input data X1 by a first coefficient;

a second multiplying step of multiplying the input data X2 by a second coefficient;

a first rounding step of performing rounding processing on an output obtained in said first multiplying step;

a second rounding step of performing rounding processing on an output obtained in said second multiplying step;

a first calculating step of adding an output obtained in said first rounding step to the input data X0;

a second calculating step of adding an output obtained in said second rounding step to the input data X3;

a third rounding step of obtaining difference data between an output obtained in said first calculating step and an output obtained in said second calculating step, multiplying the difference data by a third coefficient and performing rounding processing on the result of multiplication of the difference data by the third coefficient;

a third calculating step of adding an output obtained in said third rounding step to the input data X1;

a fourth calculating step of adding an output obtained in said third rounding step to the input data X2;

a fourth multiplying step of multiplying an output obtained in said third calculating step by the second coefficient;

a fifth multiplying step of multiplying an output obtained in said fourth calculating step by the first coefficient;

a fourth rounding step of performing rounding processing on an output obtained in said fourth multiplying step;

a fifth rounding step of performing rounding processing on an output obtained in said fifth multiplying step;

a fifth calculating step of adding an output obtained in said fourth rounding step to an output obtained in said second calculating step; and

a sixth calculating step of adding an output obtained in said fifth rounding step to an output obtained in said first calculating step,

wherein the outputs obtained in said third, fourth, fifth and sixth calculating steps are output as the four items of data in the frequency space.

3. A data transform apparatus for converting four items of input data X0, X1, X2 and X3 into four items of data in a frequency space, wherein the input data X0, X1, X2 and X3 are integers, the apparatus comprising:

a first calculator configured to add the input data X3 to the input data X2;

a second calculator configured to subtract the input data X1 from the input data X0;

a rounding processor configured to obtain difference data between an output of said first calculator and an output of said second calculator, to multiply the difference data by a coefficient and to perform rounding processing on the result of multiplication of the difference data by the coefficient;

a third calculator configured to add the input data X1 to an output of said rounding processor;

a fourth calculator configured to add the input data X2 to the output of said rounding processor;

a fifth calculator configured to subtract an output of said fourth calculator from an output of said second calculator; and

a sixth calculator configured to add an output of said first calculator to an output of said third calculator,

wherein the outputs of said third, fourth, fifth and sixth calculators are output as the four items of data in a frequency space.

4. An apparatus according to claim 3, wherein said rounding processor converts the result of multiplication into an integer by counting fractions over ½ as one and disregarding the rest, or counting fractions as one, or omission of fractions.

5. A data transform method of converting four items of input data X0, X1, X2 and X3 into four items of data in a frequency space, wherein the input data X0, X1, X2 and X3 are integers, the method comprising:

a first calculating step of adding the input data X3 to the input data X2;

a second calculating step of subtracting the input data X1 from the input data X0;

a rounding step of obtaining difference data between an output of the first calculating step and an output of the second calculating step, to multiply the difference data by a coefficient and performing rounding processing on the result of multiplication of the difference data by the coefficient;

a third calculating step of adding the input data X1 to an output of the rounding step;

a fourth calculating step of adding the input data X2 to the output of the rounding step;

a fifth calculating step of subtracting an output of the fourth calculating step from an output of the second calculating step; and

a sixth calculating step of adding an output of the first calculating step to an output of the third calculating step;

wherein calculation results in the third, fourth, fifth and sixth calculating steps are output as the four items of data in a frequency space.

6. A data transform apparatus for converting four items of input data X0, X1, X2 and X3 into four items of data in a frequency space, wherein the input data X0, X1, X2 and X3 are integers, the apparatus comprising:

a first calculator configured to add the input data X3 to the input data X2;

a second calculator configured to subtract the input data X1 from the input data X0;

a rounding processor configured to obtain difference data between an output of said first calculator and an output of the second calculator to multiply the difference data by a coefficient and to perform rounding processing on the result of multiplication of the difference data by the coefficient;

a third calculator configured to at least one of add and subtract the input data X1 and an output of the rounding processor;

a fourth calculator configured to at least one of add and subtract the input data X2 and the output of said rounding processor;

a fifth calculator configured to at least one of add and subtract an output of the fourth calculator and an output of the second calculator; and

a sixth calculator configured to at least one of add and subtract an output of the first calculator and an output of the third calculator;

wherein the outputs of the third, fourth, fifth and sixth calculators are output as the four items of data in a frequency space.

7. A data transform method of converting four items of input data X0, X1, X2 and X3 into four items of data in a frequency space, wherein the input data X0, X1, X2 and X3 are integers, the method comprising:

a first calculation step of adding the input data X3 to the input data X2;

a second calculation step of subtracting the input data X1 from the input data X0;

a rounding step of obtaining difference data between an output of the first calculation step and an output of the second calculation step to multiply the difference data by a coefficient and performing rounding processing on the result of multiplication of the difference data by the coefficient;

a third calculation step of calculating the input data X1 and an output of the rounding step;

a fourth calculation step of calculating the input data X2 and the output of the rounding step;

a fifth calculation step of calculating an output of the fourth calculation step and an output of the second calculation step; and

a sixth calculation step of calculating an output of the first calculation step and an output of the third calculation step;

wherein each step of calculating in the third, fourth, fifth and sixth calculation steps includes at least one of adding and subtracting, and

wherein the calculation results in the third, fourth, fifth and sixth calculation steps are output as the four items of data in a frequency space.

8. A data transform apparatus for converting four items of input data X0, X1 X2 and X3 into four items of data in a frequency space, wherein the input data X0, X1, X2 and X3 are integers, the apparatus comprising:

a first calculator configured to add the input data X3 to the input data X2;

a second calculator configured to subtract the input data X1 from the input data X0;

a rounding processor configured to obtain difference data between an output of the first calculator and an output of the second calculator, and output an integer value corresponding to a value that is obtained by multiplying the difference data by 1/2;

a third calculator configured to at least one of add and subtract using the input data X1 and an output of the rounding processor;

a fourth calculator configured to at least one of add and subtract using the input data X2 and the output of the rounding processor;

a fifth calculator configured to at least one of add and subtract using an output of the fourth calculator and an output of the second calculator; and

a sixth calculator configured to at least one of add and subtract using an output of the first calculator and an output of the third calculator;

wherein the outputs of the third, fourth, fifth and sixth calculators are output as the four items of data in a frequency space.

9. A data transform method of converting four items of input data X0, X1, X2 and X3 into four items of data in a frequency space, wherein the input data X0, X1, X2 and X3 are integers, the method comprising:

a first calculating step of adding the input data X3 to the input data X2;

a second calculating step of subtracting the input data X1 from the input data X0;

a rounding step of obtaining difference data between an output of the first calculating step and an output of the second calculating step, and outputting an integer value corresponding to a value that is obtained by multiplying the difference data by 1/2;

a third calculating step of calculating using the input data X1 and an output of the rounding processor;

a fourth calculating step of calculating using the input data X2 and the output of the rounding processor;

a fifth calculating step of calculating using an output of the fourth calculator and an output of the second calculator; and

a sixth calculating step of calculating using an output of the first calculator and an output of the third calculator;

wherein each step of calculating in the third, fourth, fifth and sixth calculation steps includes at least one of adding and subtracting, and

wherein the calculation results in the third, fourth, fifth and sixth calculation steps are output as the four items of data in a frequency space.