Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit

Abstract

Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation. A method of the present invention includes the steps of: forming and patterning a locos reaching an embedded insulating film, a gate oxide film, a well and a polysilicon film serving as a gate electrode; forming a second conductivity type high-density impurity region in an ultra-shallow portion of each of a source region and a drain region, a second conductivity type impurity region having a low density under the second conductivity type high-density impurity region of the ultra-shallow portion, and a second conductivity type impurity region having a high density under the second conductivity type impurity region having a low density and above the embedded insulating film; forming a sidewall around the gate electrode; forming a second conductivity type impurity region in each of the source region and the drain region; forming an interlayer insulating film and forming contact holes in the source region, the drain region and the gate electrode; and forming a wiring on the interlayer insulating film.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of manufacturing a transistor having a structure allowing the reduction of impact ionization in a transistor formed on an SOI wafer. In particular, the present invention relates to a method of manufacturing an SOI transistor having an electric potential of a supporting substrate fixed to a GND level or a low voltage level.

2. Description of the Related Art

FIGS. 4A to 4D show a method of manufacturing a conventional SOI transistor, and FIGS. 5A and 5B are a top view and a cross-sectional view showing a structure of the conventional SO transistor. Herein, the transistor is formed by using a wafer in which a P-type semiconductor film is formed on a P-type supporting substrate through an embedded insulating film.

The conventional SOI transistor is formed in a semiconductor film 1 surrounded by a LOCOS 11 reaching an embedded insulating film as shown in FIG. 5. The transistors are completely isolated from each other by the LOCOS 11. In the case of an N-type transistor, since the semiconductor film 1 is of P-type, a transistor is formed by implanting N-type ions to source/drain regions 14 and 15.

On the other hand, in the case of a P-type transistor, the semiconductor film 1 surrounded by the LOCOS 11 is implanted with N-type ions so as to be imparted with an N-type conductivity. In this state, the source/drain regions 14 and 15 are implanted with P-type ions to form a transistor.

As a manufacturing method, as shown in FIGS. 4A to 4D, first, a nitride film 8 is grown. The formed nitride film 8 is patterned and then is thermally oxidized to form the LOCOS 11. The nitride film 8 is oxidized so that the LOCOS 11 has a thickness reaching the embedded insulating film 2. Next, ion implantation is conducted by using a resist 6 as a mask so as to form a well 7 (FIG. 4A). At this point, an energy of the ion implantation is controlled so as to have a density peak in the semiconductor film.

Next, a thermal treatment is conducted so as to activate and diffuse the implanted ions. After formation of the LOCOS 11, the formation of a gate oxide film 13, the formation of a gate electrode 12, and the ion implantation to the source/drain regions 14 and 15 of the transistor are performed. Then, an interlayer insulating film 18 is formed (FIG. 4C). Furthermore, the interlayer insulating film 18 is patterned and etched to form contacts 19 to the gate electrode 12 and the source/drain regions 14 and 15. Then, a wiring 20 is provided (FIG. 4D).

Since an electric potential of the supporting substrate 3 affects the characteristics of the transistor in the case of the SOI transistor, it is necessary to fix the electric potential of the supporting substrate 3. Therefore, the electric potential of the supporting substrate 3 is obtained from an electrically conductive pedestal adhered through an electrically conductive adhesive when the supporting substrate is to be mounted onto a package. Normally, the supporting substrate 3 is connected to a ground terminal or a power source voltage terminal.

In a conventional method of forming an SOI transistor, since the transistor formed on the semiconductor film and the supporting substrate are not electrically connected to each other because of the presence of the embedded insulating film between the supporting substrate and the semiconductor film, an electric potential of the supporting substrate is in a floating state. In the case of a fully depleted SOI transistor or the like, however, the semiconductor film is entirely depleted in its thickness direction to such a degree that the depletion reaches the embedded insulating film. Therefore, the characteristics of the transistor are greatly affected by the electric potential of the supporting substrate. As a result, a variation in the electric potential of the supporting substrate exhibits similar characteristics as the back gate effect of a bulk transistor.

Thus, it is necessary to fix the electric potential of the supporting substrate. A method of fixing the electric potential of the supporting substrate is normally conducted by adhering the supporting substrate to an electrically conducive pedestal through an electrically conductive adhesive upon mounting on a package. In this state, the electric potential of the pedestal is fixed so as to fix the electric potential of the supporting substrate. The electric potential of the supporting substrate is connected either to a ground terminal or to a power source voltage terminal. In order to fix the electric potential of the supporting substrate, there is also a method of providing a through hole penetrating through the semiconductor film and the embedded insulating film to reach a part of the supporting substrate.

In the case where the electric potential of the supporting substrate is fixed by the above-described connection methods, a parasitic transistor using the supporting substrate as a gate is formed. When the electric potential of the supporting substrate serving as the gate of the parasitic transistor is set to the GND level, a difference in the electric potential between the gate and a drain is increased. As a result, impact ionization occurs in the proximity of the drain of a body.

Unlike the SOI transistor, a parasitic transistor is not formed in a conventional bulk transistor. Therefore, although the impact ionization occurs in a concentrated manner only in the vicinity of the substrate surface in the proximity of a drain in the conventional bulk transistor, the impact ionization occurs even in the vicinity of the embedded insulating film in the proximity of the drain in addition to the vicinity of the substrate surface in the proximity of the drain in the SIO transistor due to formation of a parasitic transistor. The amount of generated impact ions is increased, so that a parasitic bipolar phenomenon, in which a hole of a pair of an electron and a hole flows into a source as a bipolar current, is likely to occur in an N-type transistor. As a result, the operation of the transistor cannot be controlled by a gate voltage.

As a method of restraining the occurrence of the parasitic bipolar phenomenon, there is a method of setting a body electric potential as shown in FIG. 6 so as to compulsively pull holes out from a body. However, since a layout of the transistor used for a bulk transistor is remarkably different from that used for the SOI transistor, a layout modification from a conventional layout becomes a great encumbrance in the case where a circuit design using the SOI device is to be achieved. Furthermore, in principle, the SOI device has a latchup free structure. Therefore, it is not necessary to provide a guard ring for the transistor, and thus is greatly effective to reduce the area. In the method of setting a body electric potential so as to compulsively pull the holes out from the body, however, the effects of the SOI device of reducing the area is disadvantageously halved.

SUMMARY OF THE INVENTION

According to the present invention, there is provided a method of manufacturing a semiconductor integrated circuit, in which a CMOS transistor is formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film, including the steps of: conducting thermal oxidation so as to reach the embedded insulating film to form a LOCOS for element separation between transistors; forming a gate oxide film of a first second conductivity type transistor; forming a first conductivity type impurity region reaching the embedded insulating film on the semiconductor film in a region where the first second conductivity type transistor is to be formed; forming a polysilicon film serving as a gate electrode of the first second conductivity type transistor so as to form a second conductivity type impurity region; forming a second conductivity type impurity region in an ultra-shallow portion of each of a source region and a drain region; forming a second conductivity type impurity region having a low density under the second conductivity type impurity region in the ultra-shallow portion; forming a second conductivity type impurity region having the same density as the second conductivity type impurity region in the ultra-shallow portion under the second conductivity type impurity region having the lower density and above the embedded insulating film; forming an insulating film on the source region, the drain region, and the gate electrode; dry etching the insulating film formed on the source region, the drain region, and the gate electrode so as to form a sidewall around the gate electrode; forming a second conductivity type impurity region in each of the source region and the drain region; forming an interlayer insulating film and forming contact holes in the source region, the drain region, and the gate electrode; and forming a wiring on the interlayer insulating film. As a result, in the transistor formed on the semiconductor film, a depletion layer generated by a difference in electric potential between a drain and a body can be extended toward the body side in the portion of the drain region having a high density whereas the depletion layer can be actively extended toward the drain side in the portion of the drain region having a low density. Therefore, the electric field density in the vicinity of the body surface of the proximity of the drain or the vicinity of the insulating film can be reduced to reduce the generation of impact ions. Furthermore, the SOI transistor conventionally has a disadvantage in that the use of a method of pulling holes generated by impact ionization out from a body terminal halves the area reduction effect. Since the generation of impact ions themselves is reduced without providing a body terminal in the SOI transistor according to the present invention, the SOI transistor according to the present invention is effective to realize the area reduction effect which is the advantage of the SOI device.

Furthermore, a method of manufacturing a semiconductor integrated circuit, in which a CMOS transistor is formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film, includes the steps of: conducting thermal oxidation so as to reach the embedded insulating film to form a LOCOS for element separation between transistors; forming a gate oxide film of a first second conductivity type transistor; forming a first conductivity type impurity region reaching the embedded insulating film on the semiconductor film in a region where the first second conductivity type transistor is to be formed; forming a polysilicon film serving as a gate electrode of the first second conductivity type transistor so as to form a second conductivity type impurity region; forming a second conductivity type impurity region in an ultra-shallow portion of each of a source region and a drain region; forming a second conductivity type impurity region having a low density under the second conductivity type impurity region in the ultra-shallow portion; forming a second conductivity type impurity region having the same density as the second conductivity type impurity region in the ultra-shallow portion under the second conductivity type impurity region having the low density and above the embedded insulating film; providing a mask on the gate electrode and a part of the source region and the drain region so as to form a second conductivity type impurity region in each of the source region and the drain region; forming an interlayer insulating film and forming contact holes in the source region, the drain region, and the gate electrode; insulating film and forming a wiring on the interlayer. In a transistor formed by the above-mentioned method, a width of the portion of the drain region having a low density in a channel length direction is affected by a width of the mask. Therefore, a width in a channel length direction can be more easily controlled as compared with the case where a sidewall is provided around the gate electrode and a portion having a low density is formed in the drain region. As a result, the extension of the depletion layer in the proximity of the drain can be adjusted so as to be uniform. Accordingly, the impact ionization can be reduced in the vicinity of the body surface in the proximity of the drain or in the vicinity of the embedded insulating film.

Furthermore, a method of manufacturing a semiconductor integrated circuit, in which a CMOS transistor is formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film, includes the steps of: conducting thermal oxidation so as to reach the embedded insulating film to form a LOCOS for element separation between transistors; forming a gate oxide film of a first conductivity type transistor; forming a first second conductivity type impurity region reaching the embedded insulating film on the semiconductor film in a region where the first second conductivity type transistor is to be formed; forming a first conductivity type impurity region having a higher density than that of the first second conductivity type impurity region in a portion of the semiconductor film serving as the proximal region to a drain in the first conductivity type impurity region; forming a polysilicon film serving as a gate electrode of the first conductivity type transistor and forming a second conductivity type impurity region; forming a second conductivity type impurity region in each of the source region and the drain region; forming an interlayer insulating film and forming contact holes in the source region, the drain region, and the gate electrode; and forming a wiring on the interlayer insulating film. In a transistor formed by the above-mentioned method, the depletion layer is extended toward the body side in the portion having a low density of the first conductivity type impurity region in the proximity of the drain while being extended toward the drain side in the portion having a high density so as to allow the uniformization of the extension of the depletion layer in the proximity of the drain. As a result, the generation of impact ions can be reduced.

Claims

1. A method of manufacturing a semiconductor integrated circuit, in circuit in which a cmos transistor is formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film, comprising the steps of:

conducting thermal oxidation to form a locos for element separation between transistors in the semiconductor film;

forming a gate oxide film of a first second conductivity type transistor;

forming a first conductivity type impurity region between the gate oxide film and the embedded insulating film in a region where the first second conductivity type transistor is to be formed;

forming a polysilicon film on the gate oxide film and etching the polysilicon film so as to form a gate electrode of the first second conductivity type transistor;

forming a second conductivity type impurity region in an ultra-shallow portion of each of a source region and a drain region;

forming a second conductivity type impurity region having a low density in a middle portion of each of the source region and the drain region;

forming a second conductivity type impurity region having the same density as the second conductivity type impurity region in the ultra-shallow portion in a lower portion of each of the source region and the drain region;

forming an insulating film on the source region, the drain region, and the gate electrode;

dry etching the insulating film formed on the source region, the drain region, and the gate electrode to form a sidewall around the gate electrode; and

performing ion implantation using the sidewall as a mask so as to form a second conductivity type impurity region in each of the source region and the drain region.