A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.
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0. 28. A delay circuit, comprising:
an energy-storage element;
a control circuit operable to generate enable signals;
a current circuit coupled to the energy-storage element and to the control circuit and operable to receive an input signal having first and second levels, the current circuit including current stages that are each operable to source a respective first constant current to the energy-storage element through a respective first current element in response to the input signal having the first level and in response to a respective one of the enable signals and operable to sink a respective second constant current from the energy-storage element through a respective second current element in response to the input signal having the second level and in response to the respective one of the enable signals; and
an output circuit coupled to the energy-storage element and operable to generate a delayed signal.
0. 31. A method, comprising:
delaying a first edge of an input signal by charging an energy-storage element with a first constant current through a first current element in response to the input signal transitioning from a first level to a second level;
delaying a second edge of the input signal by discharging the energy-storage element with a second constant current through a second current element in response to the input signal transitioning from the second level to the first level;
delaying the first edge of the input signal by charging the energy-storage element with a third constant current through a third current element in response to an enable signal and in response to the input signal transitioning from the first level to the second level; and
delaying the second edge of the input signal by discharging the energy-storage element with a fourth constant current through a fourth current element in response to the enable signal and in response to the input signal transitioning from the second level to the first level.
0. 19. A delay circuit, comprising:
an energy-storage element;
a current circuit coupled to the energy-storage element and operable to receive an input signal having first and second levels, to source a first constant current to the energy-storage element through a first current element in response to the input signal having the first level, and to sink a second constant current from the energy-storage element through a second current element in response to the input signal having the second level;
an output circuit coupled to the energy-storage element and operable to generate a delayed signal;
a control circuit coupled to the current circuit and operable to generate an enable signal; and
wherein the current circuit comprises a current stage operable to source a third constant current to the energy-storage element through a third current element in response to the enable signal and in response to the input signal having the first level, and operable to sink a fourth constant current from the energy-storage element through a fourth current element in response to the enable signal and in response to the input signal having the second level.
0. 26. A delay circuit, comprising:
an energy-storage element;
a current circuit coupled to the energy-storage element and operable to receive an input signal having first and second levels, to source a first constant current to the energy-storage element through a first current element in response to the input signal having the first level, and to sink a second constant current from the energy-storage element through a second current element in response to the input signal having the second level;
an output circuit coupled to the energy-storage element and operable to generate a delayed signal;
a control circuit coupled to the current circuit and operable to generate enable signals; and
wherein the current circuit comprises current stages each operable to source a respective third constant current to the energy-storage element through respective third current element in response to a respective one of the enable signals and in response to the input signal having the first level, and operable to sink a respective fourth constant current from the energy-storage element through a respective fourth current element in response to the respective one of the enable signals and in response to the input signal having the second level.
0. 18. A delay circuit comprising:
one or more current-mirror transistors each having an enable input, an input for receiving an input signal, and a constant-current output for providing a constant current responsive to the input signal;
a programmable delay control circuit operable to generate one or more enable signals, each enable signal connected to a respective one of the one or more current-mirror transistors so as to selectively enable the respective current-mirror transistor;
a fixed capacitor having a first plate and a second plate, the first plate of the capacitor connected to the constant-current outputs of the one or more current-mirror transistors, the second plate connected to a voltage reference, each current-mirror transistor having a current path between a respective one of the one or more enable signals and the first plate of said capacitor; and
an output stage having an input connected to the first plate of the capacitor and having an output for providing an output signal responsive to the voltage on the capacitor;
wherein a delay on an active edge of the input signal is adjustable by the programmable delay control circuit selectively enabling the one or more enable signals to change an overall current provided by the one or more current-mirror transistors to the first plate of the capacitor.
13. A delay circuit comprising:
a plurality of current mirror current elements transistors, with each current minor current element transistor having an enable input, having an input for receiving an input signal and having a constant current output for providing a constant current responsive to the input signal;
a programmable delay control circuit having a plurality of enable signals, each enable signal connected to the plurality of current mirror current elements transistors so as to selectively enable a current mirror current element transistor of the plurality of current mirror current elements transistors;
a fixed capacitor having a first plate and a second plate, the first plate of the capacitor connected to the constant current outputs of the plurality of current mirror current elements transistors, the second plate connected to a voltage reference, with each current mirror current element transistor having a current path between a corresponding enable signal of said programmable delay control circuit and the first plate of said capacitor; and
an output stage having an input connected to the first plate of the capacitor and having an output for providing an output responsive to the voltage on the capacitor,
wherein a delay on an active edge of the input signal is adjustable by the programmable delay control circuit selectively enabling the enable signal of one or more of the plurality of current mirror current elements transistors to change an overall current provided by the plurality of current mirror current elements transistors to the first plate of the capacitor.
0. 16. A delay circuit comprising:
a current-mirror current source having an enable input, an input for receiving an input signal, and a constant-current output for providing a constant current responsive to the input signal;
a current-mirror current drain having an enable input, an input for receiving an inverse of the input signal, and a constant drain output for providing a constant current responsive to the inverse of the input signal;
a programmable delay-control circuit operable to generate an enable signal on an enable output that is coupled to the current-mirror current source and the current-mirror current drain such that the programmable delay-control circuit selectively enables the current-mirror current source and the current-mirror current drain;
a fixed capacitor having a first plate and a second plate, the first plate of the capacitor connected to the constant current output of the current-mirror current source and to the constant drain output of the current drain, the second plate connected to a voltage reference, the current-mirror current source having a current path between the enable output and the first plate of said capacitor and the current-mirror current drain having a current path between the enable output and the first plate of said capacitor; and
an output stage having an input connected to the first plate of the capacitor and having an output for providing an output signal responsive to the voltage on the capacitor;
wherein a delay on the rising edge of the input signal is adjustable by the programmable delay-control circuit selectively enabling the enable signal to change an overall current source current provided to the first plate of the capacitor, and
wherein a delay on the falling edge of the input signal is adjustable by the programmable delay-control circuit selectively enabling the enable signal to change an overall current drain current provided to the first plate of the capacitor.
0. 17. A delay circuit comprising:
a first input transistor having a control element for receiving an input signal, and having a current path with a first end connected to a voltage source and a second end;
a second input transistor having a control element for receiving the input signal, and having a current path with a first end and a second end connected to a voltage reference;
a first bias transistor having a current path with a first end connected to the voltage source, having second end, and having a control element, wherein the second end is connected to the control element and to the second end of the current path of the first input transistor;
a resistor having a first end connected to the second end of said first bias transistor and having a second end;
a second bias transistor having a current path from the second end of said resistor to the voltage reference, and having a control element connected to the second end of said resistor and to the first end of the current path of said second input transistor;
a capacitor having a first plate and having a second plate connected to the voltage reference;
an output stage having an input connected to the first plate of said capacitor and having an output;
a programmable delay-control circuit having one or more enable outputs;
one or more constant-current sources each having a source current path between a corresponding enable output of said programmable delay-control circuit and the first plate of said capacitor, and having a bias input connected to the control element of said first bias transistor such that the current flowing in the first bias transistor is proportionately mirrored in the source current path responsive to the corresponding enable output and wherein a constant of proportionality may be chosen independently of the constant of proportionality of any other constant-current source; and
one or more constant-current drains each having a drain current path between a corresponding enable output of said programmable delay-control circuit and the first plate of said capacitor, and having a bias input connected to the control element of said second bias transistor such that the current flowing in the second bias transistor is proportionately mirrored in the drain current path responsive to the corresponding enable output and wherein a constant of proportionality may be chosen independently of the constant of proportionality of any other constant-current drain.
1. A delay circuit comprising:
a plurality of current mirror current sources source transistors, with each current mirror current source transistor having an enable input, having an input for receiving an input signal and having a constant current output for providing a constant current responsive to the input signal;
a plurality of current mirror current drains drain transistors, with each current mirror current drain transistor having an enable input, having an input for receiving an inverse of the input signal, and having a constant drain output for providing a constant current responsive to the inverse of the input signal;
a programmable delay control circuit having a plurality of enable signals, each signal connected to a current mirror current source transistor and current mirror current drain transistor such that the programmable delay control circuit selectively enables a pair of current mirror current source and drain transistors;
a fixed capacitor having a first plate and a second plate, the first plate of the capacitor connected to the constant current outputs of the plurality of current mirror current sources source transistors and to the constant drain outputs of the plurality of current drains drain transistors, the second plate connected to a voltage reference, with each current mirror current source transistor having a current path between a corresponding enable signal of said programmable delay control circuit and the first plate of said capacitor and with, each current mirror current drain transistor having a current path between the corresponding enable signal of said programmable delay control circuit and the first plate of said capacitor; and
an output stage having an input connected to the first plate of the capacitor and having an output for providing an output responsive to the voltage on the capacitor;
wherein a delay on the rising edge of the input signal is adjustable by the programmable delay control circuit selectively enabling the enable signal of one or more of the plurality of current mirror current sources source transistors to change an overall current source current provided by the plurality of current mirror current sources source transistors to the first plate of the capacitor, and
wherein a delay on the falling edge of the input signal is adjustable by the programmable delay control circuit selectively enabling the enable signal of one or more of the plurality of current mirror current drains drain transistors to change an overall current drain current provided by the plurality of current mirror current drains to drain transistor from the first plate of the capacitor.
7. A delay circuit comprising:
a first input transistor having a control element for receiving an input signal, and having a current path with a first end connected to a voltage source and a second end;
a second input transistor having a control element for receiving the input signal, and having a current path with a first end and a second end connected to a voltage reference;
a first bias transistor having a current path with a first end connected to the voltage source, having second end, and having a control element, wherein the second end is connected to the control element and to the second end of the current path of the first input transistor;
a resistor having a first end connected to the second end of said first bias transistor and having a second end;
a second bias transistor having a current path from the second end of said resistor to the voltage reference, and having a control element connected to the second end of said resistor and to the first end of the current path of said second input transistor;
a capacitor having a first plate and having a second plate connected to the voltage reference;
an output stage having an input connected to the first plate of said capacitor and having an output;
a programmable delay control circuit having a plurality of enable outputs;
a plurality of constant-current sources, each constant current source of the plurality of constant-current sources having a current path between a corresponding enable output of said programmable delay control circuit and the first plate of said capacitor, and having a bias input connected to the control element of said first bias transistor such that the current flowing in the first bias transistor is proportionately mirrored in the current path of each constant-current source of the plurality of constant-current sources, responsive to the corresponding enable output and wherein a constant of proportionality may be chosen independently of the constant of proportionality of any other constant-current source; and
a plurality of constant-current drains, each constant current drain of the plurality of constant-current drains having a current path between the corresponding enable output of said programmable delay control circuit and the first plate of said capacitor, and having a bias input connected to the control element of said second bias transistor such that the current flowing in the second bias transistor is proportionately mirrored in the current path of each constant-current drain of the plurality of constant-current drains, responsive to the corresponding enable output and wherein a constant of proportionality may be chosen independently of the constant of proportionality of any other constant-current drain.
2. The delay circuit of
4. The delay circuit of
8. The delay circuit of
9. The delay circuit of
10. The delay circuit of
14. The delay circuit of
15. The delay circuit of
0. 20. The delay circuit of
0. 21. The delay circuit of
0. 22. The delay circuit of
0. 23. The delay circuit of
0. 24. The delay circuit of
0. 25. The delay circuit of
a first inverter having an output node and having an input node coupled to the energy-storage element; and
a second inverter having an output node and having an input node coupled to the output node of the first inverter, the second inverter operable to generate the delayed signal on the output node of the second inverter.
0. 27. The delay circuit of
0. 29. The delay circuit of
a current generator operable to generate a third constant current in response to the input signal having the first level and to generate a fourth constant current in response to the input signal having the second level; and
wherein each current stage is operable to mirror the third constant current in response to the input signal having the first level and to mirror the fourth constant current in response to the input signal having the second level.
0. 30. The delay circuit of
a current generator operable to generate a third constant current; and
wherein each current stage is operable to mirror the third constant current.
0. 32. The method of
0. 33. The method of
generating a delayed signal having a third level when a voltage across the capacitor is less than a predetermined level; and
generating the delayed signal having a fourth level when the voltage across the capacitor is greater than the predetermined level.
0. 34. The method of
generating a delayed signal having the first level when a voltage across the capacitor is less than a predetermined level; and
generating the delayed signal having the second level when the voltage across the capacitor is greater than the predetermined level.
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This is a
Therefore, the rising signal on the input of the delay circuit 20 is passed on to the output of the delay signal 33, but only after the delay created by the time constant of resistor 26 and capacitor 28. However, prior art delay circuit 20 is limited since it often requires relatively large capacitors and/or resistors to obtain long delays. The requirement of a large capacitor or resistor is undesirable since a large capacitor or resistor typically requires large amounts of silicon on an integrated circuit or requires an external connection for an external capacitor. Since the cost of a integrated circuit is directly proportional to the die size, it is desirable to reduce the size of a circuit whenever possible.
Therefore, it is an object of the invention to provide relatively long delays without requiring a large capacitor or a large resistor.
It is further an object of this invention to provide a delay circuit which provides relatively long delays and without requiring large area on an integrated circuit.
It is further an object of this invention to provide a delay circuit which reduces the cost of a delay circuit by reducing the die area necessary to implement the circuit.
These and other objects, features, and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read with the drawings and appended claims.
Referring now to
In operation, an input signal is received at the gates of transistors 48 and 50. If the input signal is at a low voltage, transistor 48 turns on which allows for transistors 46 and 54 to conduct a constant current through transistor 54. The constant current through transistor 54 discharges capacitor 56. Conversely, capacitor 56 is charged when the input signal is at a high voltage since this high input voltage turns transistor 48 off and rums transistor 50 on. Therefore, transistors 46 and 54 are held off while transistors 42 and 52 are turned on. Thus, transistor 52 charges capacitor 56 with the constant current source formed by transistor 42, resistor 44, and transistor 52. The voltage on capacitor 56 buffered to the output by two inverters formed with transistors 58, 60, 62, and 64. In short, an input signal is received by transistors 48 and 50, delayed by the constant current sources or drains in combination with the capacitor, and then buffered by two inverters to the output of the delay circuit 40.
More specifically, transistors 42, 52 and 50 combine with resistor 44 to form a constant current source when the input to the delay circuit is at a high voltage. In this state, transistor 50 draws current through resistor 44 which turns on the current mirror formed by transistors 42 and 52. In the preferred embodiment, Vdd is about 5 volts and R44 is approximately 84 Kohms which defines the current through transistor 42 at about 40 microamps. Transistor 42 has an w/l (area) of 180/9 and transistor 52 has an w/l (area) of 9/9. Thus, the current through transistor 42 is approximately 20 times the current through transistor 52. Thus the current in transistor 52 is approximately 2 microamps. This constant current charges capacitor 56 when the input voltage is high. In general, the time delay can be approximately described as
time delay=(switch voltage/Vr44) (C56) (R44) (current ratio)
where:
switch voltage=the switch voltage for the inverter
Vr44=the voltage drop across R44
C56=the capacitance of capacitor 56
R44=the resistance of resistor 44
current ratio=the current ratio of the applicable current mirror.
In an embodiment, a 10 picofarad capacitor, 84 kilo-ohm resistor, and current ratio of 20 are used which yields a delay of approximately (2.5 v/4 v) (10 pF) (84 k) (20)=10.5 microseconds. (Note that the voltage drop across resistor 44 is reduced from Vdd by the voltage drop across the transistors in the current path, which in this case totals to around 1 volts.)
Conversely, transistors 48, 46, and 54 combine with resistor 44 to form a constant current drain for discharging capacitor 56. When the input of delay circuit 40 is at a low voltage, transistor 50 is off and transistor 48 is on. This allows current to flow through transistor 48 and resistor 44, thus, turning on transistors 46 and 54. With an 84 kohm resistor and 5 volt Vdd, the current through transistor 46 is approximately equal to 40 microamps. Transistor 46 has 20 times the area as transistor 54 so that the current through transistor 54 is about 2 microamps. Therefore, capacitor 56 is discharged at the rate of 2 microamps which creates a delay of about 10.5 microseconds when the input of delay circuit is low.
Transistors 58 and 60 are configured to invert the voltage on the capacitor 56. When the voltage on the gates of transistors 58 and 60 are low, the voltage on output is low and vice versa. Transistors 62 and 64 are also configured as an inverter with the gates configured as the input and the drain of transistor 62 connected to the drain of transistor 64 to form the output of the inverter. The first and second inverter form the output stage of the delay circuit and buffer the voltage on the capacitor to the output of the delay circuit 40. It is understood that numerous circuits can be used for buffering voltages without departing from the spirit and scope of the invention.
The embodiment of the invention offers the advantage providing a delay which over 12 times longer than the delay created by a prior art circuit using the same resistor and capacitor value. Alternatively, this embodiment of the invention creates the equivalent delay, but uses a resistor and/or capacitor which is approximately 12 times smaller than is required by the prior art circuit to achieve the same time delay.
In operation, this embodiment operates in an analogous manner to the previous embodiment, but with the added feature that capacitor 56 can now be charged or discharged by one or more pairs of current mirrors. Transistors 48 and 50 are the input transistors; transistors 42 and 46 are the bias transistors; transistors 82, 86, 90, and 94 are the constant-current source transistors; and transistors 84, 88, 92, and 96 are the constant-current drains, for this embodiment.
More specifically, an input signal enters the circuit through the gate of transistor 48 which turns on transistor 42. Since the gate of transistor 42 is connected to the gates of transistors 82, 86, 90, and 94, transistor 42 provides the bias voltage for transistors 82, 86, 90, and 94 such that the current flow in the respective transistor is proportional (mirrored) to the current through transistor 42. However, transistors 82, 86, 90, and 94 will only be turned on if programmable delay control circuit 80 has enabled one of those transistors by providing the source of the respective transistor with a positive voltage. Therefore, the rate of delay or the rate of charging capacitor 56 is controlled by the programmable delay control circuit 80 and the relative ratios of transistors 42 to transistors 82, 86, 90, and 94. Inversely, when the input signal goes low, transistor 50 turns on bias transistor 46 which thereby provides the bias voltage to turn on transistors 84, 88, 92, and 96 to remove the charge from capacitor 56. Again, transistors 84, 88, 92, and 96 will not drain any current from capacitor 56 unless the transistors have been enabled by programmable delay control circuit 80 providing a sufficiently low voltage to the respective transistors drain. In this disclosure, it is assumed that the enable signals from the programmable delay control signal are digital in nature with sufficient current drive to drive the MOSFET transistors.
It will be clear to persons skilled in the art that additional transistor pairs can be added to the circuit to increase the range of programmability. Four transistor pairs are disclosed for illustrative purposes and could easily be modified to less pairs or more pairs by persons skilled in the art. Additionally, persons skilled in the art can vary the ratio of the current mirrors to further increase the range of programmability. By adjusting the current mirror ratios and/or increasing the number of transistor pairs persons skilled in the art can easily design a programmable delay which meets a given design criteria for versatility as well as flexibility.
Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.
Paparo, Mario, Phillips, William A., Capocelli, Piero
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