A digital communication system for transmitting and receiving digital Visual Interface (DVI) communication data signals and display data channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.
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1. A digital communication system for processing digital Visual Interface (DVI) transition minimized differential signal (TMDS) communication data signals and display data channel (DDC) communication signals over a transmission line, the system comprising:
an open-loop equalizer circuit operable to receive DVI TMDS communication signals transmitted over the transmission line and output equalized DVI TMDS communication data signals, the open-loop equalizer circuit comprising:
a differential pair defining first and second inputs;
a reactive load coupled to the differential pair; and
a pair of input follower circuits configured to receive the DVI TMDS communication data signals and feedback signals from the reactive load and generate corresponding first and second input signals for the first and second inputs of the differential pair;
the open-loop equalizer circuit providing either proportional or disproportional equalization to the TMDS communication data signal, wherein proportional equalization provides a frequency dependent gain that is at or about the inverse of a frequency dependent attenuation caused by the transmission line, the DVI communication data signal being proportionately equalized, and if the open-loop equalizer wherein disproportionate equalization provides a frequency dependent gain that is greater than the inverse of a frequency dependent attenuation caused by the transmission line, then the DVI communication data signal being disproportionately equalized .
27. A system for transmitting and receiving digital Visual Interface (DVI) transition minimized differential signal (TMDS) communication data signals and display data channel (DDC) communication signals over a transmission line, comprising:
means for providing feedback loops at the inputs to a differential pair, the feedback loops independent of output signals generated by the differential pair;
means for providing as input to the feedback loop the DVI TMDS communication data signals at the received end of the transmission line;
means for generating first and second differential input signals from the DVI TMDS communication data signals and the feedback loop;
means for monitoring the DDC communication signal at the receive end of the transmission line; and
means for injecting a boost current at the receive end of the transmission line during a portion of the positive transition in the DDC communication signal
wherein the means for monitoring the DDC communication signal at the receive end of the transmission line comprises:
means for generating an injection activation signal when the DDC communication signal exceeds a first reference value; and
means for eliminating the injection activation signal when the DDC communication signal exceeds a second reference value;
wherein the presence of the injection activation signal causes injection of the boost current at the receive end of the transmission line,
the open-loop equalizer circuit providing either proportional or disproportional equalization to the TMDS communication data signal, wherein proportional equalization provides a frequency dependent gain that is at or about the inverse of a frequency dependent attenuation caused by the transmission line, the DVI communication data signal being proportionally equalized, and if the open-loop equalizer wherein disproportionate equalization provides a frequency dependent gain that is greater than the inverse of a frequency dependent attenuation caused by the transmission line, then the DVI communication data signal being proportionately equalized .
22. A method for transmitting and receiving digital Visual Interface (DVI) transition minimized differential signal (TMDS) communication data signals and display data channel (DDC) communication signals over a transmission line, comprising:
providing feedback loops at the inputs to a differential pair, the feedback loops independent of output signals generated by the differential pair;
providing as input to the feedback ioop loop the DVI TMDS communication data signals at the received end of the transmission line;
generating first and second differential input signals from the DVI TMDS communication data signals and the feedback loop;
monitoring the DDC communication signal at the receive end of the transmission line; and
injecting a boost current at the receive end of the transmission line during a portion of the positive transition in the DDC communication signal;
wherein the step of monitoring the DDC communication signal at a receive end of the transmission line comprises:
generating an injection activation signal when the DDC communication signal exceeds a first reference value; and
eliminating the injection activation signal when the DDC communication signal exceeds a second reference value;
wherein the presence of the injection activation signal causes injection of the boost current at the receive end of the transmission line
wherein the step of monitoring the DDC communication signal at a receive end of the transmission line further comprising:
generating a first output by a first comparator having a first input and a second input, the second input coupled to the receive end of the transmission line, the first output being high when the second input exceeds the first input and the first output being low when the second input does not exceed the first input;
generating a second output by a second comparator having a third input and a fourth input, the fourth input coupled to the receive end of the transmission line, the second output being high when the fourth input exceeds the third input, and the second output being low when the fourth input does not exceed the third input;
receiving the first output by a latch as a reset input and receiving the second output by the latch as a set input;
receiving the output of the latch by a nand gate and receiving the inverted second output by the nand gate; and
injecting the boost current when the output of the nand gate is high.
2. The system of
a compensation circuit operable to compensate for intermediate circuitry attenuation of the DVI TMDS communication data signals.
3. The system of
a DDC extension circuit operable to inject a boost current at a receive end of the transmission line during a positive transition in the DDC communication signals.
4. The system of
5. The system of
a first operational amplifier configured to receive as input a first DVI TMDS communication data signal and to receive a first feedback signal from the reactive load and generate the first input signal applied to the first input; and
a second operational amplifier configured to receive as input the second DVI TMDS communication data signal and to receive a second feedback signal from the reactive load and generate the second input signal applied to the second input.
6. The system of
7. The system of
the source of the first field effect transistor is connected to an input node of the first operational amplifier to provide the first feedback signal; and
the source of the second field effect transistor is connected to an input node of the second operational amplifier to provide the second feedback signal.
8. The system of
a voltage clamp connected to the receive end of the transmission line and operable to clamp a reflection signal caused by the DDC communication signals received at the receive end of the transmission line; and
a current booster circuit connected to the receive end of the transmission line and operable to provide the boost current at the receive end of the transmission line when the DDC communication signal exceeds a first reference value and to eliminate the boost current from the receive end of the transmission line when the DDC communication signal exceeds a second reference value.
9. The system of
a first comparator configured to receive as input the DDC communication signal and a first reference potential and to output a switch signal; and
a first switch configured to receive the switch signal and to couple the receive end of the transmission line to a second reference potential when the DDC communication signal is less than the first reference potential.
10. The system of
11. The system of
a boost current circuit connected to the receive end of the transmission line, the boost current circuit operable to provide the boost current during an activated state; and
a detector circuit operable to monitor the DDC communication signal on the receive end of the transmission line and to activate the boost current circuit when the DDC communication signal exceeds the first reference value and to deactivate the boost current circuit when the DDC communication signal exceeds the second reference value.
12. The system of
a level detector operable to output a first data signal when the DDC communication signal is less than the first reference value, and to output a second data signal when the DDC communication signal is greater than the first reference value and less than the second reference value, and to output a third data signal when the DDC communication signal is greater than the second reference value; and
a latch circuit operable to receive the output data signals of the level detector and in response to selectively activate and deactivate the boost current circuit.
13. The system of
the first reference value is a first reference voltage greater than a logic 0 voltage signal; and
the second reference value is a second reference voltage greater than the first reference voltage.
14. The system of
a first comparator configured to receive as input the DDC communication signal and the first reference value and output a first comparator signal;
a second comparator configured to receive as input the DDC communication signal and the second reference value and output a second comparator signal; and
a latch configured to receive as input the first and second comparator signals and output a latch signal.
15. The system of
a current booster circuit connected to the receive end of the transmission line, the current booster circuit operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and to eliminate the boost current at the end of the positive transition in the DDC communication signal and prevent injection of the boost current at the receive end of the transmission line during a negative transition in the DDC communication signal.
16. The system of
17. The system of
18. The system of
21. The system of
23. The method of
24. The method of
25. The method of
26. The method of
28. The system of
29. The system of
30. The system of
31. The system of
0. 32. The system of
0. 33. The method of
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This application claims the benefit of and priority to U.S. Provisional Application Ser. No. 60/364,430, entitled “Equalization In Digital Video Interfaces,” and filed on Mar. 15, 2002, and U.S. Provisional Application Ser. No. 60/441,010, entitled “Systems And Methods For Data Communication And Transmission,” and filed on Jan. 17, 2003. The entire disclosures of Application Ser. Nos. 60/364,430 and 60/441,010 are incorporated herein by reference.
This application is related to co-pending U.S. patent application Ser. No. 10/389,119, filed on Mar. 14, 2003, entitled “Input Follower System And Method,” and is also related to co-pending U.S. patent application Ser. No. 10/388,916, filed on Mar. 14, 2003, entitled “Digital Communication Extender System And Method.”
1. Technical Field
This application generally relates to digital communication systems and methods, and particularly relates to Digital Visual Interface (DVI) communications.
2. Description of the Related Art
The Digital Visual Interface (DVI) Specification, Revision 1.0, dated Apr. 2, 1999, and published by Digital Display Working Group, provides for a high speed digital connection for visual data types that is display technology independent. A DVI interface is typically focused on providing a connection between a computer and the computer display device. A DVI system uses a transition minimized differential signal (TMDS) for a base electrical connection, in which 8 bits of data are encoded into a 10-bit, transition minimized DC balanced character.
DVI accommodates several different serial signal rates, the highest of which is a signal rate of 1650 Mb/s. This signal rate corresponds to a data rate of 825 MHz. The DVI data may be transmitted over a video bus in a computer device, such as in laptop computer, or may be transmitted over a cable that is external to a computer device, such as a video cable used to connect a remote monitor to a computer. Typically, cables over short distances and low frequencies can be considered ideal channels having minimal loss and a bandwidth much greater than the input signal. The ideal cable with infinite bandwidth produces no dispersion of the input data.
Real cables, however, have a loss characteristic that is a function of the data frequency and the cable length. Thus, the longer the cable length, the greater the loss characteristic. In practical applications, the attenuation of the high frequency components of the DVI data signal at 1650 MHz typically limits DVI cable lengths to about 5 meters.
Equalizers may be used to restore the integrity of the DVI data so that the cable length between the source and the destination does not reduce the system performance. Many equalizers comprise a differential pair having an automatic gain control (AGC) feedback block between the output of the differential pair and the inputs of the differential pair. Additionally, many of these differential pairs utilize inductors, which demand a relatively large amount of semiconductor area and are susceptible to noise.
The DVI specification also supports the VESA Display Data Channel (DDC), which enables the computer display, the computer, and a graphics adapter to communicate and automatically configure the system to support different features available in the computer display. The DDC link is typically a lower bandwidth signal, e.g., 400 kHz, and thus may be transmitted over a longer cable length than the DVI data signal. However, the DDC cable is typically not terminated in an impedance match, and thus reflections in the DDC cable may degrade the DDC signal as the DDC cable length increases. Additionally, the bandwidth of the DDC signal is limited by the amount of pull-up current injected into the DDC cable during a transition of the data signal from a low voltage level to a high voltage level.
A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Chemical (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.
The graphics controller 10 is operable to encode 8 bits of video data into a 10-bit TMDS DC balanced character on each data channel. The graphics controller 10 may be one of many DVI-compliant graphics controllers. The transmitter 14 and receiver 16 are operable to transmit and receive the 10-bit TMDS DC balanced characters over a transmission line. The display controller 18 is operable to decode the 10-bit character back into the 8 bits of video data for each data channel. The display controller 18 may be one of many DVI-compliant display controllers.
The DDC controller 12 is operable to transmit DDC data and receive DDC data over the transmission line. Unlike the DVI data, the DDC data is not DC balanced. The DDC data link typically comprises a clock channel and a digital data channel.
Usually, the physical path between the transmitter 14 and the receiver 16 is less than five meters. For example, the transmitter 14 and receiver 16 may be enclosed in a single enclosure, such as when connected by a short video bus within a laptop computer. Alternatively, the receiver 16 may be connected to the transmitter 14 by a relatively short cable. Because the cable impedance, signal attenuation, and reflection are proportional to the cable length, signal degradation does not typically affect data integrity for relatively short cables.
Table 1 below provides the maximum allowable attenuation for a transmitted DVI signal.
TABLE 1
Maximum Attenuation
Data Frequency
Maximum
(MHz)
Attenuation (dB)
1
0.14
10
0.45
50
1.0
100
1.5
200
2.1
400
3.0
700
4.3
1000
5.4
From Table 1, it can be seen that the maximum attenuation for a data frequency rate of 825 MHz is approximately 5 dB, which corresponds to a maximum cable length of about 5 meter. Accordingly, to transmit DVI data over a cable in excess of 5 meters, equalization of the DVI data is usually required. Additionally, as the cable length increases, signals on the DDC data channel begin to degrade due to reflections and decreased rise times. Thus, a DDC extender circuit may be used in conjunction with an equalizer.
Each of the equalizers 22, 24, 26 and 28 comprise an open-loop architecture in which the output signal of the equalizer is not fed back to adjust the input signal to the equalizer, and are configured to receive a DC balanced differential signal as the input signal.
The DDC channel comprises a DDC data channel and DDC clock channel, and the DDC extender circuit 30 comprises circuitry serving both of these channels. Because the DDC channel is typically a lower frequency channel as compared to the DVI data channels, the DDC channel does not incorporate an equalizer circuit. The DDC extender circuit 30 is located on a receiving end of a transmission line and provides voltage clamping during data transition from a positive voltage data signal to a zero voltage data signal, and also provides a boost current during data transition from a zero voltage data signal to a positive voltage data signal.
The digital communication system 20 may be located on the side of the transmitter 14, or on the side of the receiver 16, or on both the side of the transmitter 14 and the receiver 16. Typically, the DDC extender circuit 30 is located on the receive end of the transmission line. Additionally, the DDC extender circuit 30 may be located on both ends of the transmission line if the transmission line is used for bi-directional communication. The DDC extender circuit 30 need not be located on both ends of the transmission line for bi-directional communication, however. For example, the DDC extender circuit 30 may be located at the receiver 16, and the transmitter 14 may have different reflection and impedance mitigation circuitry, or none at all.
The equalizers 22, 24, 26 and 28 may be located on the receive end of the transmission line before the receiver 16, or on the transmitting side of the transmission line after the transmitter 14, or on both the receive end of the transmission line before the receiver 16 and on the transmitting side of the transmission line after the transmitter 14.
In one variation of this embodiment, the equalizer 40 is configured to compensate for the length of the transmission line 32. For example, the equalizer 40 may be implemented in a remote monitor having a 20-meter video cable 32. The equalizer 40 may then be adjusted to compensate for frequency dependent attenuation corresponding to a 20-meter long video cable.
In another variation of this embodiment, the equalizer 40 may be adjusted to compensate for a maximum length D of the video cable 32. For example, the equalizer 40 may be implemented in a remote monitor having a receptacle for receiving a video cable, and the equalizer 40 is adjusted to compensate for a video cable 32 length of 30 meters. The remote monitor may thus be “rated” for a maximum video cable length of 30 meters.
In yet another variation of this embodiment, the equalizer 40 may be configured to compensate for frequency dependent attenuation caused by electrostatic discharge (ESD) protection circuitry located at the input of the receiver 16. An exemplary ESD protection circuit comprises a pair of diodes connected to a ground potential and a high potential, with an output pin or receptacle corresponding to a conductor of the transmission line 32 interposed between the diodes. The diodes tend to act as low pass filters due to their inherent capacitances, and thus attenuate the high frequency components of a data signal. Accordingly, the equalizer 40 is configured to compensate for the diode capacitances such that the output signal of the equalizer 40 includes restored high frequency components of the original data signal.
In another variation of this embodiment, the equalizer 42 may be adjusted to compensate for a maximum length D of the video cable 32. For example, the equalizer 42 may be implemented in a computer device for generating video signals and having a receptacle for receiving a video cable, and the equalizer 42 is adjusted to compensate for a video cable 32 length of 30 meters. The computer device may thus be “rated” for a maximum video cable length of 30 meters.
In yet another variation of this embodiment, the equalizer 42 may be configured to compensate for frequency dependent attenuation caused by ESD protection circuitry located at the output of the transmitter 14. The equalizer 42 is configured to compensate for the ESD protection circuitry such that the output signal of the equalizer 42 includes restored high frequency components of the original data signal.
The ESD compensation circuit 60 is configured to compensate for the high frequency attenuation of the data signal in a manner as described above with reference to
The output driver 80 is configured to receive the equalized data signal from the open-loop equalizer 70 and provide the equalized data signal to processing circuitry, such as the display controller 18 of FIG. 1. The output driver 80 may be a buffer circuit, or may be a converter circuit operable to convert the output differential voltage of the open-loop equalizer stage 70 into a differential current signal. The converter circuit may be utilized as an output driver 80 in the case of a DVI repeater stage, for example.
While the embodiments of
A DC balanced data signal is a data signal comprising DC characters having an average DC value. For example, a data signal may be divided into 6-bit characters, and the DC value of each 6-bit character may be 2 volts (for a voltage signal) or 50 milliamps (for a current signal). In the case of DVI graphics data, a graphics controller, such as the graphics controller 10 of
The open-loop equalizer core gain stages 74 are configured to receive the output of the equalizer input stage 70 and equalize the voltage data signal by conditioning the signal through one or more of the equalizer circuits described with reference to
Axis A depicts an ideal data pulse with zero rise and fall time and a period of t0, and axis B depicts a corresponding differential data signal. The differential signal of axis B is symmetric about the B axis that represents a DC value, and is transmitted over a transmission line. The differential signal of axis C depicts a received pulse corresponding to the differential signal of axis B received at the received end of the transmission line.
The received pulse of axis C illustrates the frequency dependent attenuation of the high frequency components of the differential signal of axis B as the signal propagates over the transmission line. As can be seen by inspection of the data signal of axis C, the transmission line low pass filters the differential signal of axis B. Because the data signal is DC balanced, however, crossing points over the DC value define the time period t0, which corresponds to the time period of the ideal pulse of axis A.
The open-loop equalizer stage 70 is configured to receive the differential signal of axis C as input, compensate for the frequency dependent attenuation of the transmission line, and output an equalized differential data signal. Depending on the length of the transmission line and the gain of the open-loop equalizer stage 70, the received differential signal may undergo proportional equalization or disproportionate equalization. Axes D and E illustrate equalized data pulses for the case of proportional equalization and disproportionate equalization, respectively. The data signal of axis D has been proportionally equalized, i.e., the open-loop equalizer stage 70 has provided a frequency dependent gain that is nearly the inverse of the frequency dependent attenuation caused by the transmission line.
The data signal of axis E, however, has undergone disproportionate equalization, i.e., the open-loop equalizer stage 70 has provided a frequency dependent gain that results in gain that is greater than the inverse of the frequency dependent attenuation caused by the transmission line. Accordingly, the differential data signal of axis E has a noticeable ripple due to the disproportionate magnitude of the high frequency components. Because the data signal is DC balanced, however, the crossing points over the DC value define the time period t0, which corresponds to the time period of the ideal pulse of axis A. The open-loop equalizer core gain stage 74, therefore, does not require an AGC circuit to adjust the output level of the equalized data signal. Additionally, a monitor or similar receiving device utilizing an open-loop equalizer stage 70 configured to provide equalization up to a maximum cable length, e.g., 30 meters, may thus be used with cables having cable lengths that are less than the maximum cable length.
As previously described, the open-loop equalizer core stage 74 provides a frequency dependent gain that is the inverse of the transmission loss due to the frequency dependent attenuation caused by the transmission line. The two primary loss mechanisms in a transmission line are skin effect and dielectric losses. These loss mechanisms may be expressed as the following transfer function:
G(f)=e−L(k
where f is the frequency, j=√{square root over (−1)}, L is the length of the transmission line, and ks and kd are the skin and the dielectric loss constants, respectively. These losses introduce both magnitude and, to a lesser extent, group delay distortions in data signals transmitted over the transmission line 22. Generally, the skin effect dominates the low frequency losses, while the dielectric loss dominates the high frequency losses.
An inverse function of G to compensate for these losses can be realized by expressing 1/G(f) as:
where α is a factor proportional to the length of the cable. This inverse gain function is implemented in the open-loop equalizer core stages 74. A typical implementation may use several open-loop equalizer core stages 74 in cascade to obtain the required gain for a certain maximum loss, e.g., the maximum attenuation depending on the length of the transmission line. Ideally, the equalized signal at the output of the open-loop equalizer core stages 74 will match the originally transmitted data signal exactly if the transfer function H(f) can be replicated exactly.
where Ro is the open-loop output impedance, α is the open-loop gain and β is the feedback gain. In one embodiment, with β=1, the open-loop gain may be approximated by
where Adc is the dc gain of the amplifier 92, ωp1 is the dominant pole frequency of the amplifier 92 in radians per second, ω is the frequency in radians per second and j−√{square root over (=1)}. Substituting equation (4) into equation (3) with β=1, and assuming Adc and ω are much smaller than dominant pole ωp1, equation (3) simplifies to:
The closed-loop output impedance of the feedback loop may be approximated by a resistance, represented by the first term
in series with an inductance, represented by the second term
While the transistors 102 and 104 are shown as field effect transistors, other types of transistors may also be used. A reactive load 120 comprising capacitors 122, 126, and 128 and resistors 124, 130 and 132 is coupled to the differential pair 100 at the sources of the transistors 102 and 104. Typically, without the input follower stages 90, inductors are usually added at the drains of the transistors 102 and 104 to adjust the response of the differential pair to match transfer function H(f). Such inductors are typically large in size, requiring additional cost for silicon area. Also, the large spiral structure of a physical inductor may introduce unwanted noise to the circuit. However, as illustrated by the derivation of equation (5), the input follower stages 90 eliminate the need for such an inductor.
The input follower stages 90 are realized by a pair of amplifiers 140 and 142 configured to receive a differential voltage data signal corresponding to the DVI communication data signals as input and compare data signals received to a feedback signal from the reactive load 120. Based on this comparison, the amplifiers 140 and 142 generate corresponding first and second input signals for the transistors 102 and 104, respectively. In one embodiment, feedback is a unity game feedback signal, i.e., β=1. The open-loop equalizer core stages 74 of
In another embodiment, β may be a value other than unity, or may be a frequency dependent variable. For example, β may be an adaptive feedback variable.
In operation, the transistors 102 and 104 are operated in the linear region. The capacitors 122, 136 and 128 are selected so that the high frequency gain of the differential pair 100 will approximate the transfer function H(f). The amplifiers 140 and 142 generate corresponding first and second input signals for the transistors 102 and 104. In response to the first and second input signals, the transistors adjust the corresponding drain currents ID102 and ID104, respectively, which in turn induce a voltage drop across resistors 106 and 108 to generate the equalized differential output signals V− and V+. Accordingly, the differential pair 100 operates in an open-loop configuration with respect to the output data signals V− and V+ generated at the resistors 106 and 108.
Thus, by selecting the particular values of the resistors and capacitors of the reactive load 120, and by cascading multiple open-loop equalizer core stages 74 such that the output of one of the open-loop equalizer core stages 74 is connected to the input of another of the open-loop equalizer core stages 74, the inverse gain function 1/G(f) of equation (2) may be readily realized.
The compensation is realized by configuring the reactive load 120 of the open-loop equalizer core gain stage 74 of
The open-loop equalizer core gain stages 74 may also be used to compensate for any intermediate circuitry between the transmitter 14 and the receiver 16; the ESD protection circuit 150 is but one example of such intermediate circuitry. Other intermediate circuitry may also include signal repeaters, transmission line taps, and the like.
Accordingly, a DDC extender circuit 30 may be used to extend the DDC channel over a transmission line.
On the receive end of the transmission line 200, a rail clamp circuit comprises a pair of diodes 206 and 208 connected to a ground potential and VDD, respectively, with an output pin or receptacle corresponding to a conductor of the transmission line 200 interposed between the diodes.
The DDC extender circuit 30 comprises a voltage clamp circuit 300 and a current booster circuit 400. The voltage clamp circuit 300 is operable to provide voltage clamping during data transition from a positive voltage data signal to a zero voltage data signal, and the current booster circuit 400 is operable to provide a boost current during data transition from a zero voltage data signal to a positive voltage data signal.
Typically, the length of the transmission cable 200 causes inductive clamping at a receive end and also results in bandwidth limitations. A DDC link typically utilizes an Inter-1C (I2C) bus as the transmission line 200, which is a bi-directional two-wire serial bus that provides a communication link between integrated circuits (ICs). With respect to inductive clamping, the falling edge of the transmission line 200 voltage data signal is relatively short, because the element employed for asserting a logic 0 on the transmission line 200 is typically the transistor 202 having a low ‘on’ resistance.
As shown in
If the receive end voltage falls below the logic 0 level, then the receive end will ring with multiple reflections. For example, without a voltage clamp, the voltage at x=X would ring to a value of −VDD, and Ix would drop to zero as the energy in the line is forced to switch from inductive energy back to capacitive energy. This behavior is analogous to an LC ‘tank’ circuit. The voltage and current in the transmission line 200 would continue to ring at diminishing amplitudes as the energy in the line is dissipated by resistive losses of the transmission line 200.
A clamping device, such as the diode 208, may be used to limit the negative voltage swing to a value of −VCLAMP, which attenuates the magnitude of the ringing at the receive end of the transmission line 200. Nevertheless, the ringing around the logic 0 level may compromise the noise margin of the DDC link. Furthermore, if the ringing persists through the period of the data signal, then the ringing may impair the detection of a transition from a logic 0 level to logic 1 level. Additionally, the conduction of current in the clamping device, such as diode 208, may cause significant injection of minority carriers into the substrate of the receiver chip, which in turn may cause a malfunction of the receiver operation. Typical negative clamp currents are 50 milliamps for 5V signal, and 30 milliamps for 3.3V signal.
When the receive end voltage is clamped to the logic 0 level, however, the resulting reflections are of negligible amplitude. Accordingly, a voltage clamp circuit 300 may be connected in parallel with the clamping diode 208 at the receive end of the transmission line 200. While the diode 208 is designed to conduct when a received falling edge of the data signal falls below the logic 0 level, the voltage clamp circuit 300 may absorb the negative pulse and prevent conduction of the diode 208.
While the voltage clamp circuit 300 facilitates a data transition from a logic 1 to a logic 0 value on the transmission line 200, it does not primarily facilitate the rise time of a data transition from a logic 0 to a logic 1 value. The I2C architecture utilized by the DDC link uses either a passive pull-up resistor or fixed current source to assert a logic ‘1’ on the transmission line 200, and thus only a finite amount of current is available to charge the transmission line 200 capacitance. Accordingly, there is an implicit bandwidth limitation imposed by the transmission line 200 capacitance that is proportional to a product of the pull-up resistance R and the line capacitance C.
A pull-up resistor in the range of 1.5K-2.2K may be used, which will typically limit a DDC link operating at a clock speed of 100 kHz to about 10 meters. A transmission line 200 in excess of this length will a cause decrease in the rise time for the rising edge of the voltage data signal. Increasing the length of the transmission line 200 increases the line capacitance, which will eventually result in the slew-rate of the 0-1 data transition to be too small to allow the rising edge of the data signal to cross a logic level detection threshold in the receiver within a specified time period.
The RC ramp results in a trapezoidal appearance of the attenuated logic ‘1’ pulses following an initial voltage step during a positive transition from logic 0 to logic 1. The initial voltage step preceding the RC ramp is caused by the inductive energy trapped in the line by the action of the voltage clamp 300 being released as the transistor 202 turns off to provide a logic 1 value to the transmission line 200. Because the voltage clamp 300 stores inductive energy in the transmission line 200, the voltage clamp 300 provides a secondary utility of slightly increasing the rise time of a positive data transition. However, the inductive energy stored in the transmission line is typically not enough to fully pull the data signal to a logic 1 level, as shown in FIG. 20.
While the value of the resistor 204 may be reduced to increase the pull-up current at the transmitting end of the transmission line 200, the additional pull-up current would require an increased power rating of the transistor 202 (or other suitable driving device). Accordingly, a current booster circuit 400 is connected to the receive end of the transmission line 200.
By providing additional pull-up current only for the duration of a positive data transition, open-collector signal devices on the transmission line 200 do not conduct at the same time as the boost current is being injected into the line, and thus the current booster circuit 400 is transparent to existing transmitting devices.
Furthermore, the current booster circuit 400 also provides a boost current at the receive end of the transmission line 200 when a digital signal is transmitted from the receive end. Accordingly, the current booster circuit 400 not only facilitates reception of digital signals at the receive end of the transmission line 200, it also facilitates the transmission of digital signals from the receive end of the transmission line 200. Thus, if the transmission line 200 is a bi-directional communication line, the current booster circuit 400 will provide a boost current at the receive end of the transmission line 200 when the voltage at the receive end transitions from a low state to a high state due to either reception of a digital signal from a transmitting device at the other end of the transmission line 200, or to the generation of a digital signal from a transmitting device connected to the receive end of the transmission line 200. Accordingly, bandwidth for both the transmission and reception of data may be increased.
During operation of the voltage clamp 300, when the voltage VL at the receive end of the transmission line 200 is greater than the ground potential, the comparator 302 outputs a low signal, which turns off the transistor 304, thus isolating the receive end of the transmission line 200 from ground. Conversely, when the voltage VL at the receive end of the transmission line 200 is less than or equal to the ground potential, the comparator 302 outputs a high signal, which turns on the transistor 304, thus coupling the receive end of the transmission line 200 to ground. Accordingly, the receive end of the transmission line 200 remains clamped to the ground potential until a positive voltage signal is applied to the transmission line 200.
While a field effect transistor 304 has been illustrated, other switching devices, such as a bipolar junction transistor, may also be used. Additionally, a positive offset voltage may also be interposed between the noninverting terminal of the comparator 302 and ground so that the receive end of the transmission line 200 is clamped to ground when the receive end of the transmission line 200 is within a noise margin, e.g., 1 mV, 10 mV, or some other noise margin.
The current booster circuit 400 comprises a first comparator 412 and a second comparator 414. The first comparator 412 has an inverting input terminal set at a potential of VTH1, which is equal to VDD−VL. The noninverting input of the first comparator 412 is connected to the receive end of the transmission line 200. Accordingly, when the receive end voltage VL of the transmission line 200 is greater than VTH1, the output of the comparator 412 is high, and when the receive end voltage VL of the transmission line 200 is less than VTH1, the output of the comparator 412 is low.
Likewise, the second comparator 414 has a noninverting input terminal set at a potential of VTH0, which is equal to a ground potential offset by a positive voltage V0. The inverting input of the second comparator 414 is connected to the receive end of the transmission line 200. Accordingly, when the receive end voltage of the transmission line 200 is greater than VTH0, the output of the comparator 414 is low, and when the receive end voltage VL of the transmission line 200 is less than VTH0, the output of the comparator 414 is high.
Thus, the first and second reference values VTH0 and VTH1 define a low and high noise margin, respectively. Comparator 412 outputs a high signal when the receive end voltage VL of the transmission line 200 is above the high noise margin VTH1, and comparator 414 outputs a high signal when the receive end voltage VL of the transmission line 200 is below the low noise margin VTH0.
The output of the comparator 412 is connected as a reset input to a latch 420, and the output of the comparator 414 is connected as a set input to the latch 420, and also to an inverter 422. The output of the latch 420 and the output of the inverter 422 are provided as input to a NAND gate 424, which in turn is used to drive transistor 426. When the transistor 426 is on, a boost current IB is injected into the receive end of the transmission line 200. A resistor 428 coupled between the drain and the receive end of the transmission line 200 governs the magnitude of the boost current IB. Alternatively, the resistor 428 could be replaced by a current mirror implementation of the transistor 426 drive circuitry. Other current source circuitry may also be used.
Operation of the current booster circuit 400 is described with reference to Table 2 below, which provides a state table corresponding to the receive end voltage V1 of the transmission line 200 during a 1-0-1 logic transition.
TABLE 2
State Transition Table
VL
S
R
Q
S′
(QS)′
IB
1
0
1
0
1
1
OFF
VTH1
0
0
0
1
1
OFF
VTH0
1
0
1
0
1
OFF
0
1
0
1
0
1
OFF
VTH0
0
0
1
1
0
ON
VTH1
0
1
0
1
1
OFF
1
0
1
0
1
1
OFF
When the receive end line voltage VL is high, e.g. at a logic 1 level or VDD, the output of the NAND gate 424 is high, and thus the transistor 426 is off, which prevents injection of the boost current ID. As the receive end line voltage VL falls below the upper threshold VTH1, the output of the comparator 412 goes low, and the reset input to the latch 420 likewise goes low. Consequently, there is no state change in the latch 420 output, and the transistor 426 remains off.
As the receive end line voltage V1 falls below the lower threshold value VTH0, the latch 420 is set. However, the output of the inverter 422 switches from a high state to a low state, and thus the output of the NAND gate 424 remains high. Accordingly, the transistor 426 remains off.
No state change is induced until the receive end line voltage VL exceeds the lower threshold VTH0 during a positive voltage transition. At this time, the output of the comparator 414 goes low, which hi turn causes the output of the inverter 422 to go high. Accordingly, both inputs to the NAND gate 424 are high, which in turn causes the output of the NAND gate 424 to go low. The transistor 426 is thereby turned on, and the boost current IB is injected into the receive end of the transmission line 200.
The transistor 426 remains hi an on state until the receive end line voltage VL exceeds the upper threshold voltage VTH1, which causes the latch 420 to reset. Accordingly, the output of the latch 420 goes low, which in turn causes the output of the NAND gate 424 to go high, shutting off the transistor 426 and eliminating the boost current IB. The current booster circuit 400 is then in the original state, and the process of injecting a boost current IB is then repeated during the next 1-0-1 logic transition.
The threshold VTH0 is typically set high enough so that noise immunity is not compromised, but not so high that significant duty-cycle distortion results from the delay of the turn-on boost current IB. The low impedance of the signal device driving the ‘0’ state on the transmission line 200, together with the inductive energy stored by the voltage clamp circuit 300 may be considered when selecting VTH0.
As illustrated in Table 2, the comparators 412 and 414 form a level detector operable to output a plurality of 2-bit data signals corresponding to the voltage level V1 at the receive end of the transmission line 200 with respect to the lower threshold value VTH0 and the upper threshold voltage VTH1. The data signals are input into the Set and Reset inputs of the latch 420 and the inverter 422 to generate the NAND gate 424 input signals, the output of which drives the transistor 426.
The systems and methods herein have been described with reference to an illustrative DVI-compliant system, but are not limited to the illustrative DVI-compliant system. For example, the equalizer core gain stages 74 may be used to equalize any DC-balanced differential signal. The DC-balanced signal may be a differential voltage signal, or may be a differential current signal that is converted to a corresponding differential voltage signal. Likewise, the voltage clamp circuit 300 and the current booster circuit 400 of the DDC extender circuit 30 may be used for receiving any type of digital data signals or digital clock signals, and are thus not limited to the illustrative DDC channel implementation.
Additionally, the equalizer core gain stages 74 and the DDC extender circuit 30 may be implemented on a single receiver chip, or, alternatively, may be implemented on different receiver chips. For example, if the equalizer core gain stages 74 are configured to operate at the same power supply voltage as that of the DDC extender circuit 30, both circuits may be provided on a single receiver chip. Alternatively, if the DDC extender circuit 30 and the equalizer core gain stages 74 are configured to operate at different power supply voltages, e.g., 5 V and 3.5 V, respectively, then the DDC extender circuit 30 and the equalizer core gain stages 74 may be located on different receiver chips.
This written description uses illustrative embodiments to disclose the invention, including the best mode, and also to enable a person of ordinary skill in the art to make and use the invention. Other embodiments are within the scope of the claims if they have elements that do not differ from the literal language of the claims, or have equivalent elements.
Hudson, John, Zamir, Eliyahu D., Webster, Stephen P., Biman, Aapoolcoyuz, Biman, Birubi Ram
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