Method for compensating non-linearity of a sigma-delta analog-to-digital converter

Abstract

The invention concerns a method for compensating the non-linearity of a sigma-delta analog-to-digital converter (A2) with quantization at n levels comprising a digital-to-analog converter (24). The method comprises a calibrating step which consists in transforming the multibit sigma-delta analog-to-digital converter (A2) into a sigma-delta analog-to-digital converter with quantization at three levels, then at two levels. The correction values of each level to be corrected are accurately measured. The method also comprises a normal functioning phase which consists, when the sigma-delta an analog-to-digital converter (A2) is operating with quantization at n levels, in producing an instantaneous correction of errors of the analog-to-digital converter (24) using said correction values.

Description

The division is simple to effect in the digital processor module 33 because a power of two has been chosen for the value of N₀. The value C is then saved in the memory 32, which has three compartments in which it saves the number N₁, the sum S1 and the value C.

Once these two calibration phases have been completed, the phase of normal operation of the sigma-delta analog-to-digital converter with three quantizing levels begins. The switch 17 is switched to the input 16, the switch 26 is switched to the corrector module 27, and the quantizer 22 operates with three quantizing levels −1, 0 and +1. The analog signal to be digitized is fed to the input 16 and leaves the quantizer 22 in the form of a digital signal 23 which is modified by the corrector module 27 and then digitally filtered by the module 28. The corrector module 27 executes an algorithm that can be summarized as in the table below:

input output


1     1
0     0 + C
−1    −1

Thus if the digital value 0 is present at the output of the quantizer 22, it is replaced by its correction value C at the output of the corrector module 27.

FIG. 5 shows the three-level quantizer 22 made up of two comparators 37 and 38 and a digital processor module 39. The comparator 37 has two inputs, a first of which receives the signal 21 from the noise-shaping filter 20 and the second of which is maintained at a fixed voltage V equal to a positive quantizing threshold voltage. The comparator 38 also has two inputs, the first of which also receives the signal 21, and the second input of the comparator 32 is maintained at a voltage equal to −V. The output of the comparator 37 and that of the comparator 38 enter the digital processor module 39 generating the digital output signal 23. If the value of the input signal 21 is greater than V, the digital signal 23 takes the value +1. If the value of the input signal 21 is less than −V, the signal 23 takes the value −1. If the value of the input signal 21 is between −V and V, the signal 23 is equivalent to 0. The digital processor module 39 is governed by the following algorithm, in which S₃₇ is the output of the comparator 37, and S₃₈ is the output of the comparator 38:

$+1=S_{37}$ $0=\stackrel{\_}{S_{37}}-S_{38}$ $-1=\stackrel{\_}{S_{38}}$

To convert the three-level quantizer 22 into a two-level quantizer the values V and −V at the second inputs of the comparators 37 and 38 are replaced by a null value and the algorithm of the digital processor module 39 is modified so that, when the value of the input signal 21 is positive, the signal 23 is equivalent to +1 and, when the value of the input signal 21 is negative, the signal 23 is equivalent to −1. To this end, the algorithm of the digital processor module 39 is as follows:

$+1=S_{37}$ $-1=\stackrel{\_}{S_{37}}$

In fact, only the comparator 37 is used, the comparator 38 being rendered “invisible”.

The non-linearity of the sigma-delta analog-to-digital converter described above can be compensated by carrying out a calibration phase without modifying the structure of the sigma-delta analog-to-digital converter.

FIGS. 6a and 6b show the conversion of the five-level quantizer into a three-level quantizer. The E axis represents the input signal 7 and the S axis represents the output signal 9. FIG. 6a shows the transfer function of a five-level quantizer (−1; −0.5; 0; 0.5; 1). For example, any input signal having a value between two positive values v1 and v2 delimiting a range of values on the E axis is converted into a digital signal of value equal to 0.5 on the S axis. To correct the zero level by converting the quantizer to three levels, the intermediate levels (−0.5 and 0.5) are eliminated, as shown in FIG. 5b. The remaining three levels are therefore (−1; 0; 1).

For example, in a simulation for a signal to be converted of maximum amplitude and no correction in accordance with the invention, a sigma-delta analog-to-digital converter with three quantizing levels sampled at a frequency of 2 048 kHz had a signal/noise ratio of 46 dB. The results obtained after applying the first calibration phase with N₀=262 144 were as follows: N₁=372 522 and S1=−6 408.

Executing the second calibration phase yielded a sum S2=−3 116 and a 0 point correction value C such that:
C=(S2−S1)/N₀=3 292/262 144

A signal/noise ratio of 105 dB was then obtained in normal operation for a signal to be converted of maximum amplitude and with correction in accordance with the invention.

The method described above performs a calibration phase using a three-level quantizer and then a two-level quantizer but retains the general structure of the sigma-delta analog-to-digital converter. The calibration phase is effected simply by controlling the various switches.

Claims

1. A method of compensating the non-linearity of a sigma-delta analog-to-digital converter with a quantizer having n quantizing levels, and including a digital-to-analog converter in a feedback loop, comprising:

a normal operation phase in which a plurality of digital values corresponding to a plurality of quantizing levels are modified by correction values C_i, where i is a positive integer from 1 to N−2; and

a calibration phase in which the correction values C_i are calculated from values of the output of the quantizer of the sigma-delta analog-to-digital converter processed digitally with the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter and after converting the multibit sigma-delta analog-to-digital converter into a sigma-delta analog-to-digital converter with three quantizing levels;

wherein during the calibration phase the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with three quantizing levels X_m, X_M, and X_i, where i is from 1 to N−2;

wherein, during a period P1_i of the calibration phase, a predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the values from the output of the quantizer of the sigma-delta analog-to-digital converter are processed digitally;

wherein the calibration phase is executed N−2 times, retaining the levels X_m and X_M, and taking successively for the level X_i, the N−2 levels other than the levels X_m and X_M; and

wherein the correction values C_i of the N−2 levels other than X_m and X_M are calculated using a sum of the processed values, the N−2 correction values C_i being adapted to modify the N−2 levels other than X_m and X_M during the normal operation phase.

2. The method of claim 1, further comprising during the calibration phase and before calculating the correction values C_i, at least one step F during which the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with two quantizing levels X_m and X_M, during a period P2, wherein the predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the successive values of the output of the sigma-delta analog-to-digital converter are processed digitally.

3. The method of claim 2, wherein the sigma-delta analog-to-digital converter with n quantizing levels is converted into a sigma-delta analog-to-digital converter with a number of quantizing levels less than n by modifying quantizing threshold values and by digital processing using internal comparators.

4. The method of claim 3, wherein during the normal operation phase, the correction value C_i is added to each level X_i present at the output of the quantizer.

5. The method of claim 4, wherein step F of the calibration phase is executed N−2 times, each time taking a period P2_i equal to each period P1_i, and a sum S2_i is calculated of all the values leaving the sigma-delta analog-to-digital converter during each execution, after which a correction value C_i corresponding to the value X_i is calculated from the equation: C_i=(S2_i−S1_i)/n_i.

6. The method of claim 5, wherein the period P1_i, for each level X_i, is equal to the period needed to count the number n_i of values equal to X_i at the output of the sigma-delta analog-to-digital converter until the number n_i is equal to a given number n₀.

7. The method of claim 3, wherein the predetermined value is equal to zero, and wherein during the calibration phase and during the period P_i for each level X_i, the number n_i of values equal to X_i and the total number NT_i of all the output values are counted at the output of the sigma-delta analog-to-digital converter and a sum S1_i of the NT_i values is calculated.

8. The method of claim 7, wherein the period P1_i, for each level X_i, is equal to the period needed to count the number n_i of values equal to X_i at the output of the sigma-delta analog-to-digital converter until the number n_i is equal to a given number n₀.

9. The method of claim 3, wherein the levels X_m and X_M are respectively the minimum value and the maximum value of the n quantizing levels.

10. The method of claim 2, wherein the levels X_m and X_M are respectively the minimum value and the maximum value of the n quantizing levels.

11. The method of claim 2, wherein during the normal operation phase, the correction value C_i is added to each level X_i present at the output of the quantizer.

12. The method of claim 2, wherein the predetermined value is equal to zero, and wherein during the calibration phase and during the period P1_i for each level X_i, the number n_i of values equal to X_i and the total number NT_i of all the output values are counted at the output of the sigma-delta analog-to-digital converter and a sum S1_i of the NT_i values is calculated.

13. The method of claim 1, wherein the levels X_m and X_M are respectively the minimum value and the maximum value of the n quantizing levels.

14. The method of claim 1, wherein during the normal operation phase, the correction value C_i is added to each level X_i present at the output of the quantizer.

15. The method of claim 1, wherein the predetermined value is equal to zero, and wherein during the calibration phase and during the period P1_i for each level X_i, the number n_i of values equal to X_i and the total number NT_i of all the output values are counted at the output of the sigma-delta analog-to-digital converter and a sum S1_i of the NT_i values is calculated.

16. A system for compensating the non-linearity of a sigma-delta analog-to-digital converter having a quantizer with n quantizing levels, comprising:

a digital-to-analog converter in a feedback loop and a digital filter, wherein the digital-to-analog converter comprises means for calculating correction values C_i, where i is a positive integer from 1 to N−2, during a calibration phase, and from values of the output of the quantizer of the sigma-delta analog-to-digital converter processed digitally with the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter and by converting the multibit sigma-delta analog-to-digital converter into a sigma-delta analog-to-digital converter with three quantizing levels, and means for modifying a plurality of digital values corresponding to a plurality of quantizing levels by applying the correction values C_i during a normal operation phase;

wherein the calculating and modifying means comprise:

counter means for counting the values leaving the quantizer of the sigma-delta analog-to-digital converter;

at least one accumulator for summing the values leaving the quantizer of the sigma-delta analog-to-digital converter;

storage means for memorizing numbers delivered by the counter means and the accumulator;

processor means for performing calculations on the memorized numbers and generating control signals in the system for controlling the various phases;

a correction module between the quantizer and the digital filter, communicating with the processor means; and

comparators and a digital processor module internal to the n-level quantizer and capable of converting the quantizer into a quantizer with fewer than n quantizing levels.

17. A method of compensating the non-linearity of a sigma-delta analog-to-digital converter with a quantizer having n quantizing levels and including a digital-to-analog converter in a feedback loop, comprising:

a normal operation phase in which a plurality of digital values corresponding to a plurality of quantizing levels are modified by correction values C_i, where i is a positive integer from 1 to N−2; and

a calibration phase in which the correction values C_i are calculated from values of the output of the quantizer of the sigma-delta analog-to-digital converter processed digitally with the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter and after converting the multibit sigma-delta analog-to-digital converter into a sigma-delta analog-to-digital converter with three quantizing levels;

wherein during the calibration phase the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with three quantizing levels X_m, X_M, and X_i, where i is from 1 to N−2;

wherein, during a period P1_i of the calibration phase, a predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the values from the output of the quantizer of the sigma-delta analog-to-digital converter are processed digitally;

wherein the calibration phase is executed N−2 times, retaining the levels X_m and X_M, and taking successively for the level X_i, the N−2 levels other than the levels X_m and X_M; and

wherein the correction values C_i of the N−2 levels other than X_m and X_M are calculated using the processed values, the N−2 correction values C_i being adapted to modify the N−2 levels other than X_m and X_M during the normal operation phase.

18. The method of claim 17, further comprising during the calibration phase and before calculating the correction values C_i, at least one step F during which the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with two quantizing levels X_m and X_M, during a period P2, wherein the predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the successive values of the output of the sigma-delta analog-to-digital converter are processed digitally.

19. A method of compensating the non-linearity of a sigma-delta analog-to-digital converter, the method comprising:

during a normal operation phase:

operating a quantizer with n quantizing levels;

generating a digital output value for each of the n quantizing levels, wherein the n quantizing levels include a minimum quantizing level X_m, a maximum quantizing level X_M, and N−2 remaining quantizing levels X_i, where i is from 1 to N−2; and

modifying each of the digital output values that correspond to the N−2 remaining quantizing levels using a respective one of N−2 correction values generated during a first portion of a calibration phase that is executed N−2 times;

during the first portion of the calibration phase:

digitally processing the digital output values with a digital-to-analog converter retained in a feedback loop of the sigma-delta analog-to-digital converter;

calculating each respective N−2 correction value using a first sum of the digitally processed digital output values;

operating the quantizer with three quantizing levels comprising X_m, X_M, and one of the remaining quantizing levels X_i;

providing a predetermined input value to the sigma-delta analog-to-digital converter;

retaining the levels X_m and X_M, and taking successively for the level X_i, the N−2 levels other than the levels X_m and X_M; and

calculating the correction values of the N−2 levels other than X_m and X_M using a sum of the processed values.

20. The method of claim 19, further comprising during a second portion of the calibration phase, operating the quantizer with two quantizing levels: X_m and X_M.

21. The method of claim 20, wherein the quantizer is operated with a number of quantizing levels less than n by modifying internal quantizing threshold values and by performing said digital processing using comparator circuits internal to the quantizer.

22. The method of claim 20, further comprising executing the calibration phase N−2 times, wherein a time to execute the second portion of the calibration phase is substantially equal to a time to execute the first portion of the calibration phase, and wherein during the second portion, a second sum (S2_i) is calculated from all of the digital output values during each execution, wherein each correction value (C_i) corresponding to each remaining quantizing level X_i is calculated by C_i=(S2_i−S1_i)/n_i, where n_i comprises a number of occurrences in which the digital output values are equal to X_i.

23. The method of claim 22, wherein the time to execute the second portion of the calibration phase is substantially equal to the period used to count the number n_i until the number n_i is equal to the number n₀.

24. The method of claim 19, wherein during the normal operation phase, said modifying includes adding the respective correction value to each digital output value corresponding to each remaining quantizing level X_i.

25. The method of claim 19, wherein the predetermined input value is equal to zero, and wherein during the first portion of the calibration phase, for each remaining quantizing level X_i, the number n_i of values equal to X_i and the total number NT_i of all the digital output values are counted and a first sum S1_i of the NT_i values is calculated.

26. The method of claim 19, wherein during each of the N−2 executions of the first portion of the calibration phase, each of the respective correction values for the N−2 remaining quantizing levels is calculated using a first sum (S1_i) of a number n₀ of the digital output values, where n₀ comprises a number of occurrences in a given period of time in which the digital output values are equal to X_i.

27. A system for compensating the non-linearity of a sigma-delta analog-to-digital converter, the system comprising:

a quantizer configured to operate in a normal operation phase and a first portion of a calibration phase, wherein the quantizer is configured to operate during the normal operation phase with a plurality of quantizing levels (n) including a minimum quantizing level X_m, a maximum quantizing level X_M, and N−2 remaining quantizing levels X_i, where i is from 1 to N−2, wherein the quantizer is configured to output a plurality of digital output values, each digital output value corresponding to one of the plurality of quantizing levels, and wherein the quantizer is further configured to operate with three quantizing levels comprising X_m, X_M, and one of the remaining quantizing levels X_i during the first portion of the calibration phase that is executed N−2 times;

a digital-to-analog converter coupled in a feedback loop to the quantizer during the first portion of the calibration phase, wherein the digital-to-analog converter is configured to digitally process the plurality of digital output values, wherein during the first portion of the calibration phase, the plurality of digital output values of the quantizer are based on a predetermined input value;

a control device coupled to the quantizer and configured, during the first portion of the calibration phase, to retain the levels X_m and X_M and take successively for the level X_i the N−2 levels other than the levels X_m and X_M, and to calculate a respective correction value from the plurality of digital output values for each of the digital output values that corresponds to the N−2 remaining quantizing levels; and

a corrector module coupled to the quantizer, wherein the corrector module is configured, during the normal operation phase, to modify each of the digital output values that corresponds to the N−2 remaining quantizing levels using a respective one of the N−2 correction values.

28. The system of claim 27, wherein the control device comprises:

a counter circuit configured to count ones of the plurality of output digital values of the quantizer;

an accumulator configured to sum the plurality of output digital values of the quantizer;

storage device coupled to the counter circuit and to the accumulator, wherein the storage device is configured to store values provided by the counter circuit and the accumulator; and

a processor module coupled to the storage device and configured to perform calculations on the values stored within the storage device and to generate control signals for controlling the quantizer.

29. The system of claim 28, wherein the quantizer includes a comparator circuit coupled to a processor module, wherein the quantizer is configured to operate with fewer than n quantizing levels depending upon the control signals.

30. The system of claim 27, wherein during each of the N−2 executions of the first portion of the calibration phase, the control device is further configured to calculate each of the respective correction values for the N−2 remaining quantizing levels using a first sum (S1_i) of a number n₀ of the digital output values, where n₀ comprises a number of occurrences in a given period of time in which the digital output values are equal to X_i.

31. The method of claim 30, wherein the quantizer is further configured to operate with two quantizing levels: X_m and X_M during a second portion of the calibration phase.

32. A system for compensating the non-linearity of a sigma-delta analog-to-digital converter, the system comprising:

a quantizer configured to operate in a normal operation phase and a first portion of a calibration phase, wherein the quantizer is configured to operate during the normal operation phase with a plurality of quantizing levels (n) and to generate a digital output value for each of the n quantizing levels, wherein the n quantizing levels include a minimum quantizing level X_m, a maximum quantizing level X_M, and N−2 remaining quantizing levels X_i, where i is from 1 to N−2, and wherein the quantizer is further configured to operate with three quantizing levels comprising X_m, X_M, and one of the remaining quantizing levels X_i during the first portion of the calibration phase that is executed N−2 times;

a digital-to-analog converter coupled in a feedback loop to the quantizer during the first portion of the calibration phase;

means for retaining the levels X_m and X_M and for taking successively for the level X_i the N−2 levels;

means for calculating, during the first portion of the calibration phase, a respective correction value from the plurality of digital output values for each of the digital output values that corresponds to the N−2 remaining quantizing levels, wherein the digital output values are processed digitally by the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter;

wherein the means for calculating comprises:

counter means for counting specific ones of the digital output values of the quantizer;

at least one accumulator for summing the digital output values of the quantizer;

storage means for storing numbers delivered by the counting means and the at least one accumulator; and

processor means for performing calculations on the stored numbers and generating control signals for controlling the quantizer; and

means for modifying, during the normal operation phase, each of the digital output values that correspond to the N−2 remaining quantizing levels using a respective one of the N−2 correction values;

wherein the means for modifying comprises:

a correction module coupled between the quantizer and a digital filter, wherein the correction module communicates with the processor means; and

within the quantizer, a comparator circuit and a digital processor module are configured to operate the quantizer with fewer than n quantizing levels.

33. The system of claim 32, wherein during each of the N−2 executions of the first portion of the calibration phase, the means for calculating is further configured to calculate each of the respective correction values for the N−2 remaining quantizing levels using a first sum (S1_i) of a number n₀ of the digital output values, where n₀ comprises a number of occurrences in a given period of time in which the digital output values are equal to X_i.

34. The method of claim 33, wherein during a second portion of the calibration phase, the quantizer is further configured to operate with two quantizing levels: X_m and X_M.

35. The method of claim 32, wherein the digital output values are based on a predetermined value provided to an input of the sigma-delta analog-to-digital converter.