A method of manufacturing a flash memory device includes the steps of forming trenches by forming a tunnel oxide layer and a conductive layer for a floating gate over a semiconductor substrate, and then etching a portion of the conductive layer, the tunnel oxide layer and the semiconductor substrate to form the trenches, filling the trenches with an insulating layer to form isolation layers projecting above the floating gate, forming spacers on sidewalls of the isolation layers projecting above the floating gate, etching the conductive layer using the spacers as a mask, thereby forming a U-shaped conductive layer, removing the spacers, etching the top surface of the isolation layers, thereby controlling an Effective field height (EFH) of the isolation layer, and forming a dielectric layer and a conductive layer for a control gate on the resulting surface.
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1. A method of manufacturing a flash memory device, comprising the steps of:
forming a tunnel oxide layer and a conductive layer for a floating gate over a semiconductor substrate;
etching a portion of the conductive layer, the tunnel oxide layer, and the semiconductor substrate to form trenches;
forming isolation layers at the trenches, wherein the isolation layers project above floating gate;
forming spacers on exposed sidewalls of the isolation layers projecting above the conductive layer;
etching the conductive layer using the spacers as an etch mask, thereby forming a U-shaped conductive layer;
removing the spacers;
etching the top surface of the isolation layers, thereby controlling an Effective field height (EFH) of the isolation layer; and
forming a dielectric layer and a second conductive layer for a control gate on the resulting surface.
2. The method of
3. The method of
sequentially forming the tunnel oxide layer, the conductive layer for the floating gate, a buffer oxide layer, and a nitride layer over the semiconductor substrate;
performing an etch process employing a mask to pattern the nitride layer; thereby forming a hard mask;
performing an etch process using the hard mask, sequentially etching the buffer oxide layer, the conductive layer for the floating gate, and the tunnel oxide layer, thereby exposing a specific region of the semiconductor substrate; and
etching the specific region of the exposed semiconductor substrate to form the trenches.
4. The method of
5. The method of
forming an oxide layer above the resulting structure of the semiconductor substrate including the isolation layers and the conductive layer for the floating gate; and
performing an etch process to form the spacers such that the oxide layer remains only on sidewalls of the isolation layers projecting above the floating gate.
7. The method of
8. The method of
9. The method of
10. The method of
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Priority to Korean patent application number 2006-59522, filed on Jun. 29, 2006, the disclosure of which is incorporated by reference in its entirety, is claimed.
The invention relates, in general, to flash memory devices and, more particularly, to a method of manufacturing a flash memory device in which interference between floating gates can be reduced and the coupling ratio can be increased.
In a NAND flash memory device, a plurality of cells for storing data are connected in series to form one string. A drain select transistor and a source select transistor are formed between the cell string and the drain and between the cell string and the source, respectively. In the cell of the NAND flash memory device, a gate in which a tunnel oxide layer, a floating gate, a dielectric layer and a control gate are stacked is formed at a specific region on a semiconductor substrate. Junctions are formed at both sides of the gate.
In the NAND flash memory device constructed above, the state of the cell is influenced by the operation of neighboring cells. It is therefore very important to maintain a constant cell state. A phenomenon in which the state of the cell is changed due to the operation of neighboring cells (i.e., a program operation) is called an interference phenomenon. In other words, if a second cell adjacent to a first cell to be read is programmed, a threshold voltage higher than that of the first cell is read due to a capacitance phenomenon caused by a change in the charges of the floating gate of the second cell. Therefore, although the charge of the floating gate of the first cell is not changed, the actual state of the first cell appears distorted due to a change in the state of neighboring cells. The state of the cell is changed due to the interference phenomenon, resulting in a degraded yield of the failure ratio. Accordingly, it is desirable to maintain a constant cell state by minimizing the interference phenomenon.
Meanwhile, in a manufacturing process of a general NAND flash memory device, part of the isolation layer and the floating gate is formed using a Self-Aligned Shallow Trench Isolation (SA-STI) process. The process is described below with reference to
A tunnel oxide layer 11 and a first polysilicon layer 12 are formed over a semiconductor substrate 10. Specific regions of the first polysilicon layer 12 and the tunnel oxide layer 11 are etched. The semiconductor substrate 10 is etched to a specific depth, forming trenches. The trenches are filled with an insulating layer. A polish process is then performed to form isolation layers 13 in the trenches. Thereafter, a second polysilicon layer 14 is formed and then etched to form floating gates 12 and 14. A dielectric layer 15 and a third polysilicon layer 16 for a control gate are formed over the floating gates 12 and 14.
If the flash memory device is fabricated by the SA-STI process described above, interference may occur between the first polysilicon layers 12 because the isolation layers 13 are formed between neighboring first polysilicon layers 12 serving as the floating gates.
Referring to
Accordingly, the invention addresses the above problems and provides a manufacturing method for a flash memory device. In the method, a floating gate is partially etched to have a U-shaped form so that the interfacial area between the floating gate and a control gate can be increased and the coupling ratio can be increased accordingly. A portion of an isolation layer between the floating gates is etched so that the control gate to be formed subsequently is disposed between the floating gates, thereby reducing the interference phenomenon.
According to an aspect of the invention, a method of manufacturing a flash memory device includes the steps of forming trenches by forming a tunnel oxide layer and a conductive layer for a floating gate over a semiconductor substrate, and then etching a portion of the conductive layer, the tunnel oxide layer and the semiconductor substrate to form the trenches, filling the trenches with an insulating layer to form isolation layers projecting above the floating gate, forming spacers sidewalls of the isolation layers projecting above the floating gate, etching the conductive layer using the spacers as a mask, thereby forming a U-shaped conductive layer, removing the spacers, etching the top surface of the isolation layers, thereby controlling an Effective Field Height (EFH) of the isolation layer, and forming a dielectric layer and a second conductive layer for a control gate on the resulting surface.
Now, a specific embodiment of the disclosure is described with reference to the accompanying drawings.
Referring to
An insulating layer, such as a high density plasma (HDP) oxide layer, is formed on the entire surface so that the trenches 105 are filled. A polishing process, such as a chemical-mechanical polish (CMP), is performed on the insulating layer such that the nitride layer 104 is exposed, thereby forming isolation layers 106 within the trenches 105.
Referring to
Referring to
Referring to
Referring to
Referring to
A conductive layer 110 for a control gate is formed on the dielectric layer 109. The conductive layer 110 is preferably formed of a polysilicon layer. The dielectric layer 109 and the conductive layer 110 completely fill the U-shaped gap between opposing sidewalls of the etched conductive layers 102, so that the opposing sidewalls of the conductive layers 102 are isolated from each other. Accordingly, the interference phenomenon between adjacent conductive layers 102 can be improved.
As described above, according to the invention, a floating gate is partially etched to have a U shape. Accordingly, the interfacial area of the floating gate and a control gate can be increased, the coupling ratio can be increased, and the program speed of a cell can be improved.
Furthermore, an isolation layer between the floating gates is partially etched so that a control gate to be formed subsequently is disposed between the floating gates. It is therefore possible to reduce the interference phenomenon.
Although the foregoing description has been made with reference to the illustrated embodiments, it is to be understood that changes and modifications may be made by the ordinarily skilled in the art without departing from the spirit and scope of the disclosure and appended claims.
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