A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M1, M2, M3 connected in parallel for respectively driving a capacitive load CL with a selected different voltage level V1, V2 or V3. transistors M1, M2, M3 are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V1, V2 or V3 to charge the load CL. The largest voltage transistor M3 has its body connected to its source. The lower voltage transistors M1, M2 have their bodies respectively connected to switches S1, S2, which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V3 when the transistors are placed in the OFF condition.
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7. A voltage level shifting circuit, comprising:
a plurality of mos transistors connected in parallel to act as main switches for selective connection of respective different reference voltage sources to a capacitive load;
auxiliary switches provided to connect the a body of each main switch, either to its source when that main switch is in the an ON condition or to the a highest one of the reference voltage sources when that main switch is in the an OFF condition.
1. A method for preventing a source-to-body forward bias condition of a pn junction between a drain and a body in a mos transistor, the method comprising:
applying voltage to the a gate of the mos transistor to place the mos transistor in an ON condition enabling flow of current between the a source and the drain of the mos transistor, the source being at a source voltage;
connecting the body of the mos transistor to the transistor source for the ON condition;
applying voltage to the gate of the mos transistor to place the mos transistor in an OFF condition preventing flow of current between the source and the drain of the mos transistor; and
switching the body of the mos transistor from the source to a voltage different than the transistor source voltage for the OFF condition; the different voltage acting to place the pn junction between the drain and the body of the mos transistor in a source-to-body reverse bias condition, when keeping the transistor body connected to the transistor source would place the pn junction between the drain and the body of the mos transistor in a source-to-body forward bias condition, wherein the voltage applied to the gate to place the mos transistor in the OFF condition is the same as the different voltage.
6. A method for preventing a forward source-to-body bias condition in a pn junction between a drain and a body of a mos transistor in a circuit having a plurality of mos transistors connected in parallel and respectively to a corresponding plurality of reference voltages, the method comprising:
applying voltage to the a gate of a first one of the plurality of mos transistors to place the first mos transistor in an ON condition enabling flow of current between the a source and a drain of the first mos transistor to apply a first one of the plurality of reference voltages to a load, the source of the first mos transistor being at the first one of the plurality of reference voltages;
connecting the a body of the first mos transistor to the first transistor source for the ON condition;
applying voltage to the gate of the first mos transistor to place the first mos transistor in an OFF condition preventing flow of current between the source and the drain of the first mos transistor;
applying voltage to the a gate of a second one of the plurality of mos transistors to place the second mos transistor in an ON condition enabling flow of current between the a source and a drain of the second mos transistor to apply a second one of the plurality of reference voltages to the load and to the drain of the first mos transistor; and
switching the body of the first mos transistor from the first transistor source to a voltage different than the first one of the plurality of reference voltage voltages for the second mos transistor ON condition; the different voltage acting to place a pn junction between the drain and the body of the first mos transistor in the a reverse bias condition, when keeping the first mos transistor body connected to the first mos transistor source would place the pn junction between the drain and the body of the first mos transistor in a source-to-body forward bias condition.
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This invention relates to MOS transistor circuits, in general; and, in particular, to apparatus and methods for biasing MOS transistors used in such circuits.
In a metal-oxide semiconductor field-effect transistor (MOSFET), a thin dielectric barrier is used to isolate the gate and the channel. The voltage applied to the gate induces an electric field across the dielectric barrier to control the free-carrier concentration in the channel region. Such devices are referred to as insulated-gate field-effect transistors (IGFETs), or simply as MOS transistors. A. Grebene, Bipolar and MOS Analog Integrated Circuit Design (1984 J. Wiley & Sons) 106. It should be noted that the term MOS applies even though the gate may be a non-metallic conductor, such as a highly doped polysilicon.
MOS transistors are classified as P-channel or N-channel devices, depending on the conductivity type of the channel region. In addition, they can also be classified as “enhancement” or “depletion” devices. In a depletion-type MOSFET, a conducting channel exists under the gate when no gate voltage is applied. The applied gate voltage controls the current flow between the source and the drain by depleting a part of this channel. In an enhancement-type MOS transistor, no conductive channel exists between the source and the drain at zero applied drain voltage. As a gate bias of proper polarity is applied and increased beyond a threshold value VT, a localized inversion layer is formed directly below the gate. This inversion layer serves as a conducting channel between the source and the drain electrodes. If the gate bias is increased further, the resistivity of the induced channel is reduced, and the current conduction from the source to the drain is enhanced. Id at 106-107.
MOS transistors make good switches because (1) when the device is ON and conducting, there is no inherent dc offset voltage between the source and drain, and (2) the control terminal (the gate) is electrically isolated from the signal path, thus no dc current flows between the control path and the signal path. Id at 303.
Normally, all the active regions of the MOSFET are reverse-biased with respect to the substrate. Thus, adjacent devices fabricated on the same substrate are electrically isolated without requiring separate isolation diffusions. The bulk of the semiconductor region is normally inactive since the current flow is confined to a thin surface channel directly below the gate. The bulk of the MOS transistor is called the “body” or “back gate” and, for efficient operation, is normally tied to the same potential as the source. Id at 108. In certain circuits, such as the conventional voltage level shifting circuits discussed below, however, it may be necessary to apply a different potential to the body in order to maintain the source-body junction in reverse biased condition and prevent a large junction current from flowing inside the transistor. Such current will interfere with normal circuit operation and can permanently damage the device or circuit.
Thus, for an N-channel MOS (NMOS) transistor the body (or bulk) must be biased to make it negative with respect to both source and drain, and for a P-channel MOS (PMOS) transistor the body must be biased to make it positive with respect to both source and drain. In a depletion device, if the reverse voltage VSB=VS−VB between the body and the source (and hence the channel) is increased, the depletion region around the channel will become wider. This will increase the minimum gate voltage VG=VT necessary to maintain the depletion region without creating a conductive channel. In an enhancement device, on the other hand, increasing the reverse voltage will narrow the enhancement region, raising the voltage VG=VT needed to develop the enhancement region to create the channel. This dependence of VT on the magnitude of the reverse biasing voltage VSB is known as the “body effect.” In addition to increasing the magnitude of the threshold VT, another undesired result of the body effect is to reduce the device transconductance and the output impedance when the device is operated in a cascode configuration. The body effect phenomenon is a major limitation of MOS devices operated at VS≠VB. See, Id at 268-271; and R. Gregorian, et al., Analog MOS Integrated Circuits for Signal Processing (1986 J. Wiley & Sons) 77-78.
This limitation can be seen by examination of the operation of a conventional voltage level shifting circuit shown of
To overcome this problem, the bodies or “back gates” of transistors M1, M2 connected to lower voltages V1, V2 are connected to a voltage VB≧VS in order to maintain the reverse biased condition. The greater source-to-body bias VSB will, however, increase the body effect for the transistors M1, M2 connected to apply the lower voltages V1, V2, and the gain of those devices will be decreased. Thus, because the channel-ON resistance RDSON directly correlates to the gain, in order to achieve the same target RDSON, the MOS structures M1, M2 with the larger body effects will require more area or “footprint”. So, all MOS switches except the one tied to the largest voltage, must be made larger to accommodate the larger higher voltage differentials. Higher potential difference between the body and the source will also dramatically reduce the efficiency of the operation of the device. Moreover, uniformity of the respective resistances RDSON between the different devices will be reduced, giving less control over the saturation current point, with the risk of putting the power supply under greater burden due to transients.
It is, therefore, an object of the present invention to overcome the forward biasing problem in voltage level shifters and other circuits which subject MOS devices to different voltage levels, without the need to use larger MOS transistors to compensate for the body effect.
The invention provides control of the body effect in MOS transistors, without the need to increase their areas, by switching the source-to-body bias from one voltage to another when the transistor goes between channel current flow ON and OFF conditions. In accordance with a preferred embodiment, a MOS transistor used to selectively connect a voltage to a load has its body connected to its source during the ON condition, and its body connected to another voltage potential to maintain reverse bias during the OFF condition.
For an illustrative voltage level shifter application, described in greater detail below, a plurality of MOS transistors are connected in parallel to act as switches for selective connection of respective different voltage sources to a capacitive load. Auxiliary switches are provided to connect the body of each main switch, either to its source when it is in the ON condition or to the highest one of the applied voltages when it is in the OFF condition. For a PMOS implementation, the body is connected to the source and the drain is tied to ground when the switch is ON, but when the switch is OFF the body and the gate are both connected to the highest voltage.
Embodiments of the invention have been chosen for purposes of illustration and description, and are shown with reference to the accompanying drawings, wherein:
Throughout the drawings, like elements are referred to by like numerals.
For simplicity in understanding the principles of the invention,
In
Implementation of the circuit of
In operation, when transistor M3 is turned ON to apply the highest voltage V3 across capacitive load CL, M3 has its gate at 0 volts and its body at V3; M2 has its gate at V3 and its body at V3 (switch S2 in the “B” position); and M1 has its gate at V3 and its body at V3 (switch S1 in the “B” position). M3 is ON; M2 is OFF; and M1 is OFF; so, the load CL is charged with the voltage V3. To charge the capacitive load CL with the voltage V2, M3 is turned OFF with its gate and body at V3; M2 is turned ON with its gate at 0 volts and its body connected to its source by setting the switch S1 to its “A” position; and M1 is left in the OFF position with its gate at V3 and its body at V3. To connect the lowest voltage V1 to load CL, M3 is turned OFF with its gate at V3 and its body at V3; M2 is turned OFF with its gate at V3 and its body at V3 (S2 in the “B” position); and M1 is turned ON with its gate at 0 volts and its body switched to its source (S1 switched to its “A” position). In this way, for their respective ON conditions, the bodies of M3 and M2 are connected to the lower voltages V1 or V2, respectively, so that the MOS structures do not have to be as large. However, when those switches are OFF they are connected to V3, to prevent reverse current flow from the higher voltage V2 or V3, when the higher voltage V2 or V3 is connected to load CL. Thus, each device has its body or back gate switched so that it is either connected to the circuit's highest potential when in the OFF condition, or its most efficient operating point (tied to its source) when in the ON condition. By connecting to the highest potential (i.e., V3) in the OFF condition, there is assurance that the forward bias condition will never be reached.
A specific implementation of the construction of auxiliary switch S1 is shown in
In operation, when VIN is connected to ground (0 volts), turning M1 ON, V3 will be applied to the gate of M4 (through the inverter IV1) and 0 volts will be applied to the gate of M5, thereby turning M4 OFF and turning M5 ON. This will connect the body of M1 through M5 to the source of M1, allowing efficient operation during the ON condition of transistor M1. On the other hand, when voltage V3 is applied at VIN to turn transistor M1 OFF, the gate of M4 will be connected to ground (
The switching of V3and V1 is all done in M4 and M5. Those transistors are, however, drawing very little current because they serve merely to switch the back gate, not to convey the main current flow to charge load CL. Thus, their relative RDSON resistances or gains are not critical and they can be made very small, relative to the main switching transistors M1, M2 and M3. The inverter IV1 is normally present in a typical cross-coupled type of shifter that might be used to load quiescent current (VIN and
Also, switching of the back gates gives better control of ON condition resistances RDSON, with consequential better uniformity of resistance. As a consequence, the construction becomes less process dependent because the body effect variance is eliminated.
Those skilled in the art to which the invention relates will appreciate that substitutions and modifications can be made to the described embodiments, without departing from the spirit and scope of the invention as defined by the claims.
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