An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.
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1. An apparatus comprising:
a well of a first type comprising a first plurality of regions;
a substrate of a second type comprising a second plurality of regions;
a first plurality of circuits formed on the well;
a second plurality of circuits formed on the substrate;
a first potential coupled to and powering the first plurality of circuits;
a second potential coupled to and powering the second plurality of circuits;
a third potential coupled to and biasing the first plurality of regions such that the well has the third potential; and
a fourth potential coupled to and biasing the second plurality of regions such that the substrate has the fourth potential.
2. The apparatus of
3. The apparatus of
5. The apparatus of
a first transistor coupled between the first potential and the third potential; and
a second transistor coupled between the second potential and the fourth potential.
6. The apparatus of
8. The apparatus of
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This is a divisional of prior application Ser. No. 09/464,023 filed on Dec. 15, 1999 56a 76a, the heavily doped n-type region 74 is connected to the power rail 78. Likewise, for the substrate tap 76a 56a, the heavily doped p-type region 54 is connected to the power rail 58.
As described above, the well tap 56a 76a biases the n-type well 68 (
In
In
Feed-throughs are pre-determined routes for the placement of designated signals, such as the power rails 58 and 78. Instead of leaving the placement of the tap cells 80 to be determined by the automatic placement tool, the feed-throughs 58a and 78a indicate where the power rails 58 and 78 will subsequently be placed. Because the automatic placement tool “knows” where the power rails 58 and 78 will be, the tool may place the tap cells 80 close to these power rails 58 and 78. The effect is to avoid excessive use of metal for connection between the tap cells 80 and the power rails 58 and 78.
The separate feed-throughs 58a for the voltage Vsssupp 58 are placed a distance 122 apart. The feed-throughs 78a for the voltage Vddsupp 78 may likewise be placed the distance 122 apart. In one embodiment of the invention, the distance 122 is approximately 55 microns. Recall that the tap cells 80 may be optimally placed about 55 microns apart to effectively bias the substrate 40 and the well 68. Thus, the placement of the feed-throughs 58a and 78a may result both in fewer tap cells 80 and in shorter metal lines for routing to the tap cells 80.
In
In
In one embodiment of the invention, the Vsssupp and the Vddsupp signals are routed in the metal 3 layer rather than in the metal 2 layer. The metal 2 layer may thus be reserved for the primary Vss and Vdd signals, which are thicker and which provide power to each cell circuit 90.
A typical integrated circuit may include multiple metal layers. For example, a circuit may include a first metal layer, M1, a second metal layer, M2, a third metal layer, M3, a fourth metal layer, M4, a fifth metal layer, MS, and so on, as needed.
Each metal layer may be thought of as a sheet of metal, with all layers being parallel to one another. However, the metal lines for each layer may run orthogonally to the metal lines for adjacent layers. Thus, if the metal lines in M1 run in one direction, the metal lines in M2 run orthogonally to the metal lines in M1, and the metal lines in M3 run orthogonally to the metal lines in M2, which are thus parallel to the metal lines in M1. The different metal layers may be connected, as needed, by vias. Vias are vertical connections between the metal layers.
In
In
However, the tap cells 80 are connected to the power rails 58 and 78. The metal line 84 connecting to the tap cell 80 is formed in the M2 layer. The via 86, a vertical connector of two metal layers, connects the metal line 84 (in M2) to the power rail 58 (in M3). In the cross-sectional view of
Another fabrication issue arises from the addition of the power rails 58 and 78. Recall that, in conventional integrated circuit designs, the p-type substrate 40 is biased with the power rail 50 (
In
The likelihood of destroying the transistor 132 may be predicted by calculating the area of the line 130, the area of the gate 134, and taking a ratio of the two. In one process technology, if the ratio exceeds a predetermined value, the transistor 132 may be destroyed.
The electrostatic discharge problem, however, does not arise if the charge being built up on the line 130 has a path to the p-type substrate 40 (which is, in effect, ground). In
The power rails 58 and 78, however, bias the p-type substrate 40 differently. The p-type substrate 40 is no longer biased to Vss, but instead is biased to Vsssupp.
Conventionally, a node area check, or NAC, protection device, may be incorporated into a design to prevent electrostatic discharge from destroying one or more transistors during fabrication. However, conventional design tools such as automatic routing tools may not properly determine where NAC protection devices are appropriate, particularly where additional power rails 58 and 78 are used.
Accordingly, in one embodiment of the invention, NAC protection devices are incorporated into the tap cells 80. Looking back to
In addition to reducing leakage from the transistors, the tap cell 80 may be used for protection against electrostatic buildup during the fabrication of the integrated circuit 120. Turning to
The drain of a transistor 88a is connected to the power rail 78. The source of the transistor 88a is connected to the power rail 70, which runs orthogonally to the power rail 78, in one embodiment of the invention. Using the NAC protection device 88a during the fabrication process, a transistor to which connections are etched has a path from the power rail 70 to the power rail 78.
The tap cell 80 also includes a second NAC protection device 88b. The NAC protection device 88b is connected to the power rail 58 at the drain. The source is connected to the power rail 50. During fabrication, any standard cell connected to the power rail 50 has a path to the power rail 58, thus preventing a transistor from being destroyed due to electrostatic buildup.
In
The NAC protection device 88b, however, provides a path for the electrostatic discharge to follow. By making a connection between the power rail 50 and the power rail 58, the built-up current may discharge to the p-type substrate 40. The gates 142a and 144a are thus protected.
Thus, in accordance with some embodiments of the invention, in an integrated circuit design, tap cells are placed outside of cell circuits for connection to power rails which do not connect to the cell circuits. The tap cells may bias the substrate and the well. Feed-throughs for the power rails are provided for efficient automatic placement of the tap cells as well as efficient use of metal for connecting the tap cells to the new power rails. Additional transistors are placed inside the tap cells, where needed, such that electrostatic charge built up during fabrication does not destroy gate dielectrics.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
Hoffman, Eric J., Clark, Lawrence T., Amrelia, Vikas R., Soetan, Raphael A., Do, Tuan X.
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