GaN-based permeable base transistor and method of fabrication

Abstract

An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.

Description

RELATED APPLICATIONS

This application Genii GenII system. Other such systems can be used here as well. Seamless epitaxy of GaN via MBE on GaN quasi-substrates can be achieved by growing the epilayers in group III-rich conditions. These base and emitter layers replicate the underlying GaN quasi-substrate layer without renucleation. The base and collector layers are doped with silicon (Si) to carrier concentrations of 5×10¹⁶ and 5×10¹⁸, respectively.

When the PBT is in ON condition, the majority carriers flow from emitter (held at ground potential) to collector (biased at positive potential). Under normal operation, the Schottky barrier is reverse-biased by a negative base-to-emitter voltage. A voltage dependent depletion region forms beneath the Schottky barrier. This constricts the effective area of the n-channel (reducing the depletion region on either side of the emitter finger), causing the channel to open and the collector current to vary with applied base bias.

In a PBT, the base bias induces a potential barrier under the collector. Near pinch-off, electrons that are injected from the emitter are accelerated by the collector bias, and pass across the potential barrier. At higher collector biases, the thermionic emission current rises exponentially with applied collector bias eventually becoming space charge limited, resulting in a triode mode device operation, where the collector current does not saturate at high collector voltages.

When a negative bias is applied to the collector, the depletion region expands and current flow through the channel is restricted. This will ultimately result in pinch off of the channel, and turn off of the PBT. Pinch off can be approximated using the equation:

$V=\frac{1{\mathrm{qNa}}^2}{2{\varepsilon }_r{\varepsilon }_0}$
where q is the charge of an electron, a is the channel thickness (or, in the case of a PBT, half the width of 1 finger), ∈(r) is the relative permittivity of the material, and ∈(0) is the permittivity of vacuum.

Fabrication Methodology

FIGS. 3a through 7 demonstrate a process flow for the fabrication of a GaN PBT in accordance with one embodiment of the present invention. This process flow includes all steps required to fabricate the device, as well as the design of a photolithography mask set drawn using AutoCAD. Various process alternatives are also provided.

The GaN PBT, because it is based on vertical transport, has three distinctly doped layers versus the two of lateral transistor devices for the metal contacts and the device itself to perform optimally. The material structure to be employed in the GaN PBT, in accordance with one embodiment of the present invention, is shown in FIG. 2a.

Due to the lattice mismatch of GaN grown on sapphire or SiC, the bottom n⁺ layer is deposited thick (e.g., n⁺5×10¹⁸ cm⁻³, HVPE) to keep the vertical threading dislocations minimal The layer structure is chosen because the heavily doped regions will be used for ohmic contacts and the lightly doped region will be used for a Schottky contact to adequately pinch off for a given range of high frequency operation. The desired blocking voltage of the transistor determines the thick n-region. The final structure will look similar to that shown in FIG. 1b, where the material layers are the same as in FIG. 2a.

Note that a full PBT will have a plurality of the collector fingers, and is this particular case. Only three are shown in FIG. 1b for the purpose of illustration. In one particular embodiment, the full PBT device has 20 collector fingers, each surrounded by two base regions to control the width of the channel, as shown in FIG. 1b. It will be appreciated that, in developing a process for a PBT device, it is necessary to have tolerances to variability in the semiconductor material characteristics and fabrication process. Some tolerances that are used herein are passivation layers, implantation, and pre-metal deposition treatments.

When referring to example embodiments of the PBT process described herein, the following views shall be discussed and are illustrated in FIG. 2b: view 1 is the overall top view; view 2 is the cross section through the collector RF probe pad; view 3 is the cross section through the collector ohmic pad; view 4 is the cross section through the base collector fingers; and view 5 is the cross section through the base RF probe pad.

This is a seven-mask process flow that is the baseline for all of the subsequent versions. Various modifications and details not included in this version will be apparent in light of this disclosure.

This particular embodiment begins with the HVPE growth of 10 μm of heavily doped (e.g., 2×10¹⁸ cm⁻³ to 5×10¹⁸ cm⁻³) n-GaN followed by 2 μm of MBE grown, lightly doped (e.g., 2×10¹⁶ cm⁻³ to 5×10¹⁶ cm⁻³) n-GaN and 0.3 μm of MBE grown, highly doped (e.g., 2×10¹⁸ cm⁻³ to 5×10¹⁸ cm⁻³) n-GaN. The silicon nitride deposition (to be discussed in turn) is to passivate the sidewalls of the collector fingers to prevent shorting of the base to the collector if metal accidentally deposits on the sidewalls.

The mask levels for this example process are shown here in Table 1:

TABLE 1

Level 1 He implant mask
Level 2 Nitride isolation pad
Level 3 Collector ohmic pad mask
Level 4 E-beam lithography of collector fingers for liftoff
Level 5 Base recess and metallization
Level 6 Emitter and device isolation etch, emitter ohmic
Level 7 Microwave test pad metal deposition

The process flow will now be discussed in steps, and with reference to the FIGS. 3a through 7. Note that the following steps are not necessarily intended to implicate any rigid order of performance, and other embodiments may have the steps performed in a different order, with a similar end product produced.

Step 1: Perform RCA wafer clean. The purpose of the RCA wafer clean is to remove organic contaminants (e.g., dust particles, grease or silica gel) from the wafer surface, as well as any oxide layer that may have built up, and any ionic or heavy metal contaminants.

Step 2: Open windows for helium (He) implantation using optical lithography. Due to the fact that the PBT is a “normally-on” device, the semiconductor material is conducting by default. Thus, an insulating layer is used to isolate the pads from the device. In this particular embodiment, the insulating layer is provided with He implantation. FIG. 3a shows the optical lithography for He implantation of this step. As can be seen, the photo resist (PR) is shown is each of the views in locations where no He implantation is desired. In one particular embodiment, the wafer is patterned with about 9 μm photo resist for the He implantation.

Step 3: Perform He²⁺ implantation at about 250 keV, 1.35 μm isolation depth (determined from a TRIM calculation). FIG. 3b shows the locations of He implantation with the diagonal striping. In one particular embodiment, a dose of about 1×10¹⁵ cm⁻³ was targeted with an acceleration voltage of 180 keV at an implant angle of 7°. With these parameters, TRIM simulations estimated an implant depth of about 2 μm.

Step 4: Strip the photo resist mask. The resulting structure after stripping is shown in FIG. 3c.

Step 5: Open windows for thin, high quality silicon nitride pad (SiN_x), about 1000–2000 Å thick, using optical lithography. FIG. 3d shows the optical lithography for the SiN_x pad of this step.

Step 5a: Perform deposition of high quality SiN_x pad, 1000–2000 Å thick. This SiN_x layer serves as the second electrical isolation for the collector and base contact pads. FIG. 3e shows the resulting structure after the SiN_x deposition of this step. In one particular embodiment, 1000 Å of high quality SiN_x pads were deposited on top of the He-implant region via plasma enhanced chemical vapor deposition (PECVD).

Step 5b: Perform lift-off of high quality silicon nitride pad, 1000–2000 Å thick. FIG. 3f shows the resulting structure after the SiN_x lift-off of this step, where all SiN_x deposited on top of photo resist is removed.

Step 6: Open windows for Ti metal pad using optical lithography. FIG. 3g shows the optical lithography for the Ti pad of this step.

Step 6a: Perform Ti metallization. FIG. 3h shows the resulting structure after the Ti metallization of this step. In one particular embodiment, Ti/Au (500 Å/1000 Å) collector metal pads are deposited using e-beam evaporation.

Step 6b: Perform lift-off of Ti metallization. FIG. 3i shows the resulting structure after the Ti metallization lift-off of this step, where all Ti deposited on top of photo resist is removed.

Step 7: Perform E-beam lithography of collector fingers and for self-aligned base recess and metallization. FIG. 3j shows the E-beam lithography of the collector fingers of this step. In one particular embodiment, the wafer is patterned with e-beam lithography using PMMA photo resist (about 0.14 μm) for the metallization of the collector fingers.

Step 7a: Perform ohmic metallization of collector. Prior to metallization, a 1 minute HCl:DI H₂0 (1:1) dip is used for removing contaminants on the semiconductor surface. Although not mentioned in other steps, this can beneficially be used for all metal depositions on semiconductor material. FIG. 3k shows the resulting structure after the Ti/Ni metallization of this step. In one particular embodiment, the metal scheme used for the collector fingers is Ti/Ni with thicknesses of 100 Å and 400 Å, respectively. With this arrangement, Ti acts as the metal contact, while Ni serves as the base shallow etch mask.

Step 7b: Perform lift-off of ohmic metallization of collector. FIG. 3m shows the resulting structure after the Ti/Ni metallization lift-off of this step, where all Ti/Ni deposited on top of photo resist is removed. In one particular embodiment, each collector finger is about 0.2 μm wide and 230 μm in length. Since only 200 μm of this length covers each finger active region of the device, the total finger area is 40 μm². Each device has 20 fingers either with a 1:1 pitch (evenly spaced) or 1:3 pitch.

Step 8: Open windows for a Ti cap in collector pad region using optical lithography. FIG. 3n shows the optical lithography for the Ti cap of this step.

Step 8a: Deposit thin Ti cap in collector pad region again to prevent collector metal fingers from peeling upward and losing contact to the pad. FIG. 3p shows the resulting structure after the Ti metallization of this step. In one particular embodiment, Ti/Au (500 Å/1000 Å) collector metal caps are deposited using e-beam evaporation.

Step 8b: Perform lift-off of the thin Ti cap in collector region. FIG. 3q shows the resulting structure after the Ti metallization lift-off of this step, where all Ti deposited on top of photo resist is removed.

Step 9: Open windows for the base recess/metallization (collector lines are part of mask) using optical lithography. FIG. 3r shows the optical lithography for the base recess/metallization of this step.

Step 9a: Perform a high density plasma etch to recess the base layer to n⁻ layer (e.g., about 0.5 μm). FIG. 3s shows the resulting structure after the high density plasma etch in the base region of this step. In one particular embodiment, the wafer is etched using a custom-built inductively coupled plasma (ICP) etching system utilizing pure Cl₂ chemistry. Etching can be performed at a chamber pressure of about 3.8×10⁻³ torr, 350 W ICP power and about −400 V chuck bias with a ramp down to about −200V bias for the last minute of the etch. The ramp down etches a layer of material damaged by plasma leaving behind undamaged GaN for subsequent metal contact deposition. This etch-damage removal enables excellent ohmic electrical characteristics. Approximately 0.5 nm etch depth is achievable.

Step 9b: Perform conformal SiN_x deposition for spacer and sidewall passivation. This layer prevents shorting between the base and collector if metal accidentally deposits on the finger sidewalls. FIG. 3t shows the resulting structure after the SiN_x deposition for spacer and sidewall passivation of this step. In one particular embodiment, the conformal SiN layer is less than 500 Å.

Step 9c: Perform directional etch to remove SiN_x on parallel surfaces. FIG. 3u shows the resulting structure after the directional etch for SiN_x removal of this step. In one particular embodiment, a directional reactive-ion etching (RIE) of the SiN planes parallel to the surface was used to expose the base layer between the fingers.

Step 9d: Perform base metallization (Pt/Ni). FIG. 3v shows the resulting structure after the base metallization of this step. In one particular embodiment, the base contact was deposited using Ni/Pt/Au (Schottky contacts) having layers of thickness 100 Å/400 Å/100 Å, respectively.

Step 9e: Perform lift-off of base metallization (Pt/Ni). FIG. 3w shows the resulting structure after the base metallization lift-off of this step.

Note that a post Schottky deposition anneal is used to alloy the ohmic contacts. This is because the Schottky metal is deposited before the emitter ohmic metal. A low temperature anneal does not substantially alter the forward bias behavior of the Schottky contacts, but decreases the reverse leakage current. Further note that the Schottky contacts are the contacts in the base region). In one particular embodiment, an anneal for about 60 seconds at 500° C. is used to maintain low reverse current leakage while providing low contact resistance.

Step 10: Open emitter etch/contact window using optical lithography. FIG. 3x shows the resulting structure after the optical lithography for emitter etch of this step. In one particular embodiment, the wafer is patterned with a thick photoresist (e.g., about 4 μm) for a deep etch of 2 μm to 3 μm down to the emitter layer via ICP etching.

Step 10a: Etch emitter recess to bottom, HVPE n⁺ GaN quasi-substrate layer (e.g., about 2.5 μm). FIG. 3y shows the resulting structure after the etching of the emitter recess of this step.

Step 10b: Perform emitter ohmic metallization. FIG. 3z shows the resulting structure after the emitter ohmic metallization of this step. In one particular embodiment, the emitter ohmic contacts were deposited using a Ti/Al/Ni/Au metal scheme having thicknesses of 300 Å/1500 Å/400 Å/1500 Å, respectively.

Step 10c: Perform lift-off of emitter ohmic metallization. FIG. 3aa shows the resulting structure after the emitter ohmic metallization of this step.

Step 11: Open windows for RF test pad metallization using optical lithography. FIG. 3bb shows the resulting structure after the optical lithography of this step.

Step 11a: Deposit RF test pad metal. FIG. 3cc shows the resulting structure after the deposition of test pad metal of this step. In one particular embodiment, this metal includes an adhesion layer (e.g., titanium or nickel) and a thick gold (Au) capping layer, since Au is a good microwave conductor and prevents oxidation.

Step 11b: Perform lift-off RF test pad metal. FIG. 3dd shows the resulting and final structure after the RF test pads liftoff of this step.

Variations on Fabrication Methodology

A first variation on the PBT fabrication methodology deals with the deposition of the SiN_x in step 5. In more detail, a conformal deposition of SiN_x over the entire wafer followed by photo resist patterning and wet chemistry etch to remove the SiN_x from the unwanted areas may be more desirable, since SiN_x is sometimes difficult to remove via liftoff. In this case, the SiN_x is about 1000 Å thick, and the wet chemical etch will provide a shallow slope on the sidewalls which will ensure metal continuity from the collector fingers to the contact pad. In addition, the metal pad on top of the collector region can be altered to Ni/Pt because of the new Schottky metal on the collector fingers.

The electron beam lithography can also be changed, to provide a second variation. In particular, instead of opening up windows for the fingers and depositing metal as previously described in steps 7 through 7b, a large window can be opened. For example, FIG. 4 shows the e-beam lithography for opening a large base window in accordance with one such embodiment of the present invention. This window would be used for base recess and metallization as well as collector finger metallization. This will ensure that the metal on the collector fingers is not very thick, thus minimizing the chance of connection between the various fingers.

Following base recess, all steps would be similar to those previously discussed until step 9d, where the Schottky metal deposited would be the metal for both the base region and collector fingers. The Schottky metal would be feasible as the collector metal because of ballistic electrons that could pass the potential barrier. In addition, the Ti capping layer on the collector contact in steps 8 through 8b can be omitted, in this particular variation.

In a third variation of the fabrication process, a “0” level Ti/Pt layer can be used. In more detail, note that the first layer (step 3) is a He implantation, which requires alignment for further steps in the process. In particular, implanted He areas are not distinguishable under optical alignment For this reason, a “0” level mask for subsequent optical and electron beam alignment was added. The metal to be used for enabling optical alignment is titanium (Ti) followed by platinum (Pt). In one such embodiment, this “0” level mask is a Ti/Pt layer of about 200–500/1500 Å, respectively. These metals are chosen because of Ti's good adhesion to GaN and Pt is a good alignment metal for e-beam writers (because it is high Z). Crosses for optical alignment and squares for e-beam alignment are thus provided.

The thick Pt was found to work best for this e-beam writing system. Also, it was found that the He²⁺ implantation given in step 3 would penetrate the photo resist about 3.50 μm based on a TRIM calculation of Rp+ΔRp (the ion range and range straggling). This shows that a thick resist, such as AZ4620, is needed. In addition, the SiN_x etch can be done via a wet chemistry of NH₄F, which will leave a shallow slope on the nitride walls due to the slow etching and isotropy characteristic of wet chemistry etches. The e-beam photo resist, PMMA, is not intended to be a dry etch mask and for this reason, cannot be used as previously given in step 7. For this reason, only the collector fingers shall be opened.

In one such particular embodiment for high power operation, 20 fingers could be used. These fingers shall be 40–200 μm long and varying width (0.15–0.3 μm). The metal on top of these fingers can be, for example, Schottky, Ni/Pt/Ni (200/500/500 Å), where the final Ni layer is used as an etch mask since it was found to withstand a chlorine etch well. This is followed by the base etch similar to step 9. The settings of this etch shall be ICP, ˜0.43 μm in depth using pure Cl₂ chemistry, 400 W ICP power, and 200 eV ion energies. The low bias voltage is used to provide a slow and accurate etch depth. The structure resulting from the base etch following collector metal deposition (with photo resist) is shown in FIG. 5a. The decreased etch depth (0.43 μm) is due to an additional etch step that is needed and will be described next.

A base metal deposition as given in step 9b isolates the base metal from the GaN material on the sides of the collector fingers so an additional etching after the SiN_x deposition is needed to expose the sidewalls of the collector fingers, and to allow better base metal contact and, therefore, better base voltage control of the collector current resulting in higher transconductance in the device. This deposited SiN_x is, for instance, less than 500 Å via PECVD. This thickness is decreased since the minimum base region width is 1500 Å and 1000 Å of SiN_x on both sides would completely close the base region. This additional etch is a two-stage etch.

First, a CH₄—O₂ mix is used via RIE to directionally remove the SiN_x since Cl₂ has a much faster etch rate on GaN than on SiN_x. Following SiN_x removal, an ICP base etch for collector finger contact will be used to etch the GaN 0.07 μm as shown in FIG. 5b. The 0.07 μm depth is exactly the thickness of the subsequent metal deposition to prevent shorting of any metal that accidentally deposits on the sidewalls or in case the metal deposition is slightly thicker than expected. After this additional base etch for collector finger contact, the base is metallized with Ni/Pt (300/400 Å). Following this, all steps can be as previously discussed.

A fourth variation of the fabrication process includes the initial deposition of Ti/Al/Pt alignment markers. The addition of Al is to create an ohmic contact at the first layer for ohmic circular transmission line measurement (CTLM) and Schottky diode test structures that will be employed since the e-beam writer cannot write large areas during definition of the collector regions (otherwise, the first ohmic deposition). The addition of Al will not affect the e-beam alignment with the thick Pt (e.g., 1500 Å) deposited. He implantation under both base and collector contact pads is used due to the high conductivity of the material. This is shown in FIG. 6a. The placement of the e-beam alignment markers is also given. Each alignment box is 4 μm×4 μm. Note that they are 75 μm from the region to be written, due to the stringent requirements of the ebeam writing tool.

The first SiN_x deposition is similar to previous versions with the exception that it is now included under the base contact pad (as well as the collector pad) as shown in FIG. 6b. This is a double safeguard for pad isolation. Now referring to FIG. 6c, note that the metal deposition shown on the collector pad is altered. Ni and Pt are both high stress films, so Ti/Au was chosen as a replacement since Ti is low stress and Au prevents oxidation to underlying metals. In one particular embodiment, these are deposited at 500/1000 Å, respectively.

Collector fingers were also changed from Schottky to ohmic since collector and base metals were no longer to be deposited simultaneously. The new metal scheme is Ti/Ni (100/400 Å). Process tests support the use of a thicker Ni layer and removal of the Al layer and are the reason for this increase in thickness. This thin metal is the maximum thickness allowed with the thin (e.g., 1500 Å) e-beam resist needed for fine features (e.g., 0.15 μm). Following this metal liftoff, SiN_x is deposited (as previously described with the two stage etch).

After the base metallization, the emitter is etched. This requires a thick resist of, for instance, AZ4620 of about 4 μm. Dimensions of the emitter etch are given in FIG. 6d, and the final device structure is shown in FIG. 6e.

A fifth variation of the fabrication process includes a modification to the silicon nitride pad deposited in steps 5, 5a, and 5b. In this alternative embodiment, the SiN_x pad is square such that, the He implanted region will extend out to the collector fingers, and no SiN will be under the fingers. This will reduce the difference in height between the fingers in the collector pad region (e.g., view 3 of FIG. 2b) relative to the height of the fingers out of the collector pad region (e.g., view 4 of FIG. 2b), which helps to prevent the metal fingers from disconnecting from the collector pad due to a significant difference in height. One such alternative embodiment is shown in FIG. 7, where there is only a layer of titanium under the fingers at the collector pad region (and no SiN layer). Thus, the height difference of the collector fingers in the collector region and the collector fingers out of the collector region is about one layer of titanium.

FIG. 8 shows a top view SEM picture of a completed PBT device configured in accordance with the present invention. As can be seen, high accuracy in the alignment of the different mask layers was achieved since the devices were processed with an optical lithography alignment tolerance in the order of 1.5 μm. This tolerance is much smaller than the usual limit for this technique.

FIG. 9 shows detailed SEM images of the collector finger of two different devices, with device (a) having 1:1 finger pitch and device (b) having 1:3 finger pitch. One half the finger width (0.2 μm/2) is the effective device channel and the base contact thickness (600 Å) is the equivalent gate length. Note that these values are very small when compared to the conventional FET device features. Further note that a ramp down from −400V bias to −200V bias during the etch step produced a fairly smooth etched base surface. A finger sidewall angle of approximately 85° was achieved, which is highly anisotropic. A nickel metal layer thickness of 400 Å acted as an excellent etch mask as can be appreciated by the uniform morphology of the finger structures.

Probing of the various CTLM test structures shows ohmic metal contacts which have specific contact resistivity, ρ_c, of about 3×10⁻⁶Ω·cm², which is an indication of the excellent contact quality.

The DC characteristic curve of a device with 1:1 finger pitch is shown in FIG. 10. The output characteristics have been measured for an applied base-emitter bias V_BE ranging from +0.5 V to −1.0 V. The collector-emitter voltage V_CE is in the 0 V to 5.5 V range. From the plot, it is evident that the base voltage controls the output current I_C, showing transistor action. For V_CE=+5.0 V and V_VE=+0.5V, a current density J_C of up to 520 mA/mm² is achieved. DC testing of the devices shows good base control (modulation Of I_CE), and current densities of up to 450 mA/mm² were achieved for a V_CE of 5.0V.

The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

1. A method for fabricating an etched grooved GaN-based permeable-base transistor device, comprising:

opening a window for helium implantation on a hydride vapor phase epitaxy (HVPE) grown n⁺ GaN quasi-substrate layer, using optical lithography;

implanting helium on the n+ n⁺ GaN quasi-substrate layer over the window for helium implantation, so as to provide an approximately 2 μm thick insulating layer for contact pads of the device;

opening a window for collector fingers using E-beam lithography;

depositing an ohmic metallization layer over the window for the collector fingers;

lifting-off ohmic metallization, thereby forming the collector fingers;

opening a window for a self-aligned base recess using optical lithography;

etching to recess a base layer to an n⁻ GaN quasi-substrate layer grown on the n⁺ GaN quasi-substrate layer, wherein the etching is performed with a ramp down in chuck bias voltage wherein said ramp down is from a high chuck bias voltage to a low chuck bias voltage;

opening a window for a collector contact pad, using optical lithography;

depositing a high quality silicon nitride layer over the window for a collector contact pad, the high quality silicon nitride layer being about approximately 1000–2000 Å thick, and deposited over the window for helium implantation via plasma enhanced chemical vapor deposition (PECVD); and

lifting-off or wet chemical etching the high quality silicon nitride layer, thereby forming a silicon nitride collector contact pad.

2. The method of claim 1 wherein the high quality silicon nitride layer is about approximately 1000–2000 Å thick, and is deposited over the window for helium implantation via plasma enhanced chemical vapor deposition (PECVD).

3. The method of claim 1 further comprising:

opening a window for Ti metallization of the collector contact pad using optical lithography;

depositing Ti over the window for Ti metallization of the collector contact pad; and

lifting-off Ti metallization, thereby forming a Ti collector contact pad.

4. The method of claim 3 further comprising:

opening a window for a second Ti metallization of the collector contact pad using optical lithography;

depositing Ti over the window for the second Ti metallization of the collector contact pad; and

lifting-off second Ti metallization, thereby forming a Ti cap over the collector contact pad.

5. The method of claim 1 wherein depositing Ti over the window for Ti metallization of the collector contact pad includes depositing Ti/Au at thicknesses of about approximately 500 Å/1000 Å, respectively, using e-beam evaporation.

6. The method of claim 1 further comprising:

opening an emitter etch/contact window using optical lithography;

etching an emitter recess to the n⁺ GaN quasi-substrate layer;

depositing an emitter ohmic metallization layer over the etched emitter recess; and

lifting-off emitter ohmic metallization, thereby forming an emitter contact pad.

7. The method of claim 1 wherein the emitter ohmic metallization layer includes at least one of titanium, aluminum, nickel, and gold.

8. The method of claim 1 wherein the helium implantation is achieved with an implant depth of about approximately 2 μm.

9. The method of claim 1 wherein the ohmic metallization layer over the window for the collector fingers is Ti/Ni with thicknesses of 100 Å and 400 Å, respectively.

10. The method of claim 1 wherein the device has a plurality of collector fingers about approximately 0.2 Å 0.2 μm wide and having a finger pitch between 1:1 and 1:3.

11. A method for fabricating an etched grooved GaN-based permeable-base transistor device, comprising:

opening a window for helium implantation on a hydride vapor phase epitaxy (HVPE) grown n⁺ GaN quasi-substrate layer, using optical lithography;

implanting helium with an implant depth of about approximately 2 μm on the n+ n⁺ GaN quasi-substrate layer over the window for helium implantation, so as to provide an insulating layer for contact pads of the device;

opening a window for collector fingers using E-beam lithography;

depositing an ohmic metallization layer over the window for the collector fingers;

lifting-off ohmic metallization, thereby forming the collector fingers;

opening a window for a self-aligned base recess using optical lithography;

etching to recess a base layer to an n⁻ GaN quasi-substrate layer grown on the n⁺ GaN quasi-substrate layer, wherein the etching is performed with a ramp down in chuck bias voltage; depositing conformal silicon nitride for passivation of the recessed base layer;

directionally etching to remove silicon nitride on planes parallel to the n⁺ GaN quasi-substrate layer;

depositing a base metallization layer; and

lifting-off base metallization, thereby forming a base contact pad.

12. The method of claim 11 further comprising base metallization and wherein an anneal is performed after said base metallization so as to provide the base contact pad with low reverse current leakage and low contact resistance.

13. The method of claim 11 wherein an emitter ohmic metallization layer includes at least one of titanium, aluminum, nickel, and gold.

14. The method of claim 11 wherein the helium implantation is achieved with an implant depth of about approximately 2 μm.

15. The method of claim 11 wherein the ohmic metallization layer over the window for the collector fingers is Ti/Ni with thicknesses of 100 Å and 400 Å, respectively.

16. The method of claim 11 wherein the device has a plurality of collector fingers about approximately 0.2 μm wide and having a finger pitch between 1:1 and 1:3.