A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.
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0. 14. A semiconductor integrated circuit device having a program execution mode and a standby mode comprising:
an external terminal receiving a supply voltage;
a first step down circuit to generate a first internal voltage lower than the supply voltage, and to output the first internal voltage to a first output terminal in the first and the second operating modes;
a second step down circuit to receive the supply voltage from the external terminal, to generate a second internal voltage, and to output the second internal voltage to a second output terminal in the program execution mode, and to stop supplying the second internal voltage to the second output terminal in the standby mode;
a ram and a register;
a ROM;
wherein the first internal voltage is supplied to the ram from the first output terminal, and the second internal voltage is supplied to the ROM from the second output terminal,
wherein the consumption current of the semiconductor integrated circuit device in the standby mode is lower than a consumption current in the program execution mode.
0. 7. A semiconductor integrated circuit device having a first operating mode and a second operating mode comprising;
an external terminal receiving a supply voltage;
a first step down circuit to generate a first internal voltage lower than the supply voltage, and to output the first internal voltage to a first output terminal in the first and the second operating modes;
a second step down circuit to receive the supply voltage through the external terminal, to generate a second internal voltage, and to output the second internal voltage through a second output terminal in the first operating mode, and not to supply the second internal voltage to the second output terminal in the second operating mode;
a volatile memory;
a non-volatile memory;
wherein the first internal voltage is supplied to the volatile memory through the first output terminal, and the second internal voltage is supplied to the non-volatile memory through the second output terminal,
wherein the consumption current of the semiconductor integrated circuit device in the second operating mode is lower than a consumption current in the first operating mode.
1. A semiconductor integrated circuit device having a first operating mode and a second operating mode comprising:
an external terminal;
a first step down circuit to receive a supply voltage through the external terminal, to generate a first internal voltage lower than the supply voltage, and to output the first internal voltage through a first output terminal during the first and second operating modes;
a second step down circuit to receive the supply voltage through the external terminal, to generate a second internal voltage lower than the supply voltage, and to output the second internal voltage through a second output terminal during the first operating mode, and to bring the second output terminal to a ground level during the second operating mode;
a first internal circuit to receive the first internal voltage through the first output terminal;
a second internal circuit to receive the second internal voltage through the second output terminal;
a state control circuit to bring the semiconductor integrated circuit device into the first operating mode or the second operating mode;
wherein the operating current of the second step down circuit is interrupted during the second operating mode.
2. The semiconductor integrated circuit device according to
a third step down circuit to receive the supply voltage through the external terminal, to generate the first internal voltage, and to output the first internal voltage through a third output terminal during the first operating mode, and to bring the third output terminal into high-impedance state during the second operating mode;
wherein the first and third output terminals are connected in common.
3. The semiconductor integrated circuit device according to
a switch connected between the first output terminal and the second output terminal;
wherein the first and second internal voltages are substantially equal, and
wherein the switch is turned on during the first operating mode, and turned off during the second operating mode.
4. The semiconductor integrated circuit device according to
wherein the first internal circuit includes a ram.
5. The semiconductor integrated circuit device according to
wherein the second internal circuit includes a ROM.
6. The semiconductor integrated circuit device according to
a fourth step down circuit to receives the supply voltage through the external terminal, to generate the second internal voltage, and to output the second internal voltage through a fourth output terminal during the first operating mode, and to bring the second output terminal to a ground level during the second operating mode;
wherein the second and fourth output terminals are connected in common.
0. 8. The semiconductor integrated circuit device according to claim 7 further comprising:
a logic circuit;
wherein the second internal voltage is supplied to the logic circuit through the second output terminal.
0. 9. The semiconductor integrated circuit device according to claim 8,
wherein the logic circuit includes a CPU.
0. 10. The semiconductor integrated circuit device according to claim 8,
wherein the volatile memory is a register that stores operational data of the logic circuit.
0. 11. The semiconductor integrated circuit device according to claim 7 further comprising:
a switch (SW) connected between the first output terminal and the second output terminal,
wherein the switch is turned on in the first operating mode and is turned off in the second operating mode.
0. 12. The semiconductor integrated circuit device according to claim 7,
wherein the second output terminal is connected to the ground in the second operating mode.
0. 13. The semiconductor integrated circuit device according to claim 7 further comprising:
a third step down circuit to generate the first internal voltage and to output the first internal voltage to the first output terminal in the first operating mode, and not to supply the first internal voltage to the first output terminal in the second operating mode,
wherein the current supply capability of the third step down circuit is larger than the current supply capability of the first step down circuit.
0. 15. The semiconductor integrated circuit device according to claim 14 further comprising:
a logic circuit;
wherein the second internal voltage is supplied to the logic circuit to the second output terminal.
0. 16. The semiconductor integrated circuit device according to claim 15,
wherein the logic circuit includes a CPU.
0. 17. The semiconductor integrated circuit device according to claim 15,
wherein the register stores operational data of the logic circuit.
0. 18. The semiconductor integrated circuit device according to claim 14 further comprising:
a switch connected between the first output terminal and the second output terminal,
wherein the switch is turned on in the program execution mode and is turned off in the standby mode.
0. 19. The semiconductor integrated circuit device according to claim 14,
wherein the second output terminal is connected to the ground in the standby mode.
0. 20. The semiconductor integrated circuit device according to claim 14 further comprising:
a third step down circuit to generate the first internal voltage and to output the first internal voltage to the first output terminal in the program execution mode, and to stop supplying the first internal voltage to the first output terminal in the standby mode,
wherein the current supply capability of the third step down circuit is larger than the current supply capability of the first step down circuit.
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The present application is a Continuation application of U.S. application Ser. No. 11/156,648, filed Jun. 21, 2005 now U.S. Pat. No. 7,200,054, the entire disclosure of which is hereby incorporated by reference.
The present application claims priority from Japanese patent application No. 2004-216662 filed on Jul. 26, 2004, the content of which is hereby incorporated by reference into this application.
The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology effectively used for semiconductor integrated circuit devices such as one-chip microcomputers and system LSIs that include a plurality of functional blocks and are provided with step-down power supply circuits for lowering the voltage of external power.
Some large-scale integrated circuits are provided with two step-down circuits for operation and for standby and so constructed that during standby, the step-down circuit for operation is stopped to reduce power consumption during standby. An example of such large-scale integrated circuits is disclosed in Japanese Unexamined Patent Publication No. Hei 2(1990)-244488. Some semiconductor integrated circuit devices selectively use two different types of step-down circuits (series type and switching type) depending on the operation mode for the enhancement of power efficiency. An example of such semiconductor integrated circuit devices is disclosed in Japanese Unexamined Patent Publication No. 2001-211640.
[Patent Document 1] Japanese Unexamined Patent Publication No. Hei 2(1990)-244488
[Patent Document 2] Japanese Unexamined Patent Publication No. 2001-211640
With respect to recent system LSIs such as one-chip microcomputers, there is a tendency to lower the threshold voltage of MOSFET (insulated gate field effect transistor) with decrease in operating voltage. However, this poses a problem. When the threshold voltage is lowered, leakage current due to subthreshold characteristic is increased. The simplest and most effective measure to cope with this is to partially turn off power supply to the circuitry during standby. However, the technique disclosed in Patent Document 1 is for memory and does not support the operation mode of microcomputers or the like. Neither Patent Document 1 or 2 takes into account cases where during standby, a step-down circuit is completely stopped to cut the internal supply voltage (the output of the step-down circuit). Consequently, a step-down circuit that can cope with turn-off of internal power supply was considered. As a result, the present invention was made.
An object of the present invention is to provide a semiconductor integrated circuit device with reduced consumption current. The above and other related objects and novel features of the present invention will be apparent from the description in this application and the accompanying drawings.
The following is a brief description of the gist of the representative elements of the invention laid open in this application. A first step-down circuit stationarily forms internal supply voltage as second reference potential smaller than supply voltage as first reference potential supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal supply voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal supply voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal supply voltage is supplied to internal circuits.
The present invention allows power consumption to be significantly reduced in standby mode and in sleep mode.
Numeral 10 is a reference voltage generation circuit, and receives supply voltage VCCI and ground potential VSSI of the circuitry which are supplied through the external terminals, respectively. The reference voltage generation circuit 10 includes a constant-voltage generation circuit such as a publicly known band gap circuit (BGR). The reference voltage generation circuit 10 forms reference voltages VREFA and VREFD that are deemed to be substantially constant regardless of fluctuation in the external supply voltage VCCI or fluctuation in temperature. The voltage value of the reference voltage VREFA is set to, for example, 1.25V (Volt), and the voltage value of the reference voltage VREFD is set to, for example, 1.5V (Volt). In this embodiment, it is preferable that the independent power supply terminals VCCI and VSSI should be used, as illustrated in
Numerals 20 and 21 denote step-down power supply circuits for analog circuit. Receiving the reference voltage VREFA, the step-down power supply circuits for analog circuit 20 and 21 form internal voltage VDDA (second reference potential) for the analog circuit 40. The voltage value of the internal voltage VDDA is set to, for example, 2.5V (Volt). The step-down power supply circuits for analog circuit 20 and 21 operate on supply voltage VCC and ground potential VSSA of the circuitry which are supplied through the external terminals, respectively. Alphabetic code CA denotes a capacitive element for smoothing constructed on chip (hereafter, also referred to as “on-chip smoothing capacitance”). The capacitive element for smoothing CA is provided between the output terminal (VDDA) of the step-down power supply circuits for analog circuit 20 and 21 and ground potential VSSA of the circuitry.
Numerals 30 to 32 denote step-down power supply circuits for digital circuit. The step-down power supply circuits for digital circuit 30 to 32 receive the reference voltage VREFD and form internal voltage VDDD (third reference potential) for a digital circuit 50. The voltage value of the internal voltage VDDD is set to, for example, 1.5V (Volt). The step-down power supply circuits for digital circuit 30 to 32 operate on supply voltage VCC and ground potential VSSD of the circuitry which are supplied through the external terminals, respectively. Alphabetic code CD denotes an external capacitive element for smoothing (hereafter, referred to as “off-chip smoothing capacitance”). The capacitive element for smoothing CD is connected with the output terminal (VDDD) of the step-down power supply circuits for digital circuit 30 to 32 through an external terminal for connection.
Numeral 40 denotes an analog circuit, comprising, for example, a PLL (Phase Locked Loop) circuit, a DLL (Delay Locked Loop) circuit, an A-D converter, a D-A converter, and the like. The analog circuit 40 uses VDDA and VSSA as power supply. Numeral 50 denotes a digital circuit, comprising a logic circuit such as CPU, and memory circuits such as ROM (Read Only Memory) and RAM (Random Access Memory). The digital circuit 50 uses VDDD and VSSD as power supply. Numeral 60 denotes a state control circuit, and controls the operating state of the semiconductor integrated circuit 1 according to the output signal S of the digital circuit 50, and externally inputted interrupt request signals IRQ, reset signals /RES, and standby signals /STBY. The state control circuit 60 uses VCC and VSSD as power supply. Numeral 70 denotes a level-up conversion circuit, and converts the output signal S (VDDD level) of the digital circuit 50 into a VCC level corresponding to the operating voltage of the state control circuit 60.
The semiconductor integrated circuit device in this embodiment is provided with a plurality of the step-down power supply circuits 20 and 21 and 30 to 32 respectively for the analog circuit 40 and for the digital circuit 50. All or some of the step-down power supply circuits are turned off in correspondence with the operating states of the analog circuit 40 and the digital circuit 50 for the reduction of power consumption. This does not mean that only the operating voltages for the analog circuit 40 and the digital circuit 50 in non-operating state are interrupted. It means that corresponding operating currents that form the output voltages of the step-down power supply circuits 20, 21, and 30 to 32 are also interrupted.
The state control circuit 60 is operated on external power VCC, not on internal power supply. Thus, when the analog circuit or the digital circuit does not operate, the power supply capability of the corresponding step-down power supply circuits 20 and 21 or 30 to 32 is reduced for the reduction of power consumption. The step-down power supply circuits for analog circuit 20 and 21 use the on-chip smoothing capacitance CA, and the step-down power supply circuits for digital circuit 30 to 32 use the off-chip smoothing capacitance CD. The reason why an on-chip smoothing capacitance is used for the smoothing capacitance CA for analog circuit is that the frequency characteristic is enhanced. More specific description will be given. Use of an off-chip smoothing capacitance involves the parasitic inductance of bonding wires and a package; therefore, an on-chip smoothing capacitance can prevent its influence. The smoothing capacitance CD for digital circuit is required to withstand a peak current equal to or rather larger than the frequency characteristic. Therefore, an off-chip smoothing capacitance having a large capacitance value, for example, 0.1 μF to 1 μF, is used.
The amplifier 12, tapped resistor string 13, and MOSFET MP0 constitute a trimming circuit. Output voltage VREF can be varied by changing the resistor tap of the tapped resistor string 13 at which voltage is taken out. Alphabetic code TRIM denotes a trimming signal, and its signal level is set to the level of supply voltage VDDD. Alphabetic code BIE denotes a burn-in enable signal, and its voltage level is set to the level of VDDD. The signals TRIM and BIE are outputted by the CPU, described later, in the digital circuit 50. Numerals 14 and 15 denote level-up conversion circuits, which convert input signals at the VDDD level into the VCC level.
Numeral 16 denotes a decoder, and its operating voltages are of VCC and VSSD. When the signal BIE is at low level (normal operation), the decoder decodes the TRIM signal to generate a resistor tap selection signal. When the BIE signal is at high level (burn-in), the decoder selects the tap in the highest position regardless of the TRM signal. Thus, the reference voltage VREF becomes higher than in normal operation (1.5V or 2.5V). When the microcomputer is in reset state (described later), the outputs of the level-up conversion circuits 14 and 15, that is, the converted signals TRIM and BIE are fixed at low level. It is advisable that the decoder 16 is so constructed that it selects a default value (e.g. the center tap of the resistor string) at this time.
In this embodiment, the level-up conversion circuits 14 and 15 are placed at the front of the decoder 16 (input side). Instead, they may be placed behind the decoder 16 (output side). In this case, VDDD and VSSD are used for the operating voltage of the decoder 16. However, it is preferable that they should be placed at the front of the decoder 16 (input side) because the number of the level-up conversion circuits 14 and 15 can be reduced. More specific description will be given. When the signal TRIM is of n bits, the number of the level-up conversion circuits 14 required is n. If the level-up conversion circuits are placed behind the decoder 16, however, more, specifically 2n, level-up conversion circuits are required.
Alphanumeric code CS1 denotes a current source, which comprises MOSFETs Q6 to Q9. When the enable signal EN is at high level, the n-channel MOSFET Q9 is turned off, and the p-channel MOSFETs Q7 and Q8 are turned on to pass current through the n-channel MOSFET Q6 in the form of diode. Thus, MOSFETs Q5 and Q10 configured in current mirror with respect to the MOSFET Q6 are caused to operate as a current source. When the enable signal EN is at low level, the n-channel MOSFET Q9 is turned on, and the p-channel MOSFETs Q7 and Q8 are turned off. Thus, the current is interrupted. At the same time, the gates and the sources of the MOSFETs Q6, Q5, and Q10 are short-circuited to each other by the MOSFET Q9 being in on state. Thus, they are turned off. As mentioned above, the operating current of a differential amplifier DA1 and an output circuit described next by the enable signal EN being at low level.
Alphanumeric code DA1 denotes a differential amplifier, which comprises: n-channel differential MOSFETs Q1 and Q2; the current source MOSFET Q5 provided between their sources and grounding terminal VSSD of the circuitry; and an active load circuit comprising p-channel MOSFETs Q3 and Q4 in current mirror configuration, provided between the drains of the MOSFETs Q1 and Q2 and power supply terminal VCC. Alphanumeric code MP1 denotes a p-channel output MOSFET. The p-channel output MOSFET MP1 is supplied at its gate with the output signal of the differential amplifier, and constitutes an output circuit together with the current source MOSFET Q10 provided on the drain side. Alphanumeric code MP2 denotes a p-channel MOSFET, and is provided between the gate and the source of the output MOSFET MP1. The MOSFET MP2 is supplied at its gate with the enable signal EN, and forcedly brings the output MOSFET MP1 into off state (output high impedance state) when the signal EN is at low level.
Alphanumeric code MN1 denotes an n-channel MOSFET, which is supplied at its gate with a signal SHORT, and short-circuits VDDD and VSSD when the signal SHORT is at high level. That is, when the signal SHORT is at high level, the n-channel MOSFET NM1 forcedly pulls VDDD out to the VSSD level. Alphanumeric code ESD denotes an electrostatic discharge damage protective element circuit, which comprises diodes, a protective MOSFET, and resistors R1 and R2. To externally install the smoothing capacitance CD, the VDDD terminal is constructed as an external terminal. Therefore, it is preferable that the ESD should be installed to take measures against electrostatic discharge damage.
Alphanumeric code DA2 denotes a differential amplifier, which uses differential MOSFETs Q1 and Q2 and a current source MOSFET Q5 similarly with the foregoing. The drain current of the differential MOSFET Q1 is outputted through the following: a p-channel MOSFET Q11 in the form of diode; a p-channel MOSFET Q12 configured in current mirror with respect thereto; an n-channel MOSFET Q13 in the form of diode that receives the drain current of the p-channel MOSFET Q12; and an n-channel MOSFET Q16 configured in current mirror with respect thereto. The drain current of the differential MOSFET Q2 is outputted through a p-channel MOSFET Q14 in the form of diode and a p-channel MOSFET Q15 configured in current mirror with respect thereto. The difference between the drain current of the p-channel MOSFET Q15 and the drain current of the n-channel MOSFET Q16 drives the output MOSFET MP3. In this differential amplifier DA2, the output signal of an AND gate circuit G1 that receives the output signal of an inverter circuit INV2 that receives the signal EN and the signal BIE2 is transmitted to the gate of the MOSFET Q5. When the signal EN is at high level, the signal BIE2 is at low level, and burn-in state is not established, the step-down circuit is activated. When the signal EN is at low level or the signal BIE2 is at high level, amplification operation is stopped by the MOSFET Q5 being in off state. At the same time, p-channel MOSFETs Q17 and Q18 are turned on, and the operation of the current mirror circuit is also stopped.
Alphanumeric code DIV1 denotes a voltage divider circuit, which feeds voltage equivalent to ½ of output voltage VDDA back to the differential amplifier DA2. Thus, the output voltage VDDA becomes a voltage two times the reference voltage VREFA. Alphabetic codes RC and CC denote a resistor for phase compensation and a capacitance. Such a step-down circuit for digital as illustrated in
Alphanumeric code MP3 denotes a p-channel output MOSFET, which is provided with the voltage divider circuit DIV1 as a load circuit. Alphanumeric code MP4 denotes a p-channel MOSFET. The p-channel MOSFET MP4 receives the output signal of an OR gate circuit G2 that receives the signal EN and the signal BIE2. When both the signal EN and the signal BIE2 are at low level (logic 0), the p-channel MOSFET MP4 is turned on, and brings the gate of the output MOSFET MP3 to high level and the output MOSFET MP3 into off state (output high impedance state). Alphanumeric code MN2 denotes an n-channel MOSFET. When the signal BIE2 is at high level, the n-channel MOSFET MN2 brings the gate of the output MOSFET MP3 to low level, and increases the output voltage VDDA as high as the supply voltage VCC.
Alphanumeric code CS2 denotes a current source. The current source CS2 is constituted of the same circuit elements Q6 to Q9 as in the current source CS1 illustrated in
Alphanumeric code BIE2 denotes a burn-in enable signal, and its signal amplitude is set to between VCC and VSSA. When the signal BIE2 is brought to high level, the output signal of an inverter circuit INV3 is brought to low level. As a result, a p-channel MOSFET Q23 is turned on, and the operation of the differential amplifier DA4 is stopped. Alphanumeric code DIV2 denotes a voltage divider circuit. The voltage divider circuit DIV2 divides the output voltage VDDA through MOSFETs Q24 and Q25 to form a divided voltage equivalent to VDDA2. The voltage divider circuit DIV2 feeds it back to the gate of the differential MOSFET Q2 to form the output voltage VDDA twice the reference voltage VREFA. Alphanumeric code MP7 denotes a p-channel output MOSFET, and the voltage divider circuit DIV2 constitutes a load circuit.
When an interrupt occurs in program execution state, sleep mode, or software standby mode (when IRQ in
Of the metal wiring layers, the metal wiring layers 110 are one electrode of the smoothing capacitance CA, and the metal wiring layer 112 is the other electrode. The left and right metal wiring layers 110 are connected with each other through an upper wiring layer though it is not shown in the figure. The metal wiring layer 111 is wiring for grounding the substrate. The smoothing capacitance CA in this embodiment is characterized in that it is a capacitor relatively less dependent on voltage as compared with MOS capacitors. Therefore, the smoothing capacitance CA can also be used as the phase compensation capacitance CC in
A CMOS inverter circuit comprising the MOSFETs Q36 and Q37 is supplied as operating voltage with the output voltage of the CMOS inverter circuit comprising the MOSFETs Q30 and Q31. A CMOS inverter circuit comprising the MOSFETs Q38 and Q39 is supplied as operating voltage with the output voltage of the CMOS inverter circuit comprising the MOSFETs Q33 and Q34. The output signal of the CMOS inverter circuit comprising the MOSFETs Q36 and Q37 and the output signal of the CMOS inverter circuit comprising the MOSFETs Q38 and Q39 are crosswise transmitted to the gates of the p-channel MOSFETs Q35 and Q32. A reset signal /RES is inputted to a gate circuit G3, and the output signal out is formed through the gate circuit G3. The gate circuit G3 and inverter circuits INV5 and INV6 are operated on supply voltage VCC. Provision of such an output control circuit fixes the output out at high level when the reset signal /RES is at low level. When the microcomputer is in reset state, as illustrated in
Numeral 50 denotes a digital circuit, which comprises RAM (Random Access Memory), ROM (Read Only Memory), register, logic circuit, and the like, as described next. The digital circuit 50 is supplied with VDDD and VSSD or VDDN and VSSD depending on its function. Numeral 60 denotes a state control circuit. Unlike the embodiment in
Numerals 80 and 81 denote level-up conversion circuits, and can be implemented by the circuitry illustrated in
In this embodiment, the following is implemented: (1) two systems of step-down power supplies for digital circuit, VDDD and VDDN, are provided. VDDD is turned off in correspondence with the operating state, and the leakage current of circuits that use VDDD as power supply is thereby prevented from flowing. That is, not only the power consumption of the step-down circuits themselves but also the power consumption equivalent to the leakage current can be reduced. When input signals do not change, theoretically, the consumption current is not passed through a CMOS circuit. However, a problem arises when MOSFETs are microminiaturized and threshold voltages are lowered. Leakage currents (subthreshold leakage currents and the like) flowing between source and drain and gate leakage currents become considerable. In this embodiment, the power consumption in the digital circuit can also be reduced. (2) The state control circuit 60 is caused to operate on internal power supply VDDN that is kept on. Thus, even in standby mode, interrupt request signals IRQ, reset signals /RES, and standby signals /STBY from outside can be coped with.
Numeral 35 denotes a VDDD step-down circuit for standby, and its current supply capability is set low and its power consumption is also reduced. Specifically, the step-down circuit 35 is constructed using, for example, the circuitry illustrated in
The digital circuit 50 comprises CPU 51, RAM 54, and ROM 55 though there is no special limitation. The CPU includes a logic circuit 52 and a register 53. The logic circuit 52 uses VDDD and VSSD as power supply, and the RAM 54 and the register 53 use VDDN and VSSD as power supply. Thus, the information stored in the RAM 54 and the register 53 is held by VDDN even during standby. A register and RAM that store information that may be lost may be supplied with internal voltage VDDD. However, a register and RAM for storing the operating state of the microcomputer must be supplied with normally supplied internal voltage VDDN, as mentioned above. The ROM 55 and the logic circuit 52 use internal voltages VDDD and VSSD. During standby, power supply is off but the information stored in the ROM 55 is not lost because the ROM 55 is a nonvolatile memory. The logic circuit 52 can be supplied with power only in operating state; therefore, there is not problem with the logic circuit 52 even if power supply is off during standby. Numeral 56 denotes a data bus.
Numeral 5 denotes a region where the step-down circuits for analog circuit 20 and 21 are disposed, and this region is disposed in proximity to the analog circuit 40 and the VCC and VSSA pads. Numeral 6 denotes a region where the level-down conversion circuits 90 to 92 are disposed, and this region is disposed in proximity to the signal IRQ, /RES, and /STBY pads. Numeral 7 denotes a region where the reference voltage generation circuit 10 and the step-down circuits 33 and 35 are disposed. This region is disposed in proximity to the VCCI and VSSI pads for the prevention of noise in power supply used in the reference voltage generation circuit 10. Dedicated power supply terminals VCCQ and VSSQ are provided as appropriate for the input/output circuit, especially for the output circuit, though these terminals are not shown in the figure.
In a semiconductor integrated circuit device such as a microcomputer, a system LSI including CPU, or the like, internal power supply for each circuit block can be turned on/off according to the operation mode. Thus, the consumption current can be reduced in sleep mode and standby mode. With this constitution, the following can be implemented by reduction in power consumption in standby mode and sleep mode, in other words, since the influence of leakage current can be prevented: voltage (threshold voltage) can be further lowered, and the performance can be enhanced. More specific description will be given. When a microcomputer or the like is in low-power consumption mode, such as sleep mode and standby mode, internal power supplies to circuit blocks that do not operate in that mode are turned off. At the same time, the step-down circuits themselves are turned off. Thus, the leakage current can be significantly reduced as a whole. As a result, the threshold voltages of MOSFETs can be reduced more than conventional, and low-voltage and high-speed circuitry can be obtained.
Up to this point, the invention made by the present inventors has been specifically described based on the embodiments. However, the present invention is not limited to these embodiments, and it will be obvious that various changes may be made without departing from the scope of the invention. Some examples will be taken. In the embodiments illustrated in
Hiraki, Mitsuru, Horiguchi, Masashi
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