Method for manufacturing semiconductor device, including multiple heat treatment

Abstract

A semiconductor device manufacturing method having forming first and second insulating gate portions spaced from each other on a semiconductor substrate, selectively implanting the first conductivity type impurity ions to the first gate electrode and a surface layer of the semiconductor substrate adjacent to the first insulating gate portion, selectively implanting the second conductivity type impurity ions to the second gate electrode and the surface layer adjacent to the second insulating gate portion, after implanting the first and second conductivity types impurity ions, pre-annealing at a first substrate temperature, and after the pre-annealing, main-activating for the first and second types impurity ions at a second substrate temperature higher than the first substrate temperature for a treatment period shorter than a period of the pre-annealing.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

t_pa=6×10⁻¹³exp[3.74×10⁴/(T₁+275)]  (2)
5×10⁻⁸exp[2.21×10⁴/(T₁+275)]<=t_pa<=6×10⁻¹³exp[3.74×10⁴/(T₁+275)]  (3)

In the treatment conditions shown in FIG. 6 and the equation (3), it is further desirable that the substrate temperature T₁ range from 600° C. to 900° C., and preferably, 800° C. to 900° C. In addition, it is desirable that the treatment period for the pre-annealing be in a range from 5 seconds to 1 hour (3.6×10³ sec).

<Pre-Heating and Main Activation>

The pre-heating is an annealing process, in which the surface of the semiconductor substrate 1 is heated up to the third substrate temperature, and the third substrate temperature is maintained for a certain period (pre-heating period). It is desirable that the third substrate temperature be in a range from 200° C. to 600° C., and preferably, from 300° C. to 500° C. In the example shown in FIG. 7, the third substrate temperature is 400° C., and the pre-heating period is 30 seconds.

The main activation is conducted following pre-heating. Specifically, the main activation is conducted in a state where the temperature of the surface of the semiconductor substrate 1 is maintained at the third substrate temperature. For the main activation, as well as the Xe flash lamp, it is possible to use light sources including a flash lamp that envelopes therein rare gases other than Xe, and an excimer laser and a YAG laser, both of which oscillate laser beams in a pulse shape. It is desirable that treatment time for the main activation, that is, the period for irradiating light emitted from such a light source onto the entire substrate surface (flashing period of flash lamp) be 100 ms or less. Preferably, the flashing period is 10 ms or less, and more preferably, 1 ms or less. In the example shown in FIG. 7, the flashing period of the flash lamp is 1 ms. Moreover, it is desirable that the surface density of the irradiation energy of the light emitted from the light source on the surface of the semiconductor substrate 1 be 100 J/cm² or less, and preferably, 60 J/cm² or less. Note that similar treatment conditions to the above are desirable also for the sub-activation.

FIRST COMPARATIVE EXAMPLE

In a method for manufacturing a semiconductor device according to a first comparative example of the embodiment, in FIG. 2B, the process in which phosphorus ions are implanted entirely into the polycrystalline silicon film 4 by use of the ion implantation method such that the concentration of the phosphorus ions can be 10¹⁹ cm⁻³ or more is omitted. Moreover, the subsequent heat treatment process in which the phosphorus ions are diffused into the polycrystalline silicon film 4 is omitted. Only the process in which the polycrystalline silicon film 4, made substantially of the intrinsic semiconductor, is deposited on the silicon oxide film 3 by use of the CVD method is conducted. Furthermore, in the method for manufacturing a semiconductor device according to the first comparative example, the RTA treatment in the pre-annealing which uses a halogen lamp under the conditions where the substrate temperature is 850° C. and the treatment period is approximately 30 seconds is not performed, but only the annealing using the xenon flash lamp is performed in the main activation. With regard to the other manufacturing processes, the embodiment and the first comparative example are identical to each other.

With regard to the impurity concentration distributions of the gate electrodes 4a and 4b and extension regions 6a and 6b and the gate capacitances of the MOS transistors, the semiconductor device illustrated in FIG. 1 and the semiconductor device manufactured in accordance with the method for manufacturing a semiconductor device according to the first comparative example are compared with each other. Note that the embodiment and the first comparative example are also compared simultaneously with the related art (RTA) in which the RTA treatment using the halogen lamp under conditions where the substrate temperature is 1015° C. and the treatment period is 10 seconds is conducted in place of the pre-annealing and the main activation.

As shown in FIGS. 8A and 8B, the impurity concentration distributions in the gate electrodes 4a and 4b made of polysilicon were investigated by use of secondary ion mass spectrometry (SIMS). The axis of ordinates of FIG. 8A represents concentrations of phosphorus (P) in the gate electrode 4a of the nMOS transistor, and the axis of ordinates of FIG. 8B represents concentrations of boron (B) in the gate electrode 4b of the pMOS transistor. The axes of abscissas of FIGS. 8A and 8B represent depths of the gate electrodes 4a and 4b. As shown in FIGS. 8A and 8B, while the concentrations of the impurities (P and B) are substantially constant in the entire gate electrodes 4a and 4b in the embodiment and the RTA, the impurity concentrations are lowered from the midways of the gate electrodes 4a and 4b in the first comparative example. Specifically, it is understood that, while the impurities are diffused uniformly into the entire gate electrodes 4a and 4b in the embodiment and the RTA, a difference in impurity concentration occurs in the gate electrodes 4a and 4b, the impurity concentrations in the gate bottoms are low, and doped layers of which impurity concentrations are low are formed in the first comparative example.

As shown in FIGS. 9A and 9B, a relationship between the gate capacitance (C) and gate voltage (V) of each of the MOS transistors formed of the gate electrodes 4a and 4b, the gate insulating films 3a and 3b and the wells 18 and 19 was investigated. The axes of ordinates of FIGS. 9A and 9B represent the gate capacitances, and the axes of abscissas thereof represent the gate voltages.

As shown in FIG. 9A, the nMOS transistors according to the embodiment and the RTA substantially coincide with each other in C-V characteristics, and each nMOS transistor has a gate capacitance of approximately 1.15 μF/cm² when the gate voltage is 1.5V. In the first comparative example, the nMOS transistor has a gate capacitance of approximately 0.13 μF/cm² when the gate voltage is 1.5V. This gate capacitance is lower as compared with those of the embodiment and RTA. As shown in FIG. 9B, the pMOS transistors according to the embodiment and the RTA substantially coincide with each other in C-V characteristics, and each pMOS transistor has a gate capacitance of approximately 1.0 μF/cm² when the gate voltage is −1.5V. In the first comparative example, the pMOS transistor has a gate capacitance of approximately 0.2 μF/cm² when the gate voltage is −1.5V. This gate capacitance is lower as compared with those of the embodiment and RTA.

As described above, it is understood that, in the first comparative example, the gate capacitance is lowered, and the gate insulating films under the gate electrodes 4a and 4b are formed apparently thick. This is because, when the impurities (P and B) implanted into the gate electrodes 4a and 4b are activated by use of the xenon flash lamp, the impurities (P and B) are not diffused deeply into the gates, and rather suffer from the extremely short time while the gate electrodes 4a and 4b are being subjected to the high temperature, allowing doped layers with insufficient concentrations to form on the gate bottoms. It was also understood that the insufficiently doped layers of the first comparative example, which were calculated based on the values of the gate capacitances, reached 20 nm or more in thickness with respect to the gate electrodes 4a and 4b with a thickness of 150 nm.

There is a possibility that such a depletion of the gate electrodes 4a and 4b may not only lower the driving power of the transistor but also damage the transistor's functions. However, when the acceleration energy of the impurities implanted into the gate electrodes 4a and 4b in order to control the depletion thereof, the impurities are deeply implanted also into the semiconductor substrate 1, and the extension regions 6a and 6b or the source/drain regions 10a and 10b are formed deep. Furthermore, the impurity diffusion in the direction parallel to the surface of the semiconductor substrate 1 also advances to induce the short channel effect. In addition, the impurities pass through the gate electrodes 4a and 4b to be diffused into the gate insulating films 3a and 3b or the surface region of the semiconductor substrate 1 thereunder, thus fluctuating the threshold voltage of the transistor.

As shown in FIGS. 10A and 10B, the impurity concentration distributions in the extension regions 6a and 6b of the nMOS transistor and the pMOS transistor were investigated by use of the SIMS. The axis of ordinates of FIG. 10A represents the concentrations of arsenic (As) in the extension region 6a of the nMOS transistor, and the axis of ordinates of FIG. 10B represents the concentrations of boron (B) in the extension region 6b of the pMOS transistor. The axes of abscissas of FIGS. 10A and 10B represent the depths of the extension regions 6a and 6b. As shown in FIGS. 10A and 10B, in the embodiment and the first comparative example, the concentrations of the impurities (As and B) are radically lowered from the surfaces (depth: 0 nm) of the extension regions 6a and 6b, and the impurities (As and B) are not detected in regions deeper than approximately 20 nm. However, as shown in FIG. 10A, in the RTA, arsenic with a concentration of approximately 10²⁰ cm⁻³ is detected through to a depth of approximately 20 nm from the surface of the extension region 6a, and arsenic continues to be detected through to a depth of approximately 40 nm. Moreover, as shown in FIG. 10B, in the RTA, boron continues to be detected through to a depth of 50 nm or more.

As described above, in the RTA treatment according to the related art, not only the impurities implanted into the gate electrodes 4a and 4b made of polycrystalline silicon but also the impurities implanted into the semiconductor substrate 1 made of monocrystalline silicon are diffused. Therefore, the shallow extension regions 6a and 6b of which depths are, for example, 20 nm or less cannot be formed.

SECOND COMPARATIVE EXAMPLE

In a method for manufacturing a semiconductor device according to a second comparative example of the embodiment, in FIG. 2B, the process in which phosphorus ions are implanted entirely into the polycrystalline silicon film 4 by use of the ion implantation method such that the concentration of the phosphorus ions can be 10¹⁹ cm⁻³ or more is omitted. Moreover, the subsequent heat treatment process in which the phosphorus ions are diffused into the polycrystalline silicon film 4 is omitted. Only the process in which the polycrystalline silicon film 4 made substantially of the intrinsic semiconductor is deposited on the silicon oxide film 3 by use of the CVD method is conducted. With regard to the other manufacturing stages, the embodiment and the second comparative example are identical to each other.

With regard to the impurity concentration distributions of the gate electrodes 4a and 4b and the gate capacitances of the MOS transistors, the semiconductor device illustrated in FIG. 1 and the semiconductor device manufactured in accordance with the method for manufacturing a semiconductor device according to the second comparative example are compared with each other.

As shown in FIGS. 11A and 11B, the impurity concentration distributions in the gate electrodes 4a and 4b made of polysilicon were investigated by use of the SIMS. The axis of ordinates of FIG. 11A represents concentrations of phosphorus (P) in the gate electrode 4a, and the axis of ordinates of FIG. 11B represents concentrations of boron (B) in the gate electrode 4b. The axes of abscissas of FIGS. 11A and 11B represent depths of the gate electrodes 4a and 4b. As shown in FIGS. 11A and 11B, the concentrations of the impurities (P and B) are substantially constant in the entire gate electrodes 4a and 4b in the embodiment. Moreover, as shown in FIG. 11B, the concentration of boron (B) is substantially constant in the entire gate electrode 4b also in the second comparative example. However, as shown in FIG. 11A, the concentration of phosphorus (P) is lowered from the midway of the gate electrode 4a of the nMOS transistor in the second comparative example.

Specifically, in the second comparative example, it is understood that, while the boron (B) is diffused uniformly into the entire gate electrode 4b in the pMOS transistor, a difference in concentration of phosphorus (P) occurs in the gate electrode 4a in the nMOS transistor, the impurity concentration of the gate bottom is low, and doped layers with insufficient concentrations are formed.

As shown in FIGS. 12A and 12B, a relationship between the gate capacitance (C) and gate voltage (V) of each of the MOS transistors formed from the gate electrodes 4a and 4b, the gate insulating films 3a and 3b and the wells 18 and 19 was investigated. The axes of ordinates of FIGS. 12A and 12B represent the gate capacitances, and the axes of abscissas thereof represent the gate voltages thereof.

As shown in FIG. 12B, the pMOS transistors according to the embodiment and the second comparative example substantially coincide with each other in C-V characteristics, and each pMOS transistor has a gate capacitance of approximately 1.0 μF/cm² when the gate voltage is −1.5V. As shown in FIG. 12A, the nMOS transistor according to the embodiment has a gate capacitance of approximately 1.15 μF/cm² when the gate voltage is 1.5V. However, in the second comparative example, the nMOS transistor has a gate capacitance of approximately 0.85 μF/cm² when the gate voltage is 1.5V. This gate capacitance is lower as compared with that of the embodiment.

As described above, boron (B) is diffused into the entire gate electrode 4b of the pMOS transistor in the second comparative example, and therefore, the embodiment and the second comparative example substantially coincide with each other in gate capacitance of the pMOS transistor. However, a doped layer with insufficient concentrations is formed in the gate electrode 4a of the nMOS transistor, and therefore, the gate capacitance of the nMOS transistor in the second comparative example is lowered as compared with that in the embodiment. Specifically, it is understood that the gate insulating film 3a under the gate electrode 4a is formed apparently thick.

Such a difference between the nMOS transistor and the pMOS transistor in the second comparative example originates mainly from a difference in the ease of diffusion between the n-type impurity and the p-type impurity in the gate electrodes 4a and 4b. Specifically, the heat treatment conditions in the case of diffusing the impurities into polysilicon differ between the n-type impurity and the p-type impurity. The process window of the nMOS transistor is narrower as compared with that of the pMOS transistor. Prior to the p-type impurity of the pMOS transistor, the n-type impurity doped to the gate electrode 4a of the nMOS transistor in which the process window is narrower is doped into the polycrystalline silicon film 4 for which the shape has not yet been processed as illustrated in FIG. 2B, and then a sufficient diffusion treatment is performed therefor. Therefore, the treatment conditions for the pre-annealing are reduced more than those of the RTA treatment according to the related art (1015° C. and 10 sec). Specifically, in such conditions, the temperature can be lowered, and the time can be shortened. Hence, the depths of the extension regions 6a and 6b in which the impurity concentrations become approximately 10¹⁸ cm⁻³ are restricted to be 20 nm or less, and simultaneously, the resistances of the extension regions 6a and 6b can be lowered. Thus, a stable process in which the lowering of yield is controlled can be expected.

As described above, the method for manufacturing a semiconductor device according to the embodiment of the present invention includes the plurality of heat treatment processes differing in heat treatment temperature and time in the event of activating the impurity ions implanted individually into the polycrystalline and monocrystalline silicons. Specifically, the annealing at a low temperature for a long time is conducted, and only the impurity ions in the polycrystalline silicon are selectively diffused. Then, to finish, the entire implanted impurity ions are activated in high concentration by irradiation of high-brightness light at a high temperature for an extremely short time, for example, the light from a flash lamp. The diffusion of the impurity ions implanted into the monocrystalline silicon can be controlled, and simultaneously, the depletion of the gate electrodes made of the polycrystalline silicon can be prevented. Hence, the low-resistant and shallow extension regions 6a and 6b can be formed, and simultaneously, the impurity ions in the gate electrodes 4a and 4b can be diffused sufficiently. It becomes possible then to control the profiles of the impurities precisely, and a high-performance MOS transistor having a shallow junction corresponding to the miniaturization can be manufactured stably with ease.

MODIFICATION EXAMPLE OF EMBODIMENT

Although the case of implanting the n-type impurity ions to the entire polycrystalline silicon film 4 as illustrated in FIG. 2B has been described in the embodiment, the present invention is not limited to this. It is desirable that the impurity ions of the first conductivity type be implanting into at least a region in the polycrystalline silicon film 4, where the gate electrode 4a is formed.

As illustrated in FIG. 13, in the modification example of the embodiment, the polycrystalline silicon film 4 substantially made of an intrinsic semiconductor is deposited, followed by deposition of a resist film by the spin-coating method. The resist film is selectively removed by use of the photolithography method, thus forming the resist pattern 20 which has an opening in a region where the p-well 8 is formed. The n-type impurity ions are selectively implanted into the polycrystalline silicon film 4 on the p-well 18 by use of the resist pattern 20 as a mask for the implanted ions. The ion implantation conditions in this case are identical to those of the embodiment. In addition, with regard to the other manufacturing processes, the embodiment and the modification example are identical to each other.

Also in accordance with the modification example of the embodiment, the depletion of the gate electrodes 4a and 4b can be restricted, and simultaneously, the extension regions 6a and 6b and the source/drain regions 10a and 10b can be formed shallow. Moreover, the impurity diffusion in the direction parallel to the surface of the semiconductor substrate 1 can be prevented, thus making it possible to control the short channel effect.

It is also thought that, before the shape of the polycrystalline silicon film is processed, not only are the n-type impurity ions selectively implanted into the polycrystalline silicon film 4 on the p-well 18, but also the p-type impurity ions are selectively implanted into the polycrystalline silicon film 4 on the n-well 19. However, in this case, the etching rate of the RIE differs between the n-type polycrystalline silicon film 4 and the p-type polycrystalline silicon film 4, and therefore, the process precision of the gate electrodes 4a and 4b deteriorates. Hence, a stable process is not obtained, thus lowering the driving power of the transistor.

Meanwhile, in the case of the modification example, in the event of processing the gate electrodes 4a and 4b illustrated in FIG. 2C, the n-type polycrystalline silicon film (n-type doped region) 4 and the polycrystalline silicon film (n-type undoped region) made of the intrinsic semiconductor will be etched simultaneously. Because the etching rate is substantially equal between the n-type doped region and the n-type undoped region, precisely processed gate electrodes 4a and 4b can be formed. Moreover, because the n-type impurity ions are not implanted into the polycrystalline silicon film 4 on the n-well 19, excessive ion implantation for inverting the conductivity type of the gate electrode 4b into the p type can be avoided in the ion implantation process illustrated in FIG. 4B. Hence, the implantation amount of the p-type impurity can be restricted without increasing the resistance of the gate electrode 4b, thus making it possible to lead to the stabilization of the process.

As described above, according to the embodiment of the present invention, the method for manufacturing a semiconductor device having low-resistant and shallow impurity diffusion layers and being equipped with good driving power can be provided.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming first and second insulating gate portions to be spaced from each other on a semiconductor substrate, the first insulating gate portion including a first gate insulating film and a first gate electrode doped with an impurity of a first conductivity type, and the second insulating gate portion including a second gate insulating film and a second gate electrode doped with an impurity of a second conductivity type;

selectively implanting impurity ions of the first conductivity type to the first gate electrode and a surface layer of the semiconductor substrate adjacent to the first insulating gate portion;

selectively implanting impurity ions of the second conductivity type to the second gate electrode and the surface layer adjacent to the second insulating gate portion;

after implanting the impurity ions of the first and second conductivity types, performing pre-annealing at a first substrate temperature; and

after the pre-annealing, performing pre-heating of the semiconductor substrate at a third substrate temperature; and

after the pre-heating, performing main activation for the impurity ions of the first and second types at a second substrate temperature higher than the first and third substrate temperature temperatures for a treatment period shorter than a period of the pre-annealing and shorter than a period of the pre-heating.

2. The method of claim 1, wherein the forming first and second insulating gate portions comprises:

forming an insulating film on the semiconductor substrate;

forming a polycrystalline conductive film doped with the impurity of the first conductivity type on the insulating film; and

selectively removing the insulating film and the polycrystalline conductive film to form the first and second gate insulating films and the first and second gate electrodes.

3. The method of claim 2, wherein the forming first and second insulating gate portions further comprises forming first and second sidewall spacers on the semiconductor substrate, the first sidewall spacer being adjacent to the first gate insulating film and the first gate electrode, and the second sidewall spacer being adjacent to the second gate insulating film and the second gate electrode.

4. The method of claim 2, wherein the forming a polycrystalline conductive film comprises:

depositing a polycrystalline conductive film made substantially of an intrinsic semiconductor on the insulating film;

implanting the impurity ions of the first conductivity type at least to a region where the first gate electrode is formed in the polycrystalline conductive film; and

diffusing the impurity ions of the first conductivity type into the polycrystalline conductive film at a temperature equal to or higher than the third substrate temperature.

5. The method of claim 3, wherein the selectively implanting impurity ions of the first conductivity type comprises:

selectively implanting the impurity ions of the first conductivity type to the first gate electrode and the surface layer adjacent to the first gate electrode; and

selectively implanting the impurity ions of the first conductivity type to the surface layer and the first gate electrode, both of which are adjacent to the first sidewall spacer.

6. The method of claim 5, wherein selectively implanting impurity ions of the first conductivity type further comprises performing sub-activation for the impurity ions of the first conductivity type at the second substrate temperature for a treatment period shorter than the period of the pre-annealing after selectively implanting the impurity ions of the first conductivity type to the first gate electrode and the surface layer adjacent to the first gate electrode, and before selectively implanting the impurity ions of the first conductivity type to the surface layer and the first gate electrode.

7. The method of claim 3, wherein the selectively implanting impurity ions of the second conductivity type comprises:

selectively implanting the impurity ions of the second conductivity type to the second gate electrode and the surface layer adjacent to the second gate electrode; and

selectively implanting the impurity ions of the second conductivity type to the surface layer and the second gate electrode, both of which are adjacent to the second sidewall spacer.

8. The method of claim 7, wherein selectively implanting impurity ions of the second conductivity type further comprises performing sub-activation for the impurity ions of the second conductivity type at the second substrate temperature for the treatment period shorter than the period of the pre-annealing after selectively implanting the impurity ions of the second conductivity type to the second gate electrode and the surface layer adjacent to the second gate electrode, and before selectively implanting the impurity ions of the second conductivity type to the surface layer and the second gate electrode.

9. The method of claim 1, wherein the first substrate temperature T₁ (° C.) and the treatment period t_pa (sec) of the pre-annealing satisfy a relationship represented by a following equation:

5×10⁻⁸exp[2.21×10⁴/(T₁+275)]≦t_pa≦6×10⁻¹³exp[3.74×10⁴/(T₁+275)].

10. The method of claim 9, wherein the first substrate temperature ranges from 600° C. to 900° C.

11. The method of claim 9, wherein the treatment period of the pre-annealing ranges from 5 seconds to 3.6×10³ seconds.

12. The method of claim 4, wherein the pre-annealing and the diffusing the impurity ions of the first conductivity type into the polycrystalline conductive film are performed by use of any of an infrared lamp, and an electric furnace and hot plate operated by resistance heating.

13. The method of claim 1, wherein the treatment period of the main activation is 100 ms or less.

14. The method of claim 13, wherein surface density of irradiation energy of light emitted from a light source for use in the main activation on a surface of the semiconductor substrate is 100 J/cm² or less.

15. The method of claim 14, wherein the light source is a flash lamp into which a rare gas is enveloped.

16. The method of claim 14, wherein the light source is an excimer laser or a YAG laser, each oscillating a laser beam in a pulse shape.

17. The method of claim 4 further comprising performing pre-heating at a third substrate temperature approximately equal to/less than a temperature at the diffusing the impurity ions of the first conductivity type into the polycrystalline conductive film before the main activation, wherein the main activation is performed subsequently to the pre-heating.

18. The method of claim 17 1, wherein the third substrate temperature ranges from 200° C. to 600° C.

19. The method of claim 17 1, wherein the pre-heating is performed by an infrared lampora lamp or a hot plate.