System and method for low power searching in content addressable memories using sampling search words to save power in compare lines

Abstract

An invention is provided for low low power searching in a cam using uses sample words to save power in the compare lines. The invention A method includes comparing a sample section of stored data to a corresponding sample section of search data on a plurality of rows in the cam. If a sample section of the stored data on any row of the plurality of rows is equivalent to the corresponding sample section of the search data, a remaining section of search data is allowed to propagate to the local compare lines coupled to the remaining section of the stored data of each row. However, if the sample section of the stored data is different from the corresponding sample section of the search data, the local compare lines coupled to the remaining section of the stored data on each row are latched.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent application Ser. No. 09/943,653, filed Aug. 30, 2001, now U.S. Pat. No. 6,577,519 and entitled “System and Method for Low Power Search in Content Addressable Memories Using Sample Search Words,” which is incorporated herein by reference; this application is related to: 1) U.S. patent application Ser. No. 09/944,251, filed Aug. 30, 2001, and entitled “System and Method for Low Power Search in Content Addressable Memories Using Non-Precharged Compare lines,” and 2) U.S. patent application Ser. No. 09/944,256, filed Aug. 30, 2001, and entitled “System and Method for Low Power Search in Content Addressable Memories Using Non-Precharged Match lines,” each of which is incorporated herein be reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to memory circuits, and more specifically to low power search techniques in content addressable memory circuits using sample words to save power in compare lines.

2. Description of the Related Art

A content addressable memory (CAM) semiconductor device is a device that allows the entire contents of the memory to be searched and matched instead of having to specify one or more particular memory locations in order to retrieve data from the memory. Thus, a CAM may be used to accelerate any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks.

CAMs provide performance advantages over conventional memory devices having conventional memory search algorithms, such as binary or tree-based searches, by comparing the desired search term, or comparand, against the entire list of entries simultaneously, giving an order-of-magnitude reduction in the search time. For example, a binary search through a non-CAM based database of 1000 entries may take ten separate search operations whereas a CAM device with 1000 entries may be searched in a single operation, resulting in significant time and processing savings. Internet routers often include a CAM for searching the address of specified data, allowing the routers to perform fast address searches to facilitate more efficient communication between computer systems over computer networks.

Conventional CAMs typically include a two-dimensional row and column content addressable memory core array of cells. In such an array, each row typically contains an address, pointer, or bit pattern entry. In this configuration, a CAM may perform “read” and “write” operations at specific addresses as is done in conventional random access memories (RAMs). However, unlike RAMs, data “search” operations that simultaneously compare a bit pattern of data against an entire list (i.e., column) of pre-stored entries (i.e., rows) can be performed.

FIG. 1A shows a simplified block diagram of a conventional CAM 100. The CAM 100 includes a data bus 102 for communicating data, an instruction bus 104 for transmitting instructions associated with an operation to be performed, and an output bus 106 for outputting a result of the operation. For example, in a search operation, the CAM 100 may output a result in the form of an address, pointer, or bit pattern corresponding to an entry that matches the input data.

As mentioned above, to perform a search operation a CAM includes a plurality of bit pattern entries, each comprising a series of CAM cells coupled to a local match line. FIG. 1B is a schematic diagram showing a prior art bit pattern entry 120 in a conventional CAM. The bit pattern entry 120 includes a plurality of CAM cells 122 coupled to a local match line 124. In addition, the bit pattern entry 120 includes a current generator 126 and precharge circuitry 128 coupled to the local match line 124. The local match line 124 is further coupled to an inverter 130, which is coupled to an inverter latch 132. Each CAM cell 122 is also coupled to a pair of compare lines K0 and K1. Although, for clarity, only one CAM cell 122 is shown coupled to compare lines in FIG. 1B, it should be noted that all the CAM cells 122 are actually coupled to compare lines.

During a search operation, the precharge circuitry 128 precharges the match line 124 to a predictable state, which is generally low, to prepare for the search. The compare data, known as the comparand, is then compared to the bit pattern entry 120. Specifically, compare lines, such as compare lines K0 and K1, are used to compare the comparand to the data stored in the CAM cells 122. The current generator 126 begins to supply current to the match line 124. As the compare data is compared to the data stored in each CAM cell 122, the CAM cell will ground the match line 124 if the data stored in the CAM cell 122 does not match the compare data. Thus, if any CAM cell 122 does not match the compare data, the match line 124 will be pulled low. Conversely, if all the CAM cells 122 in the bit pattern entry 120 match the comparand, the match line 124 will remain high. The signal from the match line 124 is then sent through an inverter 130, and then to the inverter latch 132, which provides a high or low output, as described in greater detail below.

FIG. 1C is a diagram showing exemplary search signals 150 for a conventional CAM. The search signals 150 include an external clock 152, a first compare line K0 154, a second compare line K1 156, an internal clock 158, a match line 160, and a search output 162. As previously mentioned, during a search the compare lines 154 and 156 are used to provide search data to a particular CAM cell. Each compare line 154 and 156 will be set to either high or low, depending on the search data. Typically the compare lines K0 154 and K1 156 are set to the inverse of each other, however, when using a ternary CAM cell both compare lines 154 and 156 may be set to the same value. In the example of FIG. 1C, a first set of search data is placed on the compare lines for the first and second external clock cycle 150a and 150b. Then the search data is inverted in the third and fourth external clock cycle 150c and 150d. In addition, the data stored in the CAM cell matches the first set of search data, during the first and second external clock cycle 150a and 150b, and does not match during the third and fourth external clock cycle 150c and 150d.

To set the compare lines 154 and 156 to their appropriate values in a conventional CAM, each compare line 154/156 is first set to a predictable state of zero, or low. Then, one of the compare lines is asserted high. As shown in FIG. 1C, at the rising edge of the first external clock cycle 150a, both compare lines 154 and 156 are set low. Shortly thereafter, one of the compare lines is asserted high, in this case compare line K0 154, thus in the first external clock cycle 150a, K0 154 is asserted high and K1 remains low.

Next, at the rising edge of the second external clock cycle 150b, compare line K0 154 is again set to a predictable state of zero. In this case, the search data for this particular CAM cell remains the same in the second external clock cycle 150b, thus compare line K0 154 is again asserted high shortly after the rising edge of the second external clock cycle 150b. In a similar manner, both compare lines K0 154 and K1 156 are set to a state of zero at the beginning of the third external clock cycle 150c. This time the comparand changes, thus switching compare lines K0 154 and K1 156 such that K1 156 is asserted high shortly after the rising edge of the third external clock cycle 150c, while K0 154 remains low. At the rising edge of the fourth clock cycle 150d, both compare lines 154 and 156 are set to zero. The search data remains the same for the fourth external clock cycle 150d, thus compare line K1 156 is again asserted high shortly after the rising edge of the fourth clock cycle 150d.

Thus, in a conventional CAM the compare lines are pulsed to compare the search data to the data stored in the CAM cell. This results in two transitions for every clock cycle of the external clock 152, regardless of the actual data being placed on the compare lines. As will be explained in greater detail subsequently, each transition requires increased power in the CAM to overcome the capacitance of the compare line.

Continuing with the above example, an internal clock 158 is used to control the search results in the conventional CAM. The internal clock 158 is an inverted clock, which is pulsed slightly after the compare lines 154 and 156 are set to the appropriate search value. As mentioned above, in the example of FIG. 1C the search data matches the data stored in the CAM cell during the first and second external clock cycle 150a and 150b, and does not match during the third and fourth external clock cycle 150c and 150d. Hence, at leading edge of the first internal clock cycle 158a, the match line 160 begins to ramp up, since the data stored in the CAM cell matches the comparand in the first external clock cycle 150a.

The rising match line 160 causes the inverted latch to output a high search output signal 162 during the first internal clock cycle. The precharge circuitry coupled to the match line 160 then causes the match line 160 to discharge and go low at the trailing edge of the first internal clock pulse 158a. As a result, during the leading edge of the second internal clock pulse 158b the output signal 162 is low. The output signal 162 then transitions to high after the match line 160 ramps to a sufficient level, later during the second internal clock pulse 158b. During the third and fourth external clock pulses 150c and 150d, the data stored in the CAM cell does not match the comparand. Hence, both the match line 160 and the output signal 162 are low during the third and fourth internal clock pulses 158c and 158d. Thus, during consecutive match results, the output signal 162 of the conventional CAM generally must transition from low to high during each internal clock cycle.

Each output 162 for each bit pattern entry of the CAM is coupled to a global match line, which is a long line that provides the search results to other areas of the CAM for further processing, such as to priority encoders. The long length of the global match lines results in each global match line having a large capacitance. As a result, every transition on a global match line requires a large amount of power to overcome the large capacitance. Since the output signals from the bit pattern entries propagate to the global match lines, every transition in the output signal results in a large power drain on the CAM. A similar result occurs with respect to the compare lines, each transition in the compare lines requires increased power from the CAM to overcome the capacitance of the compare line.

In view of the foregoing, there is a need for low power search methods for use in content addressable memory circuits. The methods should reduce the power required to perform searches in the CAM, and decrease the amount of transitions required during search operations.

SUMMARY OF THE INVENTION

Broadly speaking, embodiments of the present invention address these needs by utilize sample words to reduce power usage in compare lines. In one embodiment, a method for low power searching in a CAM is disclosed. The method includes comparing a sample section of stored data to a corresponding sample section of search data on a plurality of rows in the CAM. If a sample section of the stored data on any row of the plurality of rows is equivalent to the corresponding sample section of the search data, a remaining section of search data is allowed to propagate to the local compare lines coupled to the remaining section of the stored data of each row. However, if the sample section of the stored data on every row of the plurality of rows is different from the corresponding sample section of the search data, the local compare lines coupled to the remaining section of the stored data on each row are latched.

In an additional embodiment, a match line is disclosed for a CAM. In this embodiment, the match line is one of a plurality of match lines forming a group of match lines. Each match line includes a sample match line coupled to a first set of CAM cells, and a sub-match line coupled to a second set of CAM cells. Each CAM cell in the second set of CAM cells is coupled to local compare lines that are in electrical communication with global compare lines via a plurality of local compare line latches. Coupled to the local compare line latches is a compare line propagation control circuit. In operation, the compare line propagation control circuit latches the local compare lines if a sample section of search data corresponding to the first set of CAM cells is different from data stored in the first set of CAM cells for each sample match line in the group of match lines.

A CAM is disclosed in a further embodiment of the present invention. The CAM includes a group of match lines, wherein each match line includes a sample match line coupled to a first set of CAM cells, and a sub-match line coupled to a second set of CAM cells. Each CAM cell of the second set of CAM cells is coupled to a pair of local compare lines. Also included in the CAM is a plurality of global compare lines, each spanning the width of the CAM, and in electrical communication with a plurality of local compare lines via a plurality of local compare line latches. The CAM further includes a compare line propagation control circuit, which is coupled to the local compare line latches. As above, the compare line propagation control circuit latches the local compare lines if a sample section of search data corresponding to the first set of CAM cells is different from data stored in the first set of CAM cells for each sample match line in the group of match lines. However, if the sample section of search data corresponding to the first set of CAM cells is equivalent to data stored in the first set of CAM cells for any sample match line in the group of match lines, the compare line propagation control circuit allows the search data to propagate from the global compare lines to the local compare lines. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:

FIG. 1A shows a simplified block diagram of a conventional CAM;

FIG. 1B is a schematic diagram showing a prior art bit pattern entry in a conventional CAM;

FIG. 1C is a diagram showing exemplary search signals for a conventional CAM;

FIG. 2 illustrates a CAM chip including two macros, in accordance with one embodiment of the present invention;

FIG. 3 illustrates a single core that incorporates its own maintenance port and its own search port, in accordance with an embodiment of the present invention;

FIG. 4 illustrates a portion of the maintenance port and simplified versions of a sub-block, in accordance with an embodiment of the present invention;

FIG. 5 is a schematic diagram showing a bit pattern entry, in accordance with an embodiment of the present invention;

FIG. 6 is a schematic diagram showing a binary CAM cell, in accordance with an embodiment of the present invention;

FIG. 7 is a schematic diagram showing a ternary CAM cell, in accordance with an embodiment of the present invention;

FIG. 8 is a diagram showing exemplary search signals, in accordance with an embodiment of the present invention;

FIG. 9 is a flowchart showing a method for low power searching in a CAM, in accordance with an embodiment of the present invention;

FIG. 10 is a schematic diagram showing a bit pattern entry, in accordance with an embodiment of the present invention;

FIG. 11 is a diagram showing exemplary search signals including the search output for a bit pattern entry, in accordance with an embodiment of the present invention;

FIG. 12 is flowchart showing a method for low power searching in a CAM having reduced output transitions, in accordance with an embodiment of the present invention;

FIG. 13 is a schematic diagram showing a divided bit pattern entry, in accordance with an embodiment of the present invention;

FIG. 14 is schematic diagram of a bit pattern entry configured for a NOR/NOR type search, in accordance with an embodiment of the present invention;

FIG. 15 is a schematic diagram showing a sample circuit, in accordance with an embodiment of the present invention;

FIG. 16 is a diagram showing exemplary search signals for bit pattern entry configured for a NOR/NOR type search, in accordance with an embodiment of the present invention;

FIG. 17 is a diagram showing exemplary search signals for bit pattern entry configured for a NOR/NOR type search, in accordance with an embodiment of the present invention;

FIG. 18 is a flowchart showing a method for reducing power in a CAM during search operations using sample match lines, in accordance with an embodiment of the present invention;

FIG. 19 is a schematic diagram showing a bit pattern entry configured for a low power compare line search, in accordance with an embodiment of the present invention;

FIG. 20 is a schematic diagram showing an exemplary match sense circuit, in accordance with an embodiment of the present invention;

FIG. 21 is a schematic diagram showing a compare line propagation control circuit, in accordance with an embodiment of the present invention;

FIG. 22 is a diagram showing exemplary search signals for a bit pattern entry configured to save power on the compare lines during search operations, in accordance with an embodiment of the present invention;

FIG. 23 is a diagram showing additional exemplary search signals for a bit pattern entry configured to save power on the compare lines during search operations, in accordance with an embodiment of the present invention;

FIG. 24 is a flowchart showing a method for reducing power on the compare lines of a CAM using sample words, in accordance with an embodiment of the present invention;

FIG. 25 is a schematic diagram showing a ternary CAM cell and its relation to local compare lines and global compare lines, in accordance with an embodiment of the present invention; and

FIG. 26 is a schematic diagram showing the relationship between local compare lines and global compare lines, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An invention is disclosed for low power search methods in content addressable memories. To this end, an invention is disclosed for low power searching in content addressable memories using sample search words to save power in compare lines. Embodiments of the present invention utilize the results of sample searches on multiple rows to gate the propagation of search data on the compare lines that correspond to the rest of the word. If a “miss” results from all the sample words in a group of sample words on multiple rows, the search data is not propagated to the corresponding compare lines for the remainder of the word on each row of the group, thus saving power on those compare lines. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order not to unnecessarily obscure the present invention.

FIGS. 1A-1C were described in terms of the prior art. FIG. 2 illustrates a CAM chip 200 including two macros 205a and 205b, in accordance with one embodiment of the present invention. A chip can, in other embodiments, include one or more macros 205 depending on the application. Each macro 205 is shown including a plurality of cores 204, and each core 204 is accompanied by its associated maintenance port (MP) 203 and search port (SP) 202. In this example, the CAM chip 200 has macros 205 that include eight cores 204 each. Thus, each core 204 is a two-port core having its associated MP 203 and SP 202. The search ports 202 are configured to incorporate circuitry for performing searches in the memory of each of the cores 204, and the maintenance ports 203 assist in performing write operations, read operations, and other maintenance-related operations to each of the associated cores 204.

FIG. 3 illustrates a single core 204 that incorporates its own maintenance port 203a and its own search port 202b, in accordance with an embodiment of the present invention. Each core 204 includes a plurality of sub-blocks 312. In this example, the core 204 has eight sub-blocks 312, and each sub-block 312 has a width to hold a 32-bit word 320, and extends to form a column of 512 rows. It should be understood that the actual “word” 320 width and rows of a sub-block can vary depending on the desired application.

The core 204 also includes a row decoder 307 and a priority encoder (PE) 306. As is well known, the priority encoder 306 is configured to prioritize which match of potentially many matches has the highest priority and thus, is most likely to be the address for the data being searched.

The maintenance port 203a is configured to enable the reading and writing to the addresses selected from the sub-blocks 312 in order to modify and update the contents of the memory for subsequent search operations. In a preferred embodiment, the maintenance port operations are performed independently from the search port 202b operations and are coordinated such that searches continue uninterrupted by way of the search port 202b, while the maintenance port 203a operations occur in parallel with the search operations.

The maintenance port 203a preferably includes a Z decoder that enables only one word in a selected sub-block 312 at one time. To accomplish this, a logical AND is performed between a global wordline and a Z decode line. In this manner, it is possible to access only one word 320 during a read or write operation. The implementation of a Z decode is also referred to as a divided wordline implementation.

For example, FIG. 4 illustrates a portion of the maintenance port 203a and simplified versions of a sub-block 312. Traversing each of the subblocks 312 is a global wordline (GWL). The GWL is coupled to a logical AND gate 426, which is also coupled to a Z decode line (Z1). The output of the AND gate 426 is a local wordline 428 for each sub-block 312. In this embodiment, the sub-block 312 is 32-bits in width and also includes a valid bit 320a. For completeness, a pair of exemplary bitlines is drawn vertically across each of the subblocks 312 and coupling to the local wordline 428. Thus, the AND gate 426 is configured to activate only one local wordline 428 depending upon the signals provided to the respective AND gates 426 which are coupled between Z decode lines (Z1). Inverse multiplexers 422 are provided within the maintenance port 203a and are configured to communicate with the bitlines of the individual sub-blocks 312. In a preferred embodiment, the maintenance port 203a includes 32 inverse multiplexers 422 that appropriately select the correct bitlines of the sub-blocks 312.

As shown in FIG. 4, in addition to a local wordline, each bit pattern entry in a sub-block 312 includes a local match line 434. Generally, each local match line 434 is asserted high during a search operation whenever the data associated with the local match line 434 matches the comparand of the search operation. This is often referred to as a “hit.” Conversely, when the data associated with the local match line 434 docs not match the comparand of the search operation, the local match line 434 is pulled low, often referred to as a “miss.”

Power Savings in Compare Lines

FIG. 5 is a schematic diagram showing a bit pattern entry 500, in accordance with an embodiment of the present invention. The bit pattern entry 500 includes a plurality of CAM cells 502 coupled to a local match line 504. The local match line 504 is further coupled to an inverter 506, which is coupled to an inverter latch 508. Each CAM cell 502 is also coupled to a pair of compare lines K0 and K1. Although, for clarity, only one CAM cell 502 is shown coupled to compare lines in FIG. 5, it should be noted that all the CAM cells 502 are actually coupled to compare lines.

Each CAM cell 502 can be any type of CAM cell suitable for storing data for later search operations, such as a binary CAM cell or a ternary CAM cell as shown in FIGS. 6 and 7, respectively. FIG. 6 is a schematic diagram showing a binary CAM cell 600, in accordance with an embodiment of the present invention. The binary CAM cell 600 includes a storage element 602 having normal and complementary outputs c and K0g_{—s and K1g—}s K0g_—s and K1_—s, which generated local compare lines for the sample words, and remainder global compare lines K0g_r and K1g_r, which generated local compare lines for the remainder of the word.

More particularly, the sample global compare lines K0g_s and K1g_s are buffered every q rows, using buffers 2611, 2612, 2613, and 2614. The outputs of the buffers 2611, 2612, 2613, and 2614 generate the sample local compare lines K0sa, K0sb, K1sa, and K1sb, which are utilized to search the sample words. The remainder global compare lines K0g_r and K1g_r are latched every q rows using latches 2615, 2616, 2617, and 2618. The outputs of the latches 2615, 2616, 2617, and 2618 generate the remainder local compare lines K0ra, K0rb, K1ra, and K1rb, which are utilized to search the remainder of the word. The latches 2615, 2616, 2617, and 2618 are controlled by clock signals 2106a and 2106b, which are generated as illustrated in FIG. 21, discussed in greater detail below.

FIG. 19 is a schematic diagram showing a bit pattern entry 1900 configured for a low power compare line search, in accordance with an embodiment of the present invention. As will be explained subsequently, the bit pattern 1900 is configured to save power on the compare lines by allowing the local compare lines corresponding to the remainder of the word to toggle only when necessary. The bit pattern entry 1900 includes a sample local match line 1902, which is the local match line for the sample word of the bit pattern entry 1900. As shown in FIG. 19, a number m of CAM cells 502 are coupled to the sample local match line 1902. Coupled to each CAM cell 502 of the sample word, are sample local compare lines K0s and K1s.

The bit pattern entry 1900 also includes a match sense circuit 1905, which receives the sample local match line 1902 and a first clock signal CLK1 as inputs. The match sense circuit 1905 generates a sample match signal 1908 as an output, which is utilized as an input to a sample group OR gate, discussed in greater detail below with reference to FIG. 21. The remainder of the bit pattern entry 1900 includes sub-match lines 1904a and 1904b, which are the local match lines for the remainder of the word. Similar to above, a number (n−m)/2 of CAM cells 502 are coupled to each sub-match line 1904a and 1904b. Coupled to each CAM cell 502 of the remainder of the word, are remainder local compare lines K0r and K1r. For example, in one embodiment of the present invention, possible values for n, m, and q can be n=36 m=12 and q=256. In this manner, the probability of a logic value of 1 on the sample match signal 1908 generally is relatively low.

Transistors 1910 and 1912 function as current generators for the sub-match lines 1904a and 1904b. As shown in FIG. 16, a second clock signal CLK2 controls the current injected into the sub-match lines 1904a and 1904b via transistors 1911 and 1913. In addition, the sample match signal 1908 is inverted, by inverter 1930, to generate a signal 1909, which gates the current injected into the sub-match lines 1904a and 1904b via transistors 1914 and 1915.

As can be appreciated, if the local match signal 1908 is a logic 0, then signal 1909 will be a logic 1 because of inverter 1930. The logic 1 on signal 1909 turns OFF transistors 1914 and 1925, and turns ON transistors 1931 and 1932, which pulls the submatch lines 1904a and 1904b to logic 0 via transistors 1931 and 1932. Thus, if the sample word search is a “miss,” the local match signal 1908 will be logic 0 and the submatch lines 1904a and 1904b will be pulled to logic 0 indicating a “miss.”

The sub-match lines 1904a and 1904b are used as inputs to inverters 506a and 506b, which function as match sense amplifiers. The outputs of inverters 506a and 506b are provided as inputs to NOR gate 1302, the output of which is provided to the latch 1304. Thus, if both the sub-match lines 1904a and 1904b have a logic value of 1, then the latch 1304 will store a logic 1, which corresponds to a “hit” on the latch output 1920. The latch 1304 is controlled by the second clock signal CLK2, which is generated by the control block search. Waveformns for CLK2 will be discussed in greater detail below with reference to FIGS. 22 and 23.

FIG. 20 is a schematic diagram showing an exemplary match sense circuit 1905, in accordance with an embodiment of the present invention. As illustrated, the match sense circuit 1905 includes a p-channel transistor 2001, which functions as a current generator, and includes a first terminal coupled to V_DD, a second terminal coupled to a terminal of transistor 2002, and a gate coupled to ground. The first clock signal CLK1 controls the current that is injected into the local match line 1902, via p-channel transistor 2002, which includes a first terminal coupled to transistor 2001, a second terminal coupled to the local match line 1902, and a gate coupled to the first clock signal CLK1. The clock CLK1 is generated via the control lock of the search.

The match sense circuit 1905 also includes an inverter 2003, which functions as a sense amplifier. The inverter 2003 includes an input coupled to the local match line 1902 and an output coupled to the input of inverter 2004, which inverts the output of the inverter 2003 to generate the local match signal 1908. As described next with reference to FIG. 21, the local match signal 1908 is grouped with a number q of local match signals 1908 from other rows to gate the propagation of search data on the compare lines that correspond to the rest of the word. If a “miss” results from all the sample words in a group of sample words on multiple rows, the search data is not propagated to the corresponding compare lines for the remainder of the word on each row of the group, thus saving power on those compare lines, as illustrated next with reference to FIG. 21.

FIG. 21 is a schematic diagram showing a compare line propagation control circuit 2100, in accordance with an embodiment of the present invention. The compare line propagation control circuit 2100 controls the propagation of the search data on the local compare lines corresponding to the remainder of the word. In particular, a plurality of sample match line signals 1908 from a number q rows are provided as inputs to a multiple input OR gate 2101 having q inputs. The sample match line signals 1908 are the sample search outputs from the for the sample word from a number of q bit pattern entries spread over q rows.

The output of the multiple input OR gate 2101 generates a match group signal 2102, which is provided as an input to an AND gate 2103 along with a third clock signal CLK3. The output of the AND gate 2103 provides a latch control signal 2106, which is utilized to control local compare line latches 2104 and 2105. As discussed above with reference to FIG. 26, the compare line latches 2104 and 2105 are utilized to allow the data from the remainder global compare lines K0g_r and K1g_r to propagate to the remainder local compare lines K0r and K1r. As can be appreciated, only if all the sample match signal 1908 inputs to the multiple input OR gate 2101 are logic 0, does the search data from the remainder global compare lines K0g_r and K1g_r not propagate to the remainder local compare lines K0r and K1r. Hence, if any sample match signal 1908 input to the multiple input OR gate 2101 is logic 1, the search data will propagate to the remainder local compare lines K0r and K1r.

FIG. 22 is a diagram showing exemplary search signals 2200 for a bit pattern entry configured to save power on the compare lines during search operations, in accordance with an embodiment of the present invention. FIG. 22 exemplifies two external clock cycles 802a ad 802c. In the first cycle 802a there is a match in both the sample word and in the remainder of the word of a bit pattern entry.

More particularly, during the first external clock cycle 802a, the comparand is loaded on the sample local compare lines K0s and K1s of the sample word. When the sample local compare lines K0s and K1s are charged, the first pulse of the internal clock CLK1 (2201a) occurs and a current is injected in the sample local match line 1902, which ramps up to logic 1 as shown by the waveform 2210. Since the sample word is a match, the sample match signal 1908 toggles to logic 1. When the pulse 2203a of CLK3 occurs the latch control signal 2106 switches to logic 1 and the latches 2104 and 2105 become transparent. As a result the remainder local compare lines K0r and K1r of the remainder of the word are loaded. After this, the pulse 2202a of the clock CLK2 occurs, injecting current in the sub-match lines 1904a and 1904b. Consequently, the sub-match lines 1904a and 1904b ramp up as shown by waveform 2212 making the latch output 1920 to switch to logic 1 signaling a match.

In the second external clock cycle 802c, a “miss” occurs in the sample part of the word for all the bit pattern entries spread over q rows. During the second cycle 802c of the external clock the comparand is loaded again on the sample local compare lines K0s and K1s. Since a “miss” occurs in the sample part of the word for all q rows, a “miss” is generated on the sample, making the sample match line 1902 ramp down. As a result, the sample match signal 1908 switches to logic 0 for all q rows. Because all q of the signals 1908 switch to logic 0, the latches 2104 and 2105 remain opaque and the remainder local compare lines K0r and K1r do not toggle. Consequently, power is saved on the compare lines.

The sub-match lines 1904a and 1904b are also brought down to logic 0, as is the latch output 1920 signaling a “miss.” A waveform showing the current in the k lines has a pulse 2231 in the first external clock cycle 802a. However, the pulse is not repeated in the second external clock cycle 802b, when the “miss” occurred, illustrating the power savings provided by the embodiments of the present invention. A waveform showing the current in the match lines illustrates the savings in the local match lines, as described above.

FIG. 23 is a diagram showing exemplary search signals 2300 for a bit pattern entry configured to save power on the compare lines during search operations, in accordance with an embodiment of the present invention. FIG. 23 exemplifies two external clock cycles 802a ad 802c. In the first cycle 802a there is a match in both the sample word and in the remainder of the word of a bit pattern entry, similar to that illustrated in FIG. 22. In the second cycle 802c, there is a match in the sample word, but a “miss” occurs in the remainder of the word for the bit pattern entry.

The first external clock cycle 802a occurs as described above with reference to FIG. 22. During the second cycle 802c of the external clock the comparand is the same as during the cycle 802a on the sample local compare lines K0s and K1s. As a result, the sample match line 1902 and the sample match signal 1908 remain at logic 1. Thus, latches 2104 and 2105 become transparent and the remainder local compare lines K0r and K1r toggle. Consequently, the waveform showing the current in the k lines has a pulse 2331a in the cycle 802a and a pulse 2331c in cycle 802b.

FIG. 24 is a flowchart showing a method 2400 for reducing power on the compare lines of a CAM using sample words, in accordance with an embodiment of the present invention. In an initial operation 2402, preproces operations are performed. Preprocess operations can include, for example, configuring the CAM, receiving a comprand from the search port, and other preprocess operations that will be apparent to those skilled in the art after a careful reading of the present disclosure.

In operation 2404, search data is loaded onto the sample compare lines for each bit pattern entry. As described above, sample global compare lines are buffered every q rows. The outputs of the buffers generate sample local compare lines, which are utilized to search the sample words.

In operation 2406, a sample section of stored data is compared to a sample section of the search data using the sample compare lines. Generally, the bit pattern entry of the present invention includes a plurality of CAM cells coupled to a match line comprised of a sample match line, and two sub-match lines. The sub-match lines are coupled to inverters, which are coupled to a NOR gate. The output of the NOR gate is provided to a latch, which latches the output of the bit pattern entry.

During a search operation, the bit pattern entry first compares the search data with the data stored in the CAM cells coupled to the sample match line. In the following description n is the total number of CAM cells comprising the bit pattern entry. In addition, m is the total number of CAM cells coupled to the sample match line. Similarly, (n−m)/2 is the number of CAM cells coupled to each sub-match line. Further, m is smaller than n, and preferably, m is much smaller than n (m<<n).

A decision is then made, in operation 2408, as to whether any sample section of stored data matches the sample section of the search data for the q rows grouped together. As described above, a plurality of sample match line signals from a number q rows are provided as inputs to a multiple input OR gate having q inputs. The sample match line signals are the sample search outputs from the for the sample word from a number of q bit pattern entries spread over q rows. If any sample section of stored data matches the sample section of the search data for the q rows grouped together, the method 2400 continues to operation 2410. Otherwise the method 2400 branches to operation 2414.

In operation 2410, search data is loaded onto the remainder compare lines for each bit pattern entry. The remainder global compare lines are latched every q rows. The outputs of the latches generate the remainder local compare lines, which are utilized to search the remainder of the bit pattern entry. The latches are operated based on a match group control signal, which is the output of the multiple input OR gate described in operation 2408.

In particular, the output of the multiple input OR gate generates the match group signal, which is provided as an input to an AND gate along with a third clock signal CLK3. The output of the AND gate provides a latch control signal, which is utilized to control the local compare line latches. The compare line latches are utilized to allow the data from the remainder global compare lines to propagate to the remainder local compare lines.

The remaining section of the stored data is compared to the remaining section of the search data, in operation 2412. Searches occur only on sub-match lines wherein a hit occurred on the related sample match line as described in operation 2406.

A “miss” is generated, in operation 2414, if none of the sample sections of stored data matches the sample section of the search data for the q rows grouped together. Further, if none of the sample sections of stored data matches the sample section of the search data for the q rows grouped together, the search data from the remainder global compare lines is not propagated to the remainder local compare lines. As can be appreciated, only if all sample match signal inputs to the multiple input OR gate are logic 0, does the search data from the remainder global compare lines not propagate to the remainder local compare lines.

Post process operations are performed in operation 2416. Post process operations include CAM maintenance, hit prioritizing, and other post-process operations that will be apparent to those skilled in the art. Advantageously, embodiments of the present invention reduce the amount of power required in the CAM during search operations by not allowing the remainder local compare lines to toggle if a “miss” occurs in all the sample words grouped together in q rows. Further, by properly choosing bit positions throughout the bit pattern entry, the sample portion of the bit pattern entry can be made to have a high probability of missing.

Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims

1. A method for low power searching in a content addressable memory (cam), comprising the operations of:

comparing a sample section of stored data to a corresponding sample section of search data on a plurality of rows in the cam;

allowing a remaining section of search data to propagate to local compare lines coupled to a remaining section of the stored data of each row if a sample section of the stored data on any row of the plurality of rows is equivalent to the corresponding sample section of the search data; and

latching the local compare lines coupled to the remaining section of the stored data on each row if the sample section of the stored data is different from the corresponding sample section of the search data.

2. A method as recited in claim 1, further comprising the operation of loading the search data onto global compare lines, each global compare line spanning a width of the cam.

3. A method as recited in claim 2, further comprising the operation of providing results of a comparison between the sample section of the stored data and the corresponding sample section of the search data for each row of the plurality of rows as an inputs to a logic gate.

4. A method as recited in claim 3, further comprising the operation of allowing search data to propagate from the global compare lines to the local compare lines if an output of the logic gate indicates a comparison result is a match.

5. A method as recited in claim 4, further comprising the operation of latching the local compare lines if the output of the logic gate indicates all the comparison results are misses.

6. A method as recited in claim 1, wherein the remaining section of the stored data is not compared to the corresponding remaining section of the search data if the sample section of the stored data is different from the corresponding section of the search data.

7. A method as recited in claim 1, wherein the sample section of the stored data is smaller than the remaining section of the stored data.

8. A method as recited in claim 7, wherein a match line coupled to the stored data comprises a first section and a second section, both the first section and the second section being coupled to a latch via a gate.

9. A method as recited in claim 8, wherein a first portion of the sample section of the stored data is coupled to the first section of the match line and a second portion of the sample section of the stored data is coupled to the second section of the match line.

10. A match line for a content addressable memory (cam), the match line being one of a plurality of match lines forming a group of match lines, the match line comprising:

a sample match line coupled to a first set of cam cells;

a sub-match line coupled to a second set of cam cells, each cam cell of the second set of cam cells being coupled to local compare lines, the local compare lines being in electrical communication with global compare lines via a plurality of local compare line latches; and

a compare line propagation control circuit coupled to the local compare line latches, wherein the compare line propagation control circuit latches the local compare lines if a sample section of search data corresponding to the first set of cam cells is different from data stored in the first set of cam cells for each sample match line in the group of match lines.

11. A match line as recited in claim 10, wherein the compare line propagation control circuit allows the search data to propagate from the global compare lines to the local compare lines if the sample section of search data corresponding to the first set of cam cells is equivalent to data stored in the first set of cam cells for any sample match line in the group of match lines.

12. A match line as recited in claim 11, wherein the compare line propagation control circuit includes a logic gate having a plurality of inputs, each input of the logic gate being in electrical communication with the sample match line of each match line in the group of match lines.

13. A match line as recited in claim 12, wherein the search data is allowed to propagate from the global compare lines to the local compare lines if an output of the logic gate indicates a match on any sample match line of the group of match lines.

14. A match line as recited in claim 13, wherein the local compare lines are latched if the output of the logic gate indicates a “miss” on all the sample match lines of the group of match lines.

15. A content addressable memory (cam), comprising:

a group of match lines, each match line including a sample match line coupled to a first set of cam cells, and a submatch line coupled to a second set of cam cells, each cam cell of the second set of cam cells being coupled to a pair of local compare lines;

a plurality of global compare lines, each global compare lines spanning a width of the cam, each global compare line in electrical communication with a plurality of local compare lines via a plurality of local compare line latches; and

a compare line propagation control circuit coupled to the local compare line latches, wherein the compare line propagation control circuit latches the local compare lines if a sample section of search data corresponding to the first set of cam cells is different from data stored in the first set of cam cells for each sample match line in the group of match lines.

16. A cam as recited in claim 15, wherein the compare line propagation control circuit allows the search data to propagate from the global compare lines to the local compare lines if the sample section of search data corresponding to the first set of cam cells is equivalent to data stored in the first set of cam cells for any sample match line in the group of match lines.

17. A cam as recited in claim 16, wherein the compare line propagation control circuit includes a logic gate having a plurality of inputs, each input of the logic gate being in electrical communication with the sample match line of each match line in the group of match lines.

18. A cam as recited in claim 16, wherein the search data is allowed to propagate from the global compare lines to the local compare lines if an output of the logic gate indicates a match on any sample match line of the group of match lines.

19. A cam as recited in claim 18, wherein the local compare lines are latched if the output of the logic gate indicates a “miss” on all the sample match lines of the group of match lines.

20. An apparatus, comprising:

means for comparing a sample section of stored data to a corresponding sample section of search data on one or more rows in a content addressable memory;

means for allowing a remaining section of search data to propagate to local compare lines coupled to a remaining section of the stored data of one or more rows if a sample section of the stored data on any row of the one or more rows is equivalent to the corresponding sample section of the search data; and

means for latching the local compare lines coupled to the remaining section of the stored data on one or more rows if the sample section of the stored data is different from the corresponding sample section of the search data.

21. An apparatus as claimed in claim 20, further comprising means for loading the search data onto global compare lines, one or more of the global compare lines spanning a width of the content addressable memory.

22. An apparatus as claimed in claim 21, further comprising means for providing results of a comparison between the sample section of the stored data and a corresponding sample section of the search data for one or more of the one or more rows as an input to a logic gate.

23. An apparatus as claimed in claim 22, further comprising means for allowing search data to propagate from the global compare lines to the local compare lines if an output of the logic gate indicates a comparison result is a match.

24. An apparatus as claimed in claim 23, further comprising means for latching the local compare lines if the output of the logic gate indicates all the comparison results are misses.

25. An apparatus as claimed in claim 20, further comprising means for preventing comparing of the remaining section of the stored data to a corresponding remaining section of the search data if the sample section of the stored data is different from a corresponding section of the search data.

26. An apparatus as claimed in claim 20, wherein the sample section of the stored data is smaller than the remaining section of the stored data.

27. An apparatus as claimed in claim 26, further comprising a match line coupled to the stored data comprising a first section and a second section, and further comprising means for coupling the first section or the second section, or combinations thereof, to a latch via a gate.

28. An apparatus as claimed in claim 27, further comprising means for coupling a first portion of the sample section of the stored data to the first section of the match line, and means for coupling a second portion of the sample section of the stored data to the second section of the match line.

29. A method, comprising:

comparing a first portion of stored data to a corresponding first portion of search data on a row in a content addressable memory; and

providing a second portion of search data to a compare line coupled to a second portion of the stored data of the row if the first portion of the stored data is equivalent to the corresponding first portion of the search data.

30. The method of claim 29, wherein the first portion of stored data is compared to a corresponding first portion of search data on a plurality of rows of the content addressable memory, wherein the second portion of search data is provided to compare lines coupled to the second portion of the stored data of each of the plurality of rows if the first portion of the stored data on any row of the plurality of rows is equivalent to the corresponding first potion of the search data.

31. The method of claim 30, further comprising latching the compare line coupled to the second portion of the stored data if the first portion of the stored data is different from the corresponding first portion of the search data.