A method for mapping an electronic digital circuit to a look Up table (lut) based programmable logic Deviceoperates by selecting an unmapped or partially mapped lut, and identifying a group of circuit elements for mapping on the selected lut based on the available capacity of the selected lut and the mapping constraints. The identified circuit elements are mapped onto the selected lut. The identification of circuit elements and mapping is carried out while taking into consideration the cascade logic associated with the selected lut. The process continues until all circuit elements have been mapped. The group of circuit elements is mapped to the cascade logic prior to mapping on the luts. Conversely, the cascade logic is incorporated only after all circuit elements have initially been mapped onto luts or some elements remain unmapped after all luts have been utilized. The mapping constraints include timing, placement, and size constraints.
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0. 19. A method implemented by a compiler that includes software and hardware on which the software operates, the method comprising:
identifying a circuit based on a mapping constraint and an available capacity of a look up table (lut) of a device;
mapping the identified circuit onto the lut; and
mapping cascade logic associated with the lut after the mapping of the circuit onto the lut.
0. 73. One or more computer-readable storage devices comprising software that is executable on hardware to:
decompose a cluster of logic representing a logic function into logic gates;
identify, among the logic gates, one or more logic gates to be mapped to one or more cascade elements;
map the logic gates to one or more look up tables;
extract the identified one or more logic gates; and
map the identified one or more logic gates onto the one or more cascade elements.
0. 40. A method implemented by a compiler that includes software and hardware on which the software operates, the method comprising:
selecting, by the compiler, a look up table (lut) from one or more luts of a programmable logic device (PLD);
identifying a circuit based on a mapping constraint and an available capacity of the selected lut;
mapping the identified circuit onto the selected lut, and
mapping cascade logic associated with the selected lut when at least one circuit remains unmapped after each of the one or more luts of the PLD have been utilized.
0. 49. An apparatus comprising a compiler that includes software and hardware on which the software operates to cause the apparatus to:
identify a circuit based on a mapping constraint and an available capacity of a look up table (lut) of a device;
map the identified circuit onto the lut such that cascade logic of the lut is incorporated in mapping the circuit,
wherein the compiler maps the cascade logic after each of said circuits has been initially been mapped onto the lut or one or more of said circuits remain unmapped even after each of the luts of the device have been utilized.
6. An improved system for mapping an electronic digital circuit to a look up table (lut) based programmable logic device (PLD) comprising:
selecting means for selecting an unmapped or partially mapped lut,
grouping means for clustering circuit elements for mapping based on an available capacity of the selected lut and at least one mapping constraint,
mapping means for mapping the group of circuit elements onto the selected lut, and
wherein the grouping means and mapping means include the mapping of cascade logic associated with the selected lut after mapping of the group of circuit elements onto the lut.
0. 31. A method implemented by a compiler that includes software and hardware on which the software operates, the method comprising:
selecting at least one look up table (lut) of a device;
identifying a circuit based on a mapping constraint and an available capacity of the selected lut; and
mapping the identified circuit onto the selected lut such that cascade logic associated with the selected lut is incorporated in mapping the circuit,
wherein the compiler maps the cascade logic after each of said circuits has been initially been mapped onto the lut or one or more of said circuits remain unmapped even after each of the luts of the device have been utilized.
0. 61. One or more computer-readable storage devices comprising software that is executable on hardware to:
select an unmapped or partially mapped look up table (lut) from one or more luts of a programmable logic device (PLD);
more luts of a programmable logic device (PLD);
identify a circuit based on a mapping constraint and an available capacity of the selected lut;
cause the identified circuit to be mapped onto the selected lut, and
cause cascade logic associated with the selected lut to be mapped after each said circuit has been mapped onto the luts or when at least one circuit remains unmapped after each of the one or more luts of the PLD has been utilized.
12. A method for programming a programmable logic device including look-up tables and cascade elements, the method comprising:
mapping logic into the look-up tables;
mapping logic into the cascade elements;
repeating the operations of mapping logic into the look-up tables and mapping logic into the cascade elements until all logic has been mapped into the programmable logic device;
identifying logic to be mapped to the cascade elements prior to mapping logic into the look-up tables;
mapping all logic into the look-up tables to generate a mapped list; and
extracting from the mapped list the logic to be mapped into the cascade elements; and
mapping the identified logic to the cascade elements.
14. An electronic system for programming a programmable logic device, the programmable logic device including look-up tables and including cascade elements, and the electronic system comprising:
a selection circuit operable to select look-up tables within the programmable logic device;
a logic grouping circuit coupled to the selection circuit and operable to select and group logic as a function of the available capacity of a selected look-up table; and
a mapping circuit coupled to the selection and logic grouping circuits and operable to map grouped logic into the selected look-up table and into the cascade elements as a function of the available capacity of the selected look-up table, the cascade logic being mapped after the grouped logic is mapped into the selected look-up table.
1. An improved method for mapping an electronic digital circuit to a look Up table (lut) based programmable logic device (PLD) comprising the steps of:
selecting an unmapped or partially mapped lut,
identifying a group of circuit elements for mapping based on an available capacity of the selected lut and a plurality of mapping constraints,
mapping the group of circuit elements onto the selected lut,
continuing the process of selecting an lut, forming a group of circuit elements and mapping until all the circuit elements have been mapped,
wherein the cascade logic associated with each lut is also incorporated in the steps of forming the group of circuit elements and the mapping of the group; and
wherein the cascade logic is incorporated only after either all circuit elements have initially been mapped onto luts or some circuit elements remain unmapped even after all luts have been utilized.
7. A method for mapping circuit elements into a programmable logic device including look-up tables and cascade elements, the method comprising:
selecting a look-up table;
identifying a group of circuit elements to be mapped into the selected look-up table;
mapping the identified group of circuit elements into the selected look-up table; determining whether additional circuit elements can be identified and mapped into the look-up table;
if the determination is that additional circuit elements can be mapped into the look-up table, mapping the additional circuit elements into the look-up table;
if the determination is that additional circuit elements cannot be mapped into the look-up table, determining whether the additional circuit elements can be mapped into a cascade element or elements;
if the determination is that the additional circuit elements can be mapped into a cascade element or elements, then mapping the additional circuit elements into the cascade element or elements;
if the determination is that the additional circuit elements cannot be mapped into the cascade element or elements, then selecting a new look-up table and mapping the circuit elements into the new look-up table; and
repeating the operations of mapping the identified group of circuit elements into the selected look-up table through if the determination is that additional logic cannot be mapped into the cascade element or elements until all circuit elements have been mapped.
2. An improved method as claimed in
3. An improved method as claimed in
4. An improved method as claimed in
XOR, XNOR and NOT functions are not mapped on the cascade logic,
only one of either the gate mapped onto the cascade logic or its input luts have multiple fan-outs,
if the output of the cascade logic is a primary output, then the gate mapped onto it is not an ‘AND’ or ‘NOR’ gate,
if the mapped gate has multiple fan outs then the outputs are not connected to more than one other gate mapped into a cascade logic element, and
if the mapped gate connects to the output of a multi-fan out lut then the output of the lut is not, connected to more than one cascade logic element.
5. An improved method as claimed in
the number of common inputs to the fan-in luts of the cascade logic is not greater than the number of inputs of the lut,
the gate mapped onto the cascade logic is not of the type XOR, XNOR or NOT, and
only one of either the gates mapped on top the cascade logic or its input luts is multi fan.
8. The method of
9. The method of
identifying the circuit elements to be mapped to the cascade element or elements prior to mapping elements into the look-up tables;
mapping all circuit elements into the look-up tables without consideration of the cascade element or elements to generate a mapped list;
extracting from the mapped list the circuit elements to be mapped to the cascade element or elements; and
mapping the identified circuit elements to the cascade element or elements.
10. The method of
11. The method of
13. The method of
15. The electronic system of
17. The electronic system of
18. The electronic system of
0. 20. The method as recited in claim 19, wherein the cascade logic is incorporated after each said circuit has been initially been mapped onto one or more said luts or one or more said circuits remain unmapped even after each of the luts of the device have been utilized.
0. 21. The method as recited in claim 19, wherein the mapping constraint includes a timing constraint, a placement constraint, or a size constraint.
0. 22. The method as recited in claim 19, wherein the mapping of the cascade logic incorporates one or more of the following constraints that are dependent upon connectivity of an architecture:
XOR, XNOR and NOT functions are not mapped on the cascade logic;
either the gate mapped onto the cascade logic or its input said luts have multiple fan-outs, not both;
if the output of the cascade logic is a primary output, then the gate mapped onto it is not an ‘AND’ or ‘NOR’ gate;
if a mapped gate has multiple fan outs then respective outputs are not connected to more than one other gate mapped into a cascade logic element; and
if a mapped gate connects to the output of a multi-fan out lut then an output of the lut is not connected to more than one cascade logic element.
0. 23. The method as recited in claim 19, wherein the mapping of the cascade logic includes verifying one or more of the following conditions that are dependent upon connections of an architecture:
a number of common inputs to a fan-in said luts of the cascade logic is not greater than a number of inputs of the lut;
a gate mapped onto the cascade logic is not of type XOR, XNOR or NOT; and
either the gates mapped on top the cascade logic or its input luts is multi fan, not both.
0. 24. The method as recited in claim 19, further comprising clustering elements to form the circuit based on the available capacity of the lut.
0. 25. The method as recited in claim 19, further comprising:
determining whether an additional circuit is able to be mapped into the lut; and
if determination is that the additional circuit is able to be mapped into the lut, mapping the additional circuit into the lut.
0. 26. The method as recited in claim 25, further comprising if the determination is that the additional circuit is not able to be mapped into the lut, determining whether the additional circuits are able to be mapped into cascade logic.
0. 27. The method as recited in claim 26, further comprising if the determination is that the additional circuit is able to mapped into cascade logic, then mapping the additional circuit into the cascade logic.
0. 28. The method as recited in claim 27, further comprising if the determination is that the additional circuit is not able to be mapped into the cascade logic, then selecting a new lut and mapping the additional circuit into the new lut.
0. 29. The method as recited in claim 27, wherein the additional circuit is mapped to the cascade logic prior to being mapped into the lut.
0. 30. The method as recited in claim 27, wherein the additional circuit comprises NAND and NOR gates that are mapped to the cascade logic.
0. 32. The method as recited in claim 31, wherein the mapping constraint includes a timing constraint, a placement constraint, or a size constraint.
0. 33. The method as recited in claim 31, wherein the cascade logic is mapped to follow one or more constraints that are dependent upon connectivity of an architecture as follows:
XOR, XNOR and NOT functions are not mapped on the cascade logic;
either the gate mapped onto the cascade logic or its input said luts have multiple fan-outs, not both;
if the output of the cascade logic is a primary output, then the gate mapped onto it is not an ‘AND’ or ‘NOR’ gate;
if a mapped gate has multiple fan outs then respective outputs are not connected to more than one other gate mapped into a cascade logic element; and
if a mapped gate connects to the output of a multi-fan out lut then an output of the lut is not connected to more than one cascade logic element.
0. 34. The method as recited in claim 31, wherein the cascade logic is mapped to follow one or more conditions that are dependent upon connections of an architecture as follows:
a number of common inputs to a fan-in said luts of the cascade logic is not greater than a number of inputs of the lut;
a gate mapped onto the cascade logic is not of type XOR, XNOR or NOT; and
either the gates mapped on top the cascade logic or its input luts is multi fan, not both.
0. 35. The method as recited in claim 31, further comprising clustering elements to form the circuit based on the available capacity of the selected lut.
0. 36. The method as recited in claim 31, further comprising:
determining whether an additional circuit is able to be mapped into the selected lut; and
if the determination is that the additional circuit is able to be mapped into the selected lut, mapping the additional circuit into the selected lut.
0. 37. The method as recited in claim 36, further comprising if the determination is that the additional circuit is not able to be mapped into the selected lut, determining whether the additional circuit is able to be mapped into cascade logic.
0. 38. The method as recited in claim 37, further comprising if the determination is that the additional circuit is able to mapped into the cascade logic, then mapping the additional circuit into the cascade logic.
0. 39. The method as recited in claim 38, further comprising if the determination is that the additional circuit is not able to be mapped into the cascade logic, then selecting a new said lut and mapping the additional circuit into the new said lut.
0. 41. The method as recited in claim 40, wherein the mapping constraint includes a timing constraint, a placement constraint, or a size constraint.
0. 42. The method as recited in claim 40, wherein the mapping of the cascade logic incorporates one or more of the following constraints that are dependent upon connectivity of an architecture:
XOR, XNOR and NOT functions are not mapped on the cascade logic;
either the gate mapped onto the cascade logic or its input said luts have multiple fan-outs, not both;
if the output of the cascade logic is a primary output, then the gate mapped onto it is not an ‘AND’ or ‘NOR’ gate;
if a mapped gate has multiple fan outs then respective outputs are not connected to more than one other gate mapped into a cascade logic element; and
if a mapped gate connects to the output of a multi-fan out lut then an output of the lut is not connected to more than one cascade logic element.
0. 43. The method as recited in claim 40, wherein the mapping of the cascade logic includes verifying one or more of the following conditions that are dependent upon connections of an architecture:
a number of common inputs to a fan-in said luts of the cascade logic is not greater than a number of inputs of the lut;
a gate mapped onto the cascade logic is not of type XOR, XNOR or NOT; and
either the gates mapped on top the cascade logic or its input luts is multi fan, not both.
0. 44. The method as recited in claim 40, further comprising clustering one or more elements to form the circuit based on the available capacity of the selected lut.
0. 45. The method as recited in claim 40, further comprising:
determining whether an additional circuit is able to be mapped into the selected lut; and
if the determination is that the additional circuit is able to be mapped into the selected lut, mapping the additional circuit into the selected lut.
0. 46. The method as recited in claim 45, further comprising if the determination is that the additional circuit is not able to be mapped into the selected lut, determining whether the additional circuit is able to be mapped into cascade logic.
0. 47. The method as recited in claim 46, further comprising if the determination is that the additional circuit is able to mapped into the cascade logic, then mapping the additional circuit into the cascade logic.
0. 48. The method as recited in claim 47, further comprising if the determination is that the additional circuit is not able to be mapped into the cascade logic, then selecting a new said lut and mapping the additional circuit into the new said lut.
0. 50. The apparatus as recited in claim 49, wherein the mapping constraint includes a timing constraint, a placement constraint, or a size constraint.
0. 51. The apparatus as recited in claim 49, wherein the compiler is operable to incorporate one or more of the following constraints that are dependent upon connectivity of an architecture:
XOR, XNOR and NOT functions are not mapped on the cascade logic;
either the gate mapped onto the cascade logic or its input said luts have multiple fan-outs, not both;
if the output of the cascade logic is a primary output, then the gate mapped onto it is not an ‘AND’ or ‘NOR’ gate;
if a mapped gate has multiple fan outs then respective outputs are not connected to more than one other gate mapped into a cascade logic element; and
if a mapped gate connects to the output of a multi-fan out lut then an output of the lut is not connected to more than one cascade logic element.
0. 52. The apparatus as recited in claim 49, wherein the compiler is operable to verify one or more of the following conditions that are dependent upon connections of an architecture:
a number of common inputs to a fan-in said luts of the cascade logic is not greater than a number of inputs of the lut;
a gate mapped onto the cascade logic is not of type XOR, XNOR or NOT; and
either the gates mapped on top the cascade logic or its input luts is multi fan, not both.
0. 53. The apparatus as recited in claim 49, wherein the compiler is further configured to cluster elements to form the circuit based on the available capacity of the lut.
0. 54. The apparatus as recited in claim 49, wherein the compiler is further configured to:
determine whether an additional circuit is able to be mapped into the lut; and
if the determination is that the additional circuit is able to be mapped into the lut, map the additional circuit into the lut.
0. 55. The apparatus as recited in claim 54, wherein the compiler is further configured such that if the determination is that the additional circuit is not able to be mapped into the lut, determine whether the additional circuit is able to be mapped into cascade logic.
0. 56. The apparatus as recited in claim 55, wherein the compiler is further configured such that if the determination is that the additional circuit is able to be mapped into the cascade logic, the additional circuit is mapped into the cascade logic.
0. 57. The apparatus as recited in claim 56, wherein the compiler is further configured such that if the determination is that the additional circuit is not able to be mapped into the cascade logic, then a new lut is selected and the additional circuit is mapped into the new lut.
0. 58. The apparatus as recited in claim 56, wherein the additional circuit is mapped to the cascade logic prior to being mapped into the lut.
0. 59. The apparatus as recited in claim 56, wherein the additional circuit includes NAND or NOR gates that are mapped to the cascade logic.
0. 60. The apparatus as recited in claim 49, wherein the compiler includes software and hardware on which the software operates.
0. 62. One or more computer-readable storage devices as recited in claim 61, wherein the mapping constraint includes a timing constraint, a placement constraint, or a size constraint.
0. 63. One or more computer-readable storage devices as recited in claim 61, wherein the mapping of the cascade logic incorporates one or more of the following constraints that are dependent upon connectivity of an architecture;
XOR, XNOR and NOT functions are not mapped on the cascade logic;
either the gate mapped onto the cascade logic or its input said luts have multiple fan-outs, not both;
if the output of the cascade logic is a primary output, then the gate mapped onto it is not an ‘AND’ or ‘NOR’ gate;
if a mapped gate has multiple fan outs then respective outputs are not connected to more than one other gate mapped into a cascade logic element; and
if a mapped gate connects to the output of a multi-fan out lut then an output of the lut is not connected to more than one cascade logic element.
0. 64. One or more computer-readable storage devices as recited in claim 61, wherein the mapping of the cascade logic includes verifying one or more of the following conditions that are dependent upon connections of an architecture:
a number of common inputs to a fan-in said lut of the cascade logic is not greater than a number of inputs of the lut;
a gate mapped onto the cascade logic is not of type XOR, XNOR or NOT; and
either the gates mapped on top the cascade logic or its input luts is multi fan, not both.
0. 65. One or more computer-readable storage devices as recited in claim 61, wherein the software is further configured to cluster elements to form the circuit based on the available capacity of the lut.
0. 66. One or more computer-readable storage devices as recited in claim 61, wherein the software is further configured to:
determine whether an additional circuit is able to be mapped into the lut; and
if the determination is that the additional circuit is able to be mapped into the lut, map the additional circuit into the lut.
0. 67. One or more computer-readable storage devices as recited in claim 66, wherein the software is further configured such that if the determination is that the additional circuit is not able to be mapped into the lut, a determination is made as to whether the additional circuit is able to be mapped into a cascade logic.
0. 68. One or more computer-readable storage devices as recited in claim 67, wherein the software is further configured such that if the determination is that the additional circuit is able to mapped into cascade logic, the additional circuit is mapped into cascade logic.
0. 69. One or more computer-readable storage devices as recited in claim 68, wherein the software is further configured such that if the determination is that the additional circuit is not able to be mapped into cascade logic, then a new lut is selected and the additional circuit is mapped into the new lut.
0. 70. One or more computer-readable storage devices as recited in claim 69, wherein the additional circuit is mapped to the cascade logic prior to being mapped into the lut.
0. 71. One or more computer-readable storage devices as recited in claim 70, wherein the additional circuit includes NAND or NOR gates that are mapped to the cascade logic.
0. 72. One or more computer-readable storage devices as recited in claim 61, wherein the software is a compiler.
0. 74. The one or more computer-readable storage devices as recited in claim 73, wherein the mapping the logic gates to one or more look up tables causes a mapped list to be generated.
0. 75. The one or more computer-readable storage devices as recited in claim 74, wherein the mapped list comprises the identified one or more logic gates configured to be extracted.
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This application claims priority from Indian patent application No. 993/Del/2002, filed Sep. 27, 2002, which is incorporated herein by reference.
This invention relates to an improved method and system for mapping an electronic circuit to a programmable logic device (PLD). In particular, the invention relates to the utilization of cascade logic elements while mapping.
Programmable Logic Devices (PLDs) provide the capability of implementing a wide range of electronic circuits using the same physical device. This capability is exploited by configuring the device appropriately for each desired application. The configuring process involves the mapping of the target circuit onto the available resources of the PLD. Programmable Gate Arrays (PGAs) and Field Programmable Gate Arrays (FPGAS) are the most widely used PLDs. The architecture of these devices incorporates Look Up Tables (LUTS) that are configured for desired functionality. The efficiency of mapping algorithms is critical to the effective utilization of PGAs and FPGAs. In LUT-based FPGAs the mapping is implemented on the LUTs.
The conventional LUT-based FPGA mapping algorithms can be divided into two classes. The algorithms in the first class emphasize the minimization of the number of LUTs in the solution. This class includes “Chortle” and “Chortle-crf” algorithms by Francis, based on tree decomposition and bin packing techniques. The algorithms in the second class emphasize the minimization of the delay of the solution. This class includes “Flowmap” by Cong and Y. Ding, which use flow based techniques in mapping with node duplication to reduce the logical depth of the mapped netlist. See Jason Cong and Yuzheng Ding; An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs; IEEE Trans. On Computer Aided Design of Integrated Circuits and Systems CAD, Vol. 13, pp 1-12 Jan. 1994.
A DAG-map (Direct Analysis Graph) method for FPGA technology mapping for delay optimization has been proposed by J. Cong et.al. See Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew Kahng, Peter Trajmar; DAG-Map: Graph Based FPGA Technology Mapping For Delay Optimization; IEEE Design and test of computers, pp 7-20, September 1992. This method utilizes a graph based technology mapping algorithm “DAG-Map”, for delay optimization in lookup-table based FPGA designs. The algorithm carries out technology mapping and delay optimization on the entire Boolean network. As a preprocessing step in “DAG-Map”, a general algorithm transforms an arbitrary n-input network into a two-input network with a corresponding increase in the network depth; Finally, a graph matching based technique which performs area optimization without increasing the network delay is used as a post processing step for “DAG-Map”. This method does not however utilize the cascade elements available with each LUT in the FPGA.
Another optimal technology mapping algorithm for delay optimization in Lookup -Table based FPGA Designs has been proposed by Jason Cong et. al. See Jason Cong and Yuzheng Ding; An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs; IEEE Trans. On Computer Aided Design of Integrated Circuits and Systems CAD, Vol. 13, pp 1-12 January 1994. This method proposes a polynomial time technology-mapping algorithm, called “Flow-Map”, that optimally solves the LUT-based FPGA technology-mapping problem for depth minimization for general Boolean networks. A key step in “Flow-Map” is the computation of a minimum height K-feasible cut in a network, by network flow computation. This algorithm does effectively minimize the number of LUTs by maximizing the volume of each cut and by several post processing operations but it does not utilize the cascade elements with the LUT to further reduce the size of the logic.
A method for On Area/Depth Trade-off in LUT-Based FPGA Technology mapping has been disclosed in reference by Jason Cong and Yuzheng Ding. Jason Cong and Yuzheng Ding; On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping; 30th ACM/IEEE design Automation Conference (DAC), pp. 213-218, 1993. In this method the area and depth trade off in LUT based FPGA technology mapping is proposed by performing a number of depth relaxation operations to obtain a new network with bounded increase in depth and advantageous for subsequent re-mapping for area minimization. The resulting network is then re-mapped to obtain an area-minimized mapping solution. By gradually increasing the depth bound for each design a set of mapping solutions with smooth area and depth trade-off is achieved. For the area minimization step, an optimal algorithm for computing an area-minimum mapping solution without node duplication is developed. However this method also does not talk about the area minimization by utilizing the cascade elements with each LUT.
Another method proposed by Jason Cong and Yuzheng Ding proposes an integrated approach to synthesis and mapping that extends the combinatorial limit set up by the depth-optimal “Flow Map” algorithm. See Jason Cong and Yuzheng Ding; Beyond the Combinatorial Limit in Depth Minimization for LUT-Based FPGA Designs; IEEE/ACM International Conference on Computer Aided Design (IC-CAD), pp. 110-114, November 1993. The new algorithm, “FlowSYN”, uses global combinatorial optimization techniques to guide the Boolean synthesis process during depth minimization. The combinatorial optimization is achieved by computing a series of minimum cuts of fixed heights in a network based on fast network flow computation, and the Boolean optimization is achieved by efficient OBDD-based implementation of functional decomposition. This method also does not utilize cascade elements.
One aspect of this invention is to provide an algorithm for efficiently synthesizing electronic circuits by utilizing cascade elements in LUT-based FPGAs.
Another aspect of the invention is to provide a method and mechanism for maximum utilization of on-chip resources in LUT-based FPGAs hence reducing the area in logic device.
Yet another aspect of the invention is to provide a method for synthesizing a logic circuit with minimum depth in LUT-based FPGAs.
It is yet another aspect of the invention to provide a method for realizing faster LUT-based FPGA implementation.
The described embodiments of this invention provide an improved method for mapping an electronic digital circuit to a Look Up table (LUT) based Programmable Logic Device (PLD). The method operates by selecting an unmapped or partially mapped LUT, and identifying a group of circuit elements for mapping on the selected LUT based on the available capacity of the selected LUT and the mapping constraints. The identified circuit elements are then mapped onto the selected LUT. The identification of circuit elements and mapping is carried out while taking into consideration the Cascade Logic associated with the selected LUT. The process is continued until all the circuit elements have been mapped. The group of circuit elements is mapped to the cascade logic prior to mapping on the LUTs. Conversely, the cascade logic is incorporated only after either all circuit elements have initially been mapped onto LUTs or some circuit elements remain unmapped even after all LUTs have been utilized. The mapping constraints include timing constraints, placement constraints, and size constraints.
The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
The following description is based on the definition of technical terms given below:
Electronic design includes the logical structure of an electronic device such as an integrated circuit. This may be specified either as a behavioral description, as high-level Boolean equations, a circuit schematic or in any other form representing the logical arrangements of a device. It may include different constraints such as timing constraints, placement constraints, or mapping constraints, etc.
A Target hardware device includes the hardware device on which an electronic design is implemented. In context of this invention, a target hardware device typically includes the symmetric array of uncommitted logic elements. The uncommitted elements consist of the LUT, cascade gate, MUXes and flip-flops. These elements are grouped to form another hierarchy called programmable logic blocks, which are again grouped to form a programmable logic device.
A Compiler includes software and hardware on which the software operates for compiling the electronics design. The function of the compiler is to synthesize the netlist and map the netlist (design) to the target device.
Mapping refers to the process of grouping gates from a gate netlist or other hardware independent representation of logic into a logic block. In other words, the logic design may be divided into clusters representing the various logic functions within the design. These clusters are mapped onto the uncommitted logic elements in the programmable logic device during the compilation of the electronic design. The conditions for grouping (mapping) the gates into logic cells is that it should be possible to implement the grouped gates in the logic cell, For example, if a four input LUT is taken as a logic cell then the grouped gates must have less than or equal to four inputs for successful mapping.
Embodiments of the present invention utilize cascade elements during the hardware description language (HDL) compilation and maps the design for programmable integrated circuits during technology mapping.
In the accompanying diagrams (
Another method that can be applied for extracting the cascade chains is:
Since the cascade element is a single universal gate (NAND or NOR) certain constraints have to be observed while mapping gates onto the cascade element. These constraints can be divided into two groups.
The first group of conditions that need to be verified when starting a new cascade chain are:
The second set of conditions that are needed to be verified while the cascade chain is being formed are:
This process of utilizing the cascade elements while mapping a logic circuit onto target architecture is independent of the algorithm used for LUT synthesis. This method provides an optimal solution superior to existing methods without any extra traversal of the gate level netlist.
A programmable logic device programmed in accordance with the described embodiments of the present invention can be included in a variety of electronic systems, such as a computer system or an embedded system.
It will be apparent to those with ordinary skill in the art that the foregoing is merely illustrative and not intended to be exhaustive or limiting, having been presented by way of example only and that various modifications can be made within the scope of the present invention.
Accordingly, this invention is not to be considered limited to the specific examples chosen for purposes of disclosure, but rather to cover all changes and modifications, which do not constitute departures from the permissible scope of the present invention. The invention is therefore not limited by the description contained herein or by the drawings, but only by the claims.
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