In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.
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0. 15. A semiconductor device comprising:
(a) a semiconductor chip having a plurality of semiconductor elements and bonding pads formed on a main surface thereof;
(b) a lead frame having:
a chip mounting portion having one surface for mounting said semiconductor chip;
suspension leads continuously formed with said chip mounting portion; and
a plurality of leads each having an inner lead portion and an outer lead portion continuously formed with said inner lead portion and being arranged at a periphery of said chip mounting portion, said inner lead portions of said plurality of leads being electrically connected with said bonding pads of said semiconductor chip; and
(c) a resin member sealing said semiconductor chip, said chip mounting portion and said inner lead portions of said plurality of leads,
wherein a size of said chip mounting portion is smaller than that of said semiconductor chip, and
wherein said one surface of said chip mounting portion is a surface on which burrs are not formed, during formation of said chip mounting portion,
wherein said chip mounting portion is positioned under a substantially central portion of said semiconductor chip,
wherein said semiconductor chip is fixed to said chip mounting portion by an adhesive,
wherein said semiconductor chip is fixed to a part of each of suspension leads by an adhesive, and
wherein said suspension leads and said chip mounting portion of said lead frame are continuously formed in an area of said semiconductor chip.
0. 21. A semiconductor device comprising:
(a) a semiconductor chip having a plurality of semiconductor elements and bonding pads formed on a main surface thereof;
(b) a lead frame having:
a chip mounting portion for mounting said semiconductor chip;
suspension leads continuously formed with said chip mounting portion; and
a plurality of leads each having an inner lead portion and an outer lead portion continuously formed with said inner lead portion and being arranged at a periphery of said chip mounting portion,
(c) a plurality of bonding wires electrically connecting said inner lead portions of said plurality of leads with said bonding pads of said semiconductor chip respectively, each of said inner lead portions of said plurality of leads having one surface to which a corresponding bonding wire among said plurality of bonding wires is connected; and
(d) a resin member sealing said semiconductor chip, said plurality of bonding wires, said chip mounting portion and said inner lead portions of said plurality of leads,
wherein said one surface of said inner lead portion of each of said plurality of leads is a surface on which burrs are not formed, said burrs being resultant from formation of said plurality of leads,
wherein said chip mounting portion is positioned under a substantially central portion of said semiconductor chip,
wherein said semiconductor chip is fixed to said chip mounting portion by an adhesive,
wherein said semiconductor chip is fixed to a part of each of suspension leads by an adhesive, and
wherein said suspension leads and said chip mounting portion of said lead frame are continuously formed in an area of said semiconductor chip.
0. 26. A semiconductor device comprising:
(a) a semiconductor chip having a plurality of semiconductor elements and bonding pads formed on a main surface thereof;
(b) a lead frame having:
a chip mounting portion having a first surface for mounting said semiconductor chip;
suspension leads continuously formed with said chip mounting portion; and
a plurality of leads each having an inner lead portion and an outer lead portion continuously formed with said inner lead portion and being arranged at a periphery of said chip mounting portion;
(c) a plurality of bonding wires electrically connecting said inner lead portions of said plurality of leads with said bonding pads of said semiconductor chip respectively, each of said inner lead portions of said plurality of leads having a second surface to which a corresponding bonding wire among said plurality of bonding wires is connected; and
(d) a resin member sealing said semiconductor chip, said plurality of bonding wires, said chip mounting portion and said inner lead portions of said plurality of leads,
wherein a size of said chip mounting portion is smaller than that of said semiconductor chip,
wherein said first surface of said chip mounting portion is a surface on which burrs are not formed, and
wherein said second surface of said inner lead portion of each of said plurality of leads is a surface on which said burrs are formed, said burrs resultant from formation of said chip mounting portion and said plurality of leads,
wherein said chip mounting portion is positioned under a substantially central portion of said semiconductor chip,
wherein said semiconductor chip is fixed to said chip mounting portion by an adhesive,
wherein said semiconductor chip is fixed to a part of each of suspension leads by an adhesive, and
wherein said suspension leads and said chip mounting portion of said lead frame are continuously formed in an area of said semiconductor chip.
0. 1. A semiconductor integrated circuit device comprising:
a semiconductor chip having a main surface including semiconductor elements and a plurality of bonding pads;
a leadframe having:
a chip mounting portion for mounting said semiconductor chip;
suspension leads unitarily formed with said chip mounting portion, a width of said chip mounting portion being wider than a width of each of said suspension leads,
a plurality of inner lead portions arranged to surround said semiconductor chip and being electrically connected with said bonding pads by bonding wires, and
a plurality of outer lead portions individually connected with said inner lead portions; and
a resin member sealing said semiconductor chip, said inner lead portions, said chip mounting portion, said suspension leads and said bonding wires;
wherein said chip mounting portion is smaller than said semiconductor chip and is positioned under a substantially central portion of said semiconductor chip, said semiconductor chip is fixed to said chip mounting portion by adhesive, said semiconductor chip is fixed to a part of each of said suspension leads by adhesive which is located under a peripheral portion of said semiconductor chip, and an adhesive region of said chip mounting portion and said semiconductor chip and an adhesive region of each of said suspension leads and said semiconductor chip are separated from each other and wherein said suspension leads and said chip mounting portion of said leadframe are continuously formed in an area of said semiconductor chip.
0. 2. A semiconductor integrated circuit device according to
0. 3. A semiconductor integrated circuit device according to
0. 4. A semiconductor integrated circuit device according to
0. 5. A semiconductor integrated circuit device according to
0. 6. A semiconductor integrated circuit device according to
0. 7. A semiconductor integrated circuit device according to
a plurality of grooves for positioning the semiconductor chip, said grooves each formed on said four suspension leads.
0. 8. A semiconductor integrated circuit device according to
a plurality of projections for positioning the semiconductor chip, said projections each formed on said four suspension leads.
0. 9. A semiconductor integrated circuit device according to
0. 10. A semiconductor integrated circuit device according to
0. 11. A semiconductor integrated circuit device comprising:
a semiconductor chip having a main surface including semiconductor elements and a plurality of bonding pads;
a leadframe having:
a cracking suppression means for mounting said semiconductor chip thereon and for suppressing, during a reflow soldering processing, device cracking, wherein said cracking suppression means is a chip mounting portion which is smaller than said semiconductor chip and which is positioned under a substantially central portion of said semiconductor chip,
suspension leads unitarily formed with said chip mounting portion, a width of said chip mounting portion being wider than a width of each of said suspension leads,
a plurality of inner lead portions arranged to surround said semiconductor chip and being electrically connected with said bonding pads by bonding wires, and
a plurality of outer lead portions individually connected with said inner lead portions; and
a resin member sealing said semiconductor chip, said inner lead portions, said chip mounting portion, said suspension leads and said bonding wires;
wherein said semiconductor chip is fixed to said chip mounting portion by adhesive, said semiconductor chip is fixed to a part of each of said suspension leads by adhesive which is located under a peripheral portion of said semiconductor chip, and an adhesive region of said chip mounting portion and said semiconductor chip and an adhesive region of each of said suspension leads and said semiconductor chip are separated from each other and wherein said suspension leads and said chip mounting portion of said leadframe are continuously formed in an area of said semiconductor chip.
0. 12. A semiconductor integrated circuit device according to
0. 13. A semiconductor integrated circuit device comprising:
a semiconductor chip having a main surface including semiconductor elements and a plurality of bonding pads;
a leadframe having:
a chip mounting portion for mounting said semiconductor chip,
suspension leads unitarily formed with said chip mounting portion, a width of said chip mounting portion being wider than a width of each of said suspension leads,
a plurality of inner lead portions arranged to surround said semiconductor chip and being electrically connected with said bonding pads by bonding wires, and
a plurality of outer lead portions individually connected with said inner lead portions; and
a resin member sealing said semiconductor chip, said inner lead portions, said chip mounting portion, said suspension leads and said bonding wires;
wherein said chip mounting portion is smaller than said semiconductor chip and is positioned under a substantially central portion of said semiconductor chip, said semiconductor chip is fixed to said chip mounting portion by adhesive, said semiconductor chip is fixed to a part of each of said suspension leads by adhesive which is located under a peripheral portion of said semiconductor chip, and an adhesive region of said chip mounting portion and said semiconductor chip and an adhesive region of each of said suspension leads and said semiconductor chip are separated from each other.
0. 14. A semiconductor integrated circuit device comprising:
a semiconductor chip having a main surface including semiconductor elements and a plurality of bonding pads;
a leadframe having:
a cracking suppression means for mounting said semiconductor chip thereon and for suppressing, during a reflow soldering processing, device cracking, wherein said cracking suppression means is a chip mounting portion which is smaller than said semiconductor chip and which is positioned under a substantially central portion of said semiconductor chip,
suspension leads unitarily formed with said chip mounting portion, a width of said chip mounting portion being wider than a width of each of said suspension leads,
a plurality of inner lead portions arranged to surround said semiconductor chip and being electrically connected with said bonding pads by bonding wires, and
a plurality of outer lead portions individually connected with said inner lead portions; and
a resin member sealing said semiconductor chip, said inner lead portions, said chip mounting portion, said suspension leads and said bonding wires;
wherein said semiconductor chip is fixed to said chip mounting portion by adhesive, said semiconductor chip is fixed to a part of each of said suspension leads by adhesive which is located under a peripheral portion of said semiconductor chip, and an adhesive region of said chip mounting portion and said semiconductor chip and an adhesive region of each of said suspension leads and said semiconductor chip are separated from each other.
0. 16. A semiconductor device according to claim 15, wherein said burrs are formed when said lead frame is made by pressing.
0. 17. A semiconductor device according to claim 15, wherein said chip mounting portion has a substantially circular form in a plane view.
0. 18. A semiconductor device according to claim 16, wherein said chip mounting portion has a substantially cross form in a plane view.
0. 19. A semiconductor device according to claim 15, wherein said inner lead portions of said plurality of leads are electrically connected with said bonding pads of said semiconductor chip by a plurality of bonding wires.
0. 20. A semiconductor device according to claim 19, wherein parts of said inner lead portions of said plurality of leads, to which said plurality of bonding wires are connected, are plated.
0. 22. A semiconductor device according to claim 21, wherein a size of said chip mounting portion is smaller than that of said semiconductor chip.
0. 23. A semiconductor device according to claim 21, wherein said burrs are formed when said lead frame is made by pressing.
0. 24. A semiconductor device according to claim 22, wherein said chip mounting portion has a substantially circular form in a plane view.
0. 25. A semiconductor device according to claim 22, wherein said chip mounting portion has a substantially cross form in a plane view.
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Face face being directed upward so that the burrs 11 may be left on the back opposed to the chip mounting face.
On the other hand, the inner lead portions 5a are reluctant, if the burrs 11 are left at the lower side at a wire bonding step, to have wires bonded thereto so that the bonding is defective. When the inner lead portions 5a are to be pressed, the pressing is carried out downward with the bonding face being directed downward, to leave the burrs 11 on the wire bonding face.
Next, as shown in
Next, the leadframe 1 is subjected to a down-setting step. This down-setting step is a treatment to lower the height of the die pad 3 than that of the leads 5, as viewed horizontally, by bending the midway portions (as indicated at S in
Thanks to the aforementioned down-setting treatment, the resin thickness is substantially equalized at the upper face side of the semiconductor chip 2 and at the lower face side of the die pad 3 when a package is to be molded by fitting up a mold with the leadframe 1 having the semiconductor chip 2.
Next, the tape 6 is adhered to both the midway portions (i.e., wider portions) of the suspension leads 4 for supporting the die pad 3 and the inner lead portions 5a.
The adhesion of the tape 6 is carried out, as shown in
For example, the tape 6 is constructed such that an adhesive 6b of an acrylic resin is applied to a thickness of about 0.02 mm onto one side of a film 6a of a polyimide resin having an external size of about 18.5 mm×18.5 mm, a width of about 1.5 mm and a thickness of about 0.05 mm.
When the leadframe 1 having the semiconductor chip 2 is attached to the mold to form the package body, the die pad 3 can be prevented, by adhering the tape 6, i.e., the insulating film to the midway portions of the suspension leads 4 to fix the die pad 3, from being fluctuated by the flow of the molten resin. As a result, the flow velocities of the molten resin can be equalized at the upper face side of the semiconductor chip 2 and the lower face side of the die pad 3 to prevent the molding defect such as through voids.
Since the leadframe 1 of the present embodiment thus achieved is constructed such that the area of the chip mounting face of the die pad 3 is smaller than that of either the principal face of the semiconductor chip 2 to be mounted thereon or the back face opposed to the aforementioned principal face, it can mount semiconductor chips having different external sizes thereon. By cutting the leading ends of the leads 5 to shorten them, moreover, it is possible to mount a semiconductor chip 2a or 2b having a larger area.
Thus, in case the die pad 3 has a diameter of about 3 mm, for example, it is possible to mount a variety of semiconductor chips having external sizes ranging from about 5 mm×5 mm to about 15 mm×15 mm. The cutting step of the leads 5 is carried out by means of a press but with the wire bonding region being directed downward, so as to prevent the plated Ag layer from peeling from the wire bonding regions 32. As shown in
Next, one embodiment of a process for fabricating a QFP by using the aforementioned leadframe 1 will be described with reference to
First of all, as shown in
The application of the adhesive 15 is carried out, as shown in
Since the die pad 3 of the aforementioned leadframe 1 has a small area, the adhesive 15 may be applied to one point of the principal face of the die pad 3. This application results in such an advantage over the existing leadframe having a larger die pad that the structure of the nozzle 18 used may be simpler and that the application time of the adhesive 15 may be shorter.
As shown in
Since a sufficient adhesion strength is thus achieved, it is possible to prevent a disadvantage that the semiconductor chip 2 rotationally goes out of position over the die pad 3. Thanks to the formation of the small pads (i.e., adhesion-applied portions) 20, moreover, the rigidity of the suspension leads 4 can be substantially enhanced to prevent the die pad 3 from being fluctuated by the flow of the molten resin when the package is to be prepared by fitting up the mold with the leadframe 1 having the semiconductor chip 2 mounted thereon.
The aforementioned small pads 20 may be formed midway of the individual suspension leads 4, namely, between the die pads 3 and the midway portions S, as shown in
Next, as shown in
When the semiconductor chip 2 is to be positioned over the die pad 3, the locations of the V-shaped grooves 22 are detected from above the leadframe 1 by means of a (not-shown) camera, as shown in
As shown in
Next, as shown in
Next, as shown in
As shown in
Since the heat stage 27 is formed in its principal face with the aforementioned relief grooves 28, either the leadframe 1 (as shown in
Next, the aforementioned leadframe 1 is fitted in the mold, and the semiconductor chip 2, the die pads 3, the inner lead portions 5a and the wires 26 are molded of an epoxy resin, as shown in
Since the QFP 30 thus fabricated by using the leadframe 1 of the present embodiment has its die pad made smaller than the semiconductor chip 2 mounted thereon, the peripheral portion of the semiconductor chip 2 has its back contacting closely to the sealing resin.
Since the adhesion of the interface between the sealing resin and the die pad 3 is sufficient, the interface can be suppressed from peeling even if it should be expanded by the moisture having invaded and been heated at the fellow soldering step. Thus, it is possible to provide the QFP 30 having an improved reflow cracking resistance.
Moreover, since the leadframe 1 of the present embodiment can mount a variety of semiconductor chips 2 of different external sizes, the troubles of preparing a leadframe for each of the semiconductor chips having different external sizes are eliminated. As a result, the leadframe 1 can be standardized to reduce its production cost thereby to provide the QFP 30 at a reasonable cost.
Still moreover, since the leadframe 1 of the present embodiment reduces the external size of the die pad 3, the amount of the adhesive 15 to be used for mounting the semiconductor chip 2 on the die pad 3 can also be reduced to provide the QFP 30 at a more reasonable cost.
Although our invention has been specifically described in connection with the embodiments thereof, it should not be limited to the foregoing embodiments but can naturally be modified in various manners without departing from the gist thereof.
The shape of the die pad should not be limited to the circle but may be another such as a rectangle, if the adhering strength of the chip to the die pad and the minimum application region of the adhesive are retained. As shown in
As shown in
In the foregoing embodiments, the present invention has been described in case it is applied to the leadframe for fabricating the QFP, but can also be applied generally to the leadframes to be used for assembling the surface-mounting LSI package. The present invention can also be applied to a leadframe to be used for fabricating a pin-inserted LSI package such as DIP (i.e., Dual In-line Package).
The effects to be achieved by the representatives of the invention disclosed herein will be briefly summarized in the following:
(1) According to the present invention, it is possible to provide an LSI package having an improved reflow cracking resistance; and
(2) According to the present invention, a leadframe matching the flexible manufacturing system of the LSI package can be provided to reduce the production cost of the LSI package.
Tsubosaki, Kunihiro, Kawai, Sueo, Suzuki, Hiromichi, Miyaki, Yoshinori, Naito, Takahiro, Suzuki, Kazunari, Kajihara, Yujiro
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Nov 16 2001 | Hitachi ULSI Systems Co., Ltd. | (assignment on the face of the patent) | / | |||
Sep 12 2003 | Hitachi, LTD | Renesas Technology Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 014570 | /0380 | |
Apr 01 2010 | Renesas Technology Corp | Renesas Electronics Corporation | MERGER SEE DOCUMENT FOR DETAILS | 024736 | /0381 |
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