Systems and methods for load detection and correction in a digital amplifier

Abstract

Systems and methods for detecting the impedance of an output load coupled to a digital amplifier and compensating for changes in the response of the amplifier. One embodiment of the invention is implemented in a Class D pulse width modulated (PWM) amplifier. In this embodiment, a digital PCM test signal is generated. This test signal is processed by the amplifier to produce a corresponding analog audio output signal that is used to drive a speaker. A sense resistor placed in series with the speaker is used to generate a test voltage that is compared to a reference voltage. When the test voltage reaches the reference voltage, the current through the sense resistor (hence the speaker) is at a known level, so the value of the digital test signal is noted. The impedance of the speaker is then determined from the test signal value and the speaker current.

Description

RELATED APPLICATIONS

This application claims priority to U.S. Patent application Ser. No. 10/805,741, entitled “Systems And Methods For Automatically Adjusting Channel Timing,” by Taylor, et al., filed Mar. 22, 2004, which claims priority to: U.S. Provisional Patent Application No. 60/456,421, entitled “Output Device Switch Timing Correction,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,414, entitled “Adaptive Anti-Clipping Protection,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,430, entitled “Frequency Response Correction,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,429, entitled “High-Efficiency, High-Performance Sample Rate Converter,” by Anderson, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,422, entitled “Output Filter, Phase/Timing Correction,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,428, entitled “Output Filter Speaker/Load Compensation,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,420, entitled “Output Stage Channel Timing Calibration,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,427, entitled “Intelligent Over-Current, Over-Load Protection,” by Hand, et al., filed Mar. 21, 2003; each of which is fully incorporated by reference as if set forth herein in its entirety.

BACKGROUND

1. Field of the Invention

The invention relates generally to audio amplification systems, and more particularly to systems and methods for detecting the impedance of an output load coupled to a digital amplifier and compensating for changes in the frequency response of the amplifier.

2. Related Art

Pulse Width Modulation (POMPOMDIPDIP DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DIP DSP core, or any other such configuration.

The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in software or firmware modules executed by a processor, or in a combination thereof. A software product may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The benefits and advantages which may be provided by the present invention have been described above with regard to specific embodiments. These benefits and advantages, and any elements or limitations that may cause them to occur or to become more pronounced are not to be construed as critical, required, or essential features of any or all of the claims. As used herein, the terms “comprises,” “comprising,” or any other variations thereof, are intended to be interpreted as non-exclusively including the elements or limitations which follow those terms. Accordingly, a system, method, or other embodiment that comprises a set of elements is not limited to only those elements, and may include other elements not expressly listed or inherent to the claimed embodiment.

While the present invention has been described with reference to particular embodiments, it should be understood that the embodiments are illustrative and that the scope of the invention is not limited to these embodiments. Many variations, modifications, additions and improvements to the embodiments described above are possible. It is contemplated that these variations, modifications, additions and improvements fall within the scope of the invention as detailed within the following claims.

Claims

1. A method implemented in a digital amplifier comprising:

(a) generating a digital test signal;

(b) converting the digital test signal to an analog signal;

(c) driving a load with the analog signal;

(d) detecting a threshold level of current through the load;

(e) identifying a value of the digital test signal that generated the threshold level of current through the load; and

(f) calculating an impedance of the load based on the threshold level of current through the load and the corresponding value of the digital test signal.

2. The method of claim 1, wherein detecting a threshold level of current through the load comprises comparing a measured analog signal corresponding to the level of current through the load to an analog reference signal corresponding to the threshold level of current and generating a binary signal that indicates whether the measured analog signal exceeds the analog reference signal.

3. The method of claim 1, further comprising repeating (a)-(f) with multiple digital test signals having different frequencies and one or more threshold levels of current through the load, and calculating an impedance profile of the load based on the threshold levels of current through the load and the corresponding values of the digital test signals.

4. The method of claim 3, further comprising comparing the calculated impedance profile of the load to a library of impedance profiles and selecting one of the impedance profiles in the library that matches the calculated impedance profile of the load.

5. The method of claim 4, further comprising implementing a set of operating parameters in the digital amplifier that is associated with the selected one of the impedance profiles in the library.

6. The method of claim 1, wherein the digital test signal comprises a pulse code modulated (PCM) signal and converting the digital test signal to the analog signal comprises converting the PCM signal to a pulse width modulated (PWM) signal and converting the PWM signal to the analog signal.

7. The method of claim 6, wherein detecting the threshold level of current through the load comprises comparing a voltage across a sense resistor that is in series with the load to a reference voltage that is equal to a resistance of the sense resistor times the threshold level of current.

8. The method of claim 7, further comprising asserting a binary signal when the voltage across the sense resistor exceeds the reference voltage.

9. The method of claim 7, further comprising asserting an interrupt when the voltage across the sense resistor exceeds the reference voltage.

10. A method comprising:

in a test mode,

generating a digital test signal,

converting the digital test signal to an analog test signal,

applying the analog test signal across a load and a sense resistor,

comparing a voltage across the sense resistor to a first reference voltage, wherein the first reference voltage is equal to a resistance of the sense resistor times a first threshold level of current,

generating a binary signal indicating whether the voltage across the sense resistor exceeds the first reference voltage,

identifying a value of the digital test signal that causes the binary signal to transition between high and low states, and

calculating an impedance of the load based on the first threshold level of current and the identified value of the digital test signal;

in an operational mode,

converting a digital audio digital test signal to an analog audio signal,

applying the analog signal across a load and a sense resistor,

comparing a voltage across the sense resistor to a second reference voltage, wherein the second reference voltage is equal to a resistance of the sense resistor times a second threshold level of current which is higher than the first threshold level of current,

generating a binary signal indicating whether the voltage across the sense resistor exceeds the second reference voltage, and

taking a protective action to limit the load current when the binary signal indicates that the voltage across the sense resistor exceeds the second reference voltage.

11. The method of claim 10, wherein the protective action comprises at least temporarily shutting down the amplifier.

12. A digital amplifier comprising:

a digital test signal generator configured to generate a digital test signal;

an engine configured to convert the digital test signal to an analog signal;

an output stage configured to receive the analog signal and to drive a load and a sense resistor in series with the load with the analog signal;

a reference voltage generator configured to generate a reference voltage equal to a resistance of the sense resistor times a threshold level of current;

a comparator configured to compare a voltage across the sense resistor to the reference voltage and to generate a binary signal indicating whether the voltage across the sense resistor exceeds the reference voltage;

a processor configured to identify a value of the digital test signal corresponding to a transition in the binary signal and to calculate an impedance of the load based on the threshold level of current and the value of the digital test signal corresponding to the transition in the binary signal.

13. The digital amplifier of claim 12, wherein the voltage across the sense resistor and the reference voltage comprise analog signals.

14. The digital amplifier of claim 12, wherein the digital test signal generator is configured to generate digital test signals of different frequencies for multiple tests; and wherein the processor is configured to identify values of each digital test signal corresponding to transitions in the binary signal and to calculate impedances of the load for each test signal frequency based on the threshold level of current and the value of each digital test signal corresponding to transitions in the binary signal.

15. The digital amplifier of claim 14, wherein the processor is configured to compare the calculated impedances for each test signal frequency to a library of impedance profiles and to select one of the impedance profiles in the library that matches the calculated impedances of the load.

16. The digital amplifier of claim 15, wherein the processor is further configured to implement a set of operating parameters in the digital amplifier that is associated with the selected one of the impedance profiles in the library.

17. The digital amplifier of claim 12, wherein the digital test signal generator is configured to generate a pulse code modulated (PCM) signal and the engine configured to convert the digital test signal to an analog signal comprises a pulse width modulated (PWM) engine.

18. The digital amplifier of claim 12, wherein the processor is configured to assert an interrupt when the binary signal transitions from low to high.

19. The digital amplifier of claim 18 12, further comprising an accumulator configured to receive the binary signal and to assert an output signal to the processor only if the binary signal is asserted for a predetermined interval.

20. The digital amplifier of claim 12, wherein:

in a test mode,

the reference voltage generator is configured to generate a first reference voltage equal to a resistance of the sense resistor times a first threshold level of current below a maximum current level, and the processor is configured to calculate the impedance of the load based on the threshold level of current and the value of the digital test signal corresponding to the transition in the binary signal; and

in an operational mode,

the reference voltage generator is configured to generate a second reference voltage equal to a resistance of the sense resistor times a second threshold level of current which is higher than the first threshold level of current; and

the processor is configured to take action to limit the current through the load when the binary signal is asserted.

21. A method implemented in a digital amplifier comprising:

(a) generating a digital test signal having a corresponding value;

(b) converting the digital test signal to an analog test signal that drives a load;

(c) sensing a test voltage indicative of a current that flows through the load in response to the analog test signal driving the load;

(d) adjusting the value of the digital test signal, to thereby adjust an amplitude of the analog test signal driving the load, until the sensed test voltage reaches a reference voltage; and

(e) calculating an impedance of the load in dependence on the value of the digital test signal that causes the sensed test voltage to reach the reference voltage.

22. The method of claim 21, further comprising:

(f) modifying a response of the digital amplifier in dependence of the calculated impedance of the load.

23. The method of claim 22, wherein step (f) includes modifying the response of the digital amplifier to compensate for high-frequency peaking and/or drooping.

24. The method of claim 21, wherein:

the analog test signal that drives the load has a corresponding frequency; and

steps (a), (b), (c), (d) and (e) are performed for each of a plurality of different frequencies of the analog test signal to thereby calculate an impedance profile of the load.

25. The method of claim 24, further comprising:

(f) modifying a response of the digital amplifier in dependence of the calculated impedance profile of the load.

26. The method of claim 21, wherein to reduce effects of variability in the digital amplifier:

step (e) comprises calculating the impedance of the load in dependence on the value of the digital test signal that causes the sensed test voltage to reach the reference voltage for at least a predetermined interval.

27. The method of claim 21, wherein:

the reference voltage is generated in dependence on a threshold level of current; and

the calculating the impedance of the load at step (e) is also in dependence on the threshold level of current.

28. The method of claim 27, further comprising generating the reference voltage in dependence on the threshold level of current.

29. The method of claim 21, wherein:

the load comprises a speaker; and

the analog test signal comprises an analog audio test signal that drives the speaker.

30. The method of claim 29, wherein:

the digital test signal generated at step (a) comprises a digital pulse code modulated (PCM) audio test signal; and

at step (b) the digital PCM test signal is converted to an analog pulse width modulated (PWM) audio test signal that drives the speaker.

31. A digital amplifier comprising:

circuitry configured to convert a digital test signal to an analog test signal that drives a load;

further circuitry configured to sense a test voltage indicative of a current that flows through the load in response to the analog test signal driving the load; and

a processor configured to

adjust a value of the digital test signal, to thereby adjust an amplitude of the analog test signal driving the load, until the sensed test voltage reaches a reference voltage; and

calculate an impedance of the load in dependence on the value of the digital test signal that causes the sensed test voltage to reach the reference voltage.

32. The digital amplifier of claim 31, wherein the processor is also configured to modify a response of the digital amplifier in dependence of the calculated impedance of the load.

33. The digital amplifier of claim 31, further comprising:

a digital test signal generator that generates the digital test signal for each of a plurality of different frequencies, so that the load is driven by the analog test signal for each of the plurality of different frequencies;

wherein the processor is configured to calculated an impedance profile of the load, in dependence of the values of the digital test signal that cause the sensed test voltage to reach the reference voltage for the plurality of different frequencies; and

wherein the digital signal generator can be implemented by the processor.

34. The digital amplifier of claim 33, wherein the processor is also configured to modify a response of the digital amplifier in dependence of the calculated impedance profile of the load.

35. The digital amplifier of claim 31, wherein to reduce effects of variability in the digital amplifier, the processor calculates the impedance of the load in dependence on the value of the digital test signal that causes the sensed test voltage to reach the reference voltage for at least a predetermined interval.