systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.
|
0. 19. A method for converting a digital input data stream to a specified output sample rate (Fout), the method comprising:
estimating an input sample rate (Fin) of the input data stream based on frame sync signals associated with the input data stream;
receiving, at an input fifo, samples of the input data stream;
convolving the samples of the input data stream, that are output from the input fifo, with filter coefficients; and
receiving, at an output fifo, samples that have been convolved with the filter coefficients, wherein samples can be read out of the output fifo at the output sample rate (Fout);
managing a flow of samples through the input fifo and the output fifo; and
adjusting the estimated input sample rate (Fin) based on the flow of samples through the input fifo and output fifo.
0. 13. A sample rate converter that converts a digital input data stream to a specified output sample rate (Fout), the sample rate converter comprising:
a sample rate estimation path configured to receive frame sync signals associated with the input data stream and to estimate an input sample rate (Fin) of the input data stream;
an audio data path including
an input fifo configured to receive samples of the input data stream;
a convolution unit configured to receive an output of the input fifo and to convolve the samples of the input data stream with filter coefficients; and
an output fifo configured to receive an output of the convolution unit, wherein samples can be read out of the output fifo at the output sample rate (Fout); and
a fifo management unit, coupled to the input fifo and the output fifo, and configured to provide feedback to at least one component of the rate estimation path.
1. A sample rate converter comprising:
a plurality of sample rate converter components, including:
a rate estimator;
a low pass filter, wherein an output of the rate estimator is passed through the low pass filter;
a phase selection unit, wherein an output of the low pass filter is provided to the phase selection unit;
a polyphase coefficient interpolator, wherein a set of interpolated polyphase filter coefficients is generated by the polyphase coefficient interpolator based upon an output of the phase selection unit;
a convolution unit configured to convolve the interpolated polyphase filter coefficients with a corresponding sample samples of an input data stream;
an input fifo configured to receive samples of the input data stream and to provide the samples of the input data stream to the convolution unit;
an output fifo configured to receive samples of an output data stream from the convolution unit; and
a fifo management unit coupled to the input and output FIFOs and configured to provide feedback to the low pass filter;
wherein a first portion of the components comprise hardware components; and
wherein a second portion of the components comprise software components.
0. 22. A digital audio amplification system, comprising:
a sample rate converter that converts a digital input data stream from an input sample rate (Fin) to a specified output sample rate (Fout);
an audio effects subsystem that receives the digital data stream having the specified output sample rate (Fout), from the sample rate converter, and performs processing on the digital data stream to produce a processed digital data stream;
a pulse width modulator that converts the processed digital data stream to a pulse width modulated signal; and
an output stage that receives the pulse width modulated signal and outputs a signal that can be used to drive a load;
wherein the sample rate converter comprises
a sample rate estimation path configured to receive frame sync signals associated with the input data stream and to estimate the input sample rate (Fin) of the input data stream;
an audio data path including
an input fifo configured to receive samples of the input data stream;
a convolution unit configured to receive an output of the input fifo and to convolve the samples of the input data stream with filter coefficients; and
an output fifo configured to receive an output of the convolution unit, wherein samples can be read out of the output fifo at the output sample rate (Fout); and
a fifo management unit, coupled to the input fifo and the output fifo, and configured to provide feedback to at least one component of the rate estimation path.
2. The sample rate converter of
3. The sample rate converter of
4. The sample rate converter of
5. The sample rate converter of
6. The sample rate converter of
7. The sample rate converter of
8. The sample rate converter of
9. The sample rate converter of
10. The sample rate converter of
11. The sample rate converter of
12. The sample rate converter of
0. 14. The sample rate converter of claim 13, wherein the feedback is used to prevent overflow and underflow of the input fifo and the output fifo.
0. 15. The sample rate converter of claim 13, wherein:
the rate estimation path includes a low pass filter that filters counts used to estimate the input sample rate (Fin) of the input data stream; and
the feedback is provided to the low pass filter.
0. 16. The sample rate converter of claim 13, wherein the filter coefficients comprise interpolated polyphase filter coefficients.
0. 17. The sample rate converter of claim 13, wherein the rate estimation path includes:
a rate estimator, a low pass filter and a polyphase coefficient interpolator, which are implemented in hardware; and
a phase selection unit, which is implemented in software.
0. 18. The sample rate converter of claim 17, wherein:
the convolution unit, of the audio data path, is implemented in software; and
the fifo management unit is implemented in software.
0. 20. The method of claim 19, wherein the estimating includes:
producing a count based on the frame sync signals associated with the input data stream;
filtering the count; and
estimating the input sample rate (Fin) of the input data stream based on the filtered count.
0. 21. The method of claim 20, wherein the adjusting the estimating comprises adjusting the filtering of the count.
|
|||||||||||||||||||||||||||
This application claims priority to: U.S. Provisional Patent Application No. 60/469,761, entitled “Systems and Methods for Implementing a Sample Rate Converter Using Hardware and Software to Maximize Speed and Flexibility,” by Andersen, et al., filed May 12, 2003; U.S. Provisional Patent Application No. 60/456,414, entitled “Adaptive Anti-Clipping Protection,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,430, entitled “Frequency Response Correction,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,429, entitled “High-Efficiency, High-Performance Sample Rate Converter,” by Andersen, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,421, entitled “Output Device Switch Timing Correction,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,422, entitled “Output Filter, Phase/Timing Correction,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,428, entitled “Output Filter Speaker/Load Compensation,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,420, entitled “Output Stage Channel Timing Calibration,” by Taylor, et al., filed Mar. 21, 2003; U.S. Provisional Patent Application No. 60/456,427, entitled “Intelligent Over-Current, Over-Load Protection,” by Hand, et al., filed Mar. 21, 2003; each of which is fully incorporated by reference as if set forth herein in its entirety.
1. Field of the Invention
The invention relates generally to audio amplification systems, and more particularly to systems and methods for converting input data streams having a first sample rate to output data streams having a second data rate.
2. Related Art
Pulse Width Modulation (PWM) or Class D signal amplification technology has existed for a number of years. PWM technology has become more popular with the proliferation of Switched Mode Power Supplies (SMPS). Since this technology emerged, there has been an increased interest in applying PWM techniques in signal amplification applications as a result of the significant efficiency improvement that can be realized through the use of Class D power output topology instead of the legacy (linear Class AB) power output topology.
Early attempts to develop signal amplification applications utilized the same approach to amplification that was being used in the early SMPS. More particularly, these attempts utilized analog modulation schemes that resulted in very low performance applications. These applications were very complex and costly to implement. Consequently, these solutions were not widely accepted. Prior art analog implementations of Class D technology have therefore been unable to displace legacy Class AB amplifiers in mainstream amplifier applications.
Recently, digital PWM modulation schemes have surfaced. These schemes use Sigma-Delta modulation techniques to generate the PWM signals used in the newer digital Class D implementations. These digital PWM schemes, however, did little to offset the major barriers to integration of PWM modulators into the total amplifier solution. Class D technology has therefore continued to be unable to displace legacy Class AB amplifiers in mainstream applications.
There are a number of problems with existing digital PWM modulation schemes. One of the problems is that the performance and quality characteristics of the remainder of the signal processing system vary with the application. The exact implementation of the total system solution and the end-user application is not deterministic. As a result, implementation details cannot be accounted for apriori. Because existing technologies require application-specific solutions, they typically are not flexible, scalable or transportable to other applications. Consequently, these technologies generally are not applicable to mainstream systems.
One area in particular where existing digital PWM modulation schemes do not meet mainstream system requirements is in the processing of digital input data streams having various sample rates. These input data streams may have different sample rates, depending upon the type of device that provides the data, as well as the particular design of the device. The input data streams may also use different clock sources that may have slightly different rates or may drift with respect to one another. Existing technologies require a single input sample rate, or multiple fixed, known input rates, and cannot adapt to the different rates at which devices may provide the input data.
Another problem with prior art systems is that, because they do not have a sample rate converter that can generate a local clock signal, they typically regenerate the PWM clock signal from the input data. This regenerated clock signal cannot support the higher performance that is possible with a locally generated clock signal.
One or more of the problems outlined above may be solved by the various embodiments of the invention. Broadly speaking, the invention comprises systems and methods for converting a digital input data stream from a first sample rate to a second sample rate using a combination of hardware and software components. In one embodiment, the conversion from the first sample rate to the second sample rate is performed in a sample rate converter for a digital audio system. The sample rate converter has multiple components, some of which are implemented in hardware and some of which are implemented in software. Whether each component is implemented in hardware or software depends upon the performance requirements of the component. Components that achieve better performance in software are implemented in software, while those that achieve better performance in hardware are implemented in hardware. It should be noted that performance may be improved, not only in audio performance measures, but also in computational complexity, the “fit” of components onto the software engine, and in other areas.
One embodiment comprises a sample rate converter system including a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to increase phase resolution by interpolating the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. As indicated above, these system components include both hardware and software components. In one embodiment, the system includes two or more channels, each of which is capable of receiving an input data stream having a different, variable sample rate than the data streams received by the other channels. In one embodiment, the different channels share one or more common components with the other channels. In one embodiment, the sample rate converter system is coupled to an audio amplification system and is configured to convert input data streams to a common output sample rate for processing by amplifier components such as an audio effects unit or a pulse width modulator.
Another embodiment comprises a method which includes the steps of receiving an input data stream having an input sample rate and processing the input data stream using a combination of hardware and software components to produce an output data stream having a output sample rate that is different from the input sample rate. In one embodiment, the processing comprises estimating the input sample rate, selecting a phase for interpolation of a set of polyphase filter coefficients, interpolating the set of polyphase filter coefficients, convolving the set of interpolated polyphase filter coefficients with samples of the input data stream, and providing resulting samples of the output data stream. In one embodiment, the method comprises receiving and processing two or more input data streams having independently variable sample rates on separate channels to produce corresponding output data streams having a common output sample rate. At least a portion of the processing of the different data streams in the different channels is performed in common with or software components.
Numerous additional embodiments are also possible.
The use of both hardware and software components may provide a number of advantages over prior art systems. One potential advantage is that components for which processing speed is important may be implemented in dedicated hardware to maximize their performance, while other components for which flexibility is more important can be implemented in software. Another potential advantage is that hardware and/or software components may be common to (shared by) multiple channels, thereby reducing the cost and complexity of the system, while retaining the speed and flexibility of the system. Another potential advantage is that each of the channels may be able to handle input sample rates which are variable and which are independent of the sample rates of data streams on other channels. Another potential advantage is that the generation of a local, high-performance clock signal enables the PWM output to meet higher performance standards than if the clock signal must be regenerated from the input data.
Other objects and advantages of the invention may become apparent upon reading the following detailed description and upon reference to the accompanying drawings.
While the invention is subject to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and the accompanying detailed description. It should be understood, however, that the drawings and detailed description are not intended to limit the invention to the particular embodiment which is described. This disclosure is instead intended to cover all modifications, equivalents and alternatives falling within the scope of the present invention as defined by the appended claims.
One or more embodiments of the invention are described below. It should be noted that these and any other embodiments described below are exemplary and are intended to be illustrative of the invention rather than limiting.
As described herein, various embodiments of the invention comprise systems and methods for converting a digital input data stream from a first sample rate to a second sample rate using a combination of hardware and software components. As used herein, “hardware” refers to dedicated, fixed-function logic. “Software,” on the other hand, is used to refer to programmable logic that is controlled by an algorithm defined by a programmer, or utilizing generic programmable blocks under software, as in a digital signal processor (DSP) arithmetic logic unit (ALU) or memory.
In one embodiment, the conversion from the first sample rate to the second sample rate is performed in a sample rate converter for a digital audio system. The sample rate converter has multiple components, some of which are implemented in hardware and some of which are implemented in software. Whether each component is implemented in hardware or software depends upon the performance requirements of the component. Components that achieve better performance in software are implemented in software, while those that achieve better performance in hardware are implemented in hardware. As noted above, performance may measured in terms of the audio performance, computational complexity, etc., using such metrics as the number of processor cycles required for operations, device size, implementation cost, flexibility, power consumption and the like.
The use of both hardware and software components may provide a number of advantages over prior art systems which are conventionally implemented either entirely in hardware or entirely in software. For example, components for which processing speed is important may be implemented in dedicated hardware to maximize their performance. For other components, processing speed may be less important than flexibility. These components may be implemented in software in order to provide the desired flexibility. Another advantage of the use of both hardware and software components is that some of the components may be used for multiple channels. By sharing some of the components between channels, the cost and complexity of the system may be reduced, while retaining the speed and flexibility of the system.
A preferred embodiment of the invention is implemented in an audio amplification system. As noted above, pulse width modulation (PWM) technology has recently been applied in audio amplification systems, but has suffered from the drawbacks of conventional methodologies. These methodologies employ analog modulation schemes which are complex and costly, and which provide relatively poor performance. The present systems and methods are instead implemented in digital modulation schemes and employ methodologies which overcome some of the problems that existed in the prior art.
Referring to
In the present systems and methods, sample rate converter 110 converts the input data stream from the sample rate at which it was received to a predetermined internal rate which is used within system 100. In one embodiment, this internal sample rate is 100 kHz. Thus, if data is received at a sample rate of 50 kHz, sample rate converter 110 will re-sample the data to produce a corresponding internal data stream at a sample rate of 100 kHz. This internal data stream is then provided to an audio effects subsystem 120. Audio effects subsystem 120 performs any desired processing on the internal data stream and provides the resulting processed data stream to PWM modulator 130.
The data stream received by PWM modulator 130 represents a pulse code modulated signal. PWM modulator 130 converts this data stream to a pulse width modulated signal. The pulse width modulated signal is then provided to output stage 140. In output stage 140 amplifies the pulse width modulated signal and may perform some filtering or further processing of the amplified signal. The resulting signal is then output to a speaker system 150, which converts the electrical signal to an audible signal which can be heard by a listener.
The present disclosure focuses on the sample rate converter in the audio system described above. As explained above, the purpose of the sample rate converter is to receive an input data stream which is sampled at a first rate, and to generate an output data stream which is sampled at a second rate. While the audio signal which is represented by the data stream remains essentially unchanged (at least in some embodiments), the sampling rate is changed to conform to the requirements of the audio system so that it can be processed by the system.
Referring to
The up-sampled data stream is low-pass filtered and then decimated to reduce the sample rate from the intermediate rate to the desired output rate. After down-sampling, the sample rate is Fout=(M/N)×Fin. The down-sampling, or decimation, of the data stream is typically accomplished by dropping samples from the intermediate data stream. For example, if the intermediate data stream is sampled at 200 kHz and the desired output sample rate is 100 kHz, every other sample will be dropped.
Ideally, M and N are integers. If M is an integer, the up-sampling of the input data stream comprises inserting M−1 new samples, evenly spaced between each of the original samples. Then, if N is an integer, the down-sampling of the intermediate data stream comprises taking only every Nth sample and dropping the rest. This is illustrated in
One of the problems with a straightforward implementation of the up-sampling and down-sampling of the input data stream is that, in order to make M and N integers, and in order to maintain the desired resolution, M and N typically must be very large numbers. Consider the example of
Another problem with the interpolation-and-decimation methodology is that it may be difficult to handle variations in the sample rates of the received data streams. In typical audio systems, each device or component may generate its own clock signal upon which the corresponding sample rate is based. Even if the clock signals for two components are intended to be identical, however, the clock signals are not synchronized and may have slight variations. As a result of the differences in clock signals, data may be dropped, or buffers may overflow, resulting in errors. The present sample rate converter is designed to handle these differences.
It should be noted that audio systems may also include various different types of audio sources. For example, the audio signal may be generated by a CD player, MP3 player, digital audio tape or the like. These devices may be configured to generate audio signals at different sample rates. For instance, a CD player may provide an output signal that has a 44.1 kHz sample rate, while a digital audio tape player may generate an output signal at a 32 kHz sample rate. The present systems and methods enable the sample rate converter to accommodate multiple different sample rates in the input data stream. Moreover, the sample rate converter is capable of independently adjusting each channel to accommodate a different input sample rate. By comparison, prior art systems can only accommodate different sample rates on different channels if the two sample rates are known.
The accommodation of different sample rates, and variations between rates that are nominally the same, may be achieved through the use of a polyphase filter. The polyphase filter performs the functions of both interpolator 210 and decimator 220. The polyphase filter performs these functions by interpolating the input data stream in a manner which does not require that the data stream be up-sampled by an integer factor or down-sampled by an integer factor.
The interpolator and the decimator described above are typically implemented as (FIR-type) filters. The polyphase filter is obviously also a filter, but rather than generating a large number of samples (as performed by the interpolation filter) and then throwing away unneeded samples and (as performed by the decimation filter), the polyphase filter generates only those samples that will, in the end, be retained. Thus, compared to the example of
The polyphase filter is defined by a set of filter coefficients. If the coefficients are extrapolated to a different set of coefficients, different sampling rates are achieved. This enables non-integer sample rate conversion through the choice of appropriate filter coefficients.
A typical sample rate converter that uses polyphase filters contains memory for storing samples from the input data stream, memory for storing filter coefficients, hardware for performing interpolation calculations for the filter coefficients, and a multiply-accumulate unit for calculating inner products of the data and coefficients. Typically, these components are all implemented using dedicated hardware. This is very costly, particularly in terms of the additional logic required to perform the calculations, and in terms of the dedicated memories that are needed for input sample data. These memories are relatively small and therefore utilize silicon area in a manner that is relatively inefficient. While it is also possible to implement a sample rate converter entirely in software, such implementations typically cannot provide the speed necessary to support audio applications.
The present systems and methods therefore utilize a combination of hardware and software components to achieve both speed and efficiency in the sample rate converter. These systems and methods make use of processors that have sufficient computational power and memory reserves to implement the required components.
Referring to
As shown in
Frame sync signals associated with the audio data are received by rate estimator counters 421 and 422. Rate estimator counters 421 and 422 simply count the numbers of clock cycles between samples received on the respective channels. (It should be noted that, while the present embodiment has two channels, and corresponding rate estimators, other embodiments may handle N channels and have N corresponding sets of components.) One of the rate estimator counters is selected by multiplexer 430 and the corresponding count is filtered by low pass filter 440. The filtered sample rate count is forwarded to phase selection unit 450, and is used to interpolate the filter coefficients for the polyphase filter. The interpolated polyphase filter coefficients are then convolved with the data samples in convolution unit 410 to produce the re-sampled data.
The flow of data samples through FIFO 405 and FIFO 406 are managed by FIFO management unit 407. based on the flow of data, FIFO management unit 407 provides feedback to feedback unit 470. This feedback is used to adjust low pass filter 440. Effectively, this adjusts the sample rate which is estimated and thereby adjusts the coefficient interpolation performed in the sample rate converter. The sample rate conversion is thereby also adjusted to more closely track the actual input sample rate and to prevent the overflow or underflow of FIFOs 405 and 406.
It can be seen that the components of
In one embodiment, rate estimator counters 421 and 422 are 24-bit counters. Each can select from four input frame sync signals: SAI LRCK; SPDIF RX frame sync; Packet Data frame sync; and ESSI frame sync. The period measurement is accomplished by counting the number of DSP clock cycles within the counting period of the frame sync signal. The counting period is programmable, typically with the period equal to 1. In this embodiment, the count is multiplied by a gain. The gain is a 12-bit integer which is typically set to a power of 2, which is equivalent to moving a decimal point. This may facilitate increased resolution in low-pass filter 440.
Low pass filter 440 is, in one embodiment, a second-order IIR filter. This filter may, for example, comprise a pair of cascaded first-order IIR filters. Low pass filter 440 attenuates jitter in the count received from the rate estimator counter. This ensures that the count changes slowly, and thereby improves the quality of the sample rate conversion. The averaging process that is implemented by the low pass filter causes the potential for buffer underflow or overflow. This problem is corrected by implementing closed loop feedback in the software which adjusts a 24-bit offset that is added to the count value before the value is passed through low pass filter 440. In one embodiment, the filter coefficient of low pass filter 440 is adjustable to allow faster frequency and phase lock.
Coefficient interpolator 460 works in conjunction with the ROM in which the coefficients are stored and the ROM address generator that provides addresses for retrieval of the coefficients for use by the interpolator. The filter coefficients are actually stored in two ROMs—one stores even coefficients, while the other stores odd coefficients. The interpolator performs a cubic spline interpolation. The interpolator employs a five-stage, two-cycle pipeline to perform the interpolation, thereby enabling resource sharing while maintaining a throughput of one interpolation per two clock cycles.
The components that are implemented in software include convolution unit 410, phase selection unit 450, FIFO management unit 407 and feedback unit 470. These components provide flexibility that is not possible in the strictly hardware implementations of the prior art. The software components read the values of the rate estimator counters 421 and 422 and determine the input sample rates from these values. The rate estimates are adjusted by feedback from software components such as FIFO management unit 407 and feedback unit 470. The estimated rates are then used by phase selection software 450 to interpolate the polyphase filter coefficients, and the convolution of the coefficients with the input data samples is performed by convolution unit 410. Convolution unit 410 is implemented in software because a typical DSP can efficiently perform this function while reading in samples from main memory and coefficients from coefficient interpolator 460.
In one embodiment, the software of the sample rate converter is responsible for performing a number of tasks. For example, as mentioned above, rate estimator counters 421 and 422 multiply their respective counter values by a gain, but the gain is determined by the software. Similarly, the offset and filter coefficients for the low pass filter following the rate estimator counters are determined by the software. The software is further responsible for calculating the ratio of the input sample rate (Fin) to the output sample rate (Fout), which is fixed in the preferred embodiment. Based upon the ratio of sample rates and the filtered counter values, the software determines the filter length, phase and phase increment for interpolation of the polyphase filter coefficients. Further, the software is responsible for convolving the polyphase filter coefficients with the input samples, managing the input and output FIFOs, and providing feedback for adjustment of the estimated input sample rate.
The software components are implemented in a data processor. Typical modern processors have the capability of executing tight loops very efficiently while reading in data streams. For example, digital signal processors (DSP's) have “zero overhead looping” capability. Modern microcontrollers also have the capability of executing multiple instructions per cycle. These DSP's and microcontrollers typically also have separate program and data memories that make them suitable for sample rate converter applications.
These processors have the capability, for example, to execute the following in one processor cycle: read a data sample from memory (as indicated by a sample pointer register); update the sample pointer register to point to a next sample; fetch a coefficient value from the peripheral coefficient interpolation unit; multiply the data sample by the coefficient value; and add (accumulate) the result of the multiplication in a data register. If the polyphase filter contains X coefficients, X clock cycles are used to compute one output sample.
A processor can handle a number of parallel channels Y at the same time, where Y is limited by the available number of accumulator and sample pointer registers. When Y channels are processed simultaneously using identical coefficients, relatively compact hardware can be designed to perform the following in Y or less cycles: read a number of coefficients from memory (as indicated by coefficient pointer); update a coefficient pointer register; and perform interpolation to calculate filter coefficients to a desired precision.
In “pseudo C” the processor would do the following:
for every output sample
Initialize the hardware coefficient calculator
for j=1 to Y
o[Y] = 0;
// Initialize accumulators
p[Y] = start(N);
// Initialize pointers
for i=1 to X
// For every coefficient
C = mem[coeff]
// Read coefficient
for j=1 to Y
// For every channel
o[Y] += C*mem[p[Y]++]
Typically, the inner loop using j would be unrolled, and reading the next coefficient would be done in parallel with the last iteration (j=Y). A simple and efficient processor would calculate a new coefficient for every Y cycles. A more flexible solution would calculate a coefficient in Y or fewer cycles. When a new sample becomes available, it will halt computations until this sample is read and thereby automatically adjust to the rate at which the DSP reads the filter coefficients. Besides making the actual value of Y more flexible, this also allows the processor to periodically halt the computations and service other functions like interrupts.
The various embodiments of the invention may provide a number of advantages which were not available in the prior art. For example, at a very high level, the combination of hardware and software components allows the present systems and methods to provide greater speed and flexibility in the performance of sample rate conversion functions than prior art systems that were implemented entirely in hardware, or entirely in software. They may also be implemented more efficiently than in the prior art.
In some embodiments, components of the sample rate converter may be shared between two or more independent sample rate conversion paths. For instance, two different paths may both use the same polyphase filter coefficients interpolation hardware, potentially including the ROMs that store the coefficients, the address generator and the interpolator itself. Another example of resources that are shared across sample rate conversion paths is the data processor that executes the software components of the respective paths. Despite the shared resources, the sample rate conversion paths each perform their respective sample rate conversion functions independently of the others.
Another advantage of at least some embodiments of the invention is the ability to process input data streams that have sample rates which are allowed to vary. Because each sample rate conversion path includes a sample rate estimator to determine the input sample rate, as well as various components to adapt the function of the sample rate converter to this input sample rate, the sample rate converter is not subject to errors from variations in the sample rates. A related advantage is the ability to independently adapt two different sample rate conversion paths to input data streams which have different sample rates.
Another advantage is the ability to simplify the implementation of some of the components of the sample rate converter. For example, in one embodiment, the rate estimator hardware for each sample rate conversion path consists of a simple counter. That counter can easily be read by a software component, which can then determine the sample rate of an input data stream based upon the value of the counter.
Those of skill in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. The information and signals may be communicated between components of the disclosed systems using any suitable transport media, including wires, metallic traces, vias, optical fibers, and the like.
Those of skill will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those of skill in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with general purpose processors, digital signal processors (DSPs) or other logic devices, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete gates or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be any conventional processor, controller, microcontroller, state machine or the like. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in software or firmware modules executed by a processor, or in a combination thereof. A software product may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The benefits and advantages which may be provided by the present invention have been described above with regard to specific embodiments. These benefits and advantages, and any elements or limitations that may cause them to occur or to become more pronounced are not to be construed as critical, required, or essential features of any or all of the claims. As used herein, the terms “comprises,” “comprising,” or any other variations thereof, are intended to be interpreted as non-exclusively including the elements or limitations which follow those terms. Accordingly, a system, method, or other embodiment that comprises a set of elements is not limited to only those elements, and may include other elements not expressly listed or inherent to the claimed embodiment.
While the present invention has been described with reference to particular embodiments, it should be understood that the embodiments are illustrative and that the scope of the invention is not limited to these embodiments. Many variations, modifications, additions and improvements to the embodiments described above are possible. It is contemplated that these variations, modifications, additions and improvements fall within the scope of the invention as detailed within the following claims.
Hand, Larry E., Andersen, Jack B., Chieng, Daniel L. W., Taylor, Wilson E., Page, Joel W., Andersen, Tonya
| Patent | Priority | Assignee | Title |
| 9166843, | Aug 14 2013 | Industrial Technology Research Institute | Digital pulse width generator and method for generating digital pulse width |
| Patent | Priority | Assignee | Title |
| 5185805, | Dec 17 1990 | Tuned deconvolution digital filter for elimination of loudspeaker output blurring | |
| 5331346, | Oct 07 1992 | Matsushita Electric Corporation of America | Approximating sample rate conversion system |
| 5331436, | Jan 03 1992 | Kabushiki Kaisha Toshiba | Encoder and decoder |
| 5475628, | Sep 30 1992 | Analog Devices, Inc | Asynchronous digital sample rate converter |
| 5481568, | Feb 14 1992 | Sony Corporation | Data detecting apparatus using an over sampling and an interpolation means |
| 5824936, | Jan 17 1997 | Cirrus Logic, INC | Apparatus and method for approximating an exponential decay in a sound synthesizer |
| 5986589, | Oct 31 1997 | ATI Technologies ULC | Multi-stream audio sampling rate conversion circuit and method |
| 6057789, | Oct 29 1998 | HANGER SOLUTIONS, LLC | Re-synchronization of independently-clocked audio streams by dynamically switching among 3 ratios for sampling-rate-conversion |
| 6061410, | Feb 27 1997 | HANGER SOLUTIONS, LLC | Frequency ratio estimation arrangement and method thereof |
| 6134268, | Oct 19 1998 | Google Technology Holdings LLC | Apparatus for performing a non-integer sampling rate change in a multichannel polyphase filter |
| 6593807, | Dec 21 2000 | Digital amplifier with improved performance | |
| 6695783, | Dec 22 2000 | Koninklijke Philips Electronics N.V. | Multiline ultrasound beamformers |
| 7218581, | Dec 20 2002 | KONINKLIJKE PHILIPS ELECTRONICS, N V | Asynchronous crosstalk cancellation |
| 7345600, | Mar 09 2005 | Texas Instruments Incorporated | Asynchronous sampling rate converter |
| 7528745, | Feb 15 2006 | Qualcomm Incorporated | Digital domain sampling rate converter |
| 20020093437, | |||
| 20020105448, | |||
| 20020190880, | |||
| 20030179116, | |||
| GB2267193, | |||
| JP2002314429, | |||
| JP2008018518, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Mar 18 2004 | ANDERSEN, JACK B | D2Audio Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032843 | /0924 | |
| Mar 18 2004 | HAND, LARRY E | D2Audio Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032843 | /0924 | |
| Mar 18 2004 | CHIENG, DANIEL L W | D2Audio Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032843 | /0924 | |
| Mar 20 2004 | PAGE, JOEL W | D2Audio Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032843 | /0924 | |
| Jan 23 2009 | D2Audio Corporation | (assignment on the face of the patent) | / | |||
| Mar 20 2009 | TAYLOR, WILSON E | D2Audio Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032843 | /0966 | |
| Dec 23 2011 | D2Audio Corporation | D2AUDIO LLC | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 032917 | /0916 | |
| Mar 29 2013 | D2AUDIO LLC | INTERSIL AMERICAS LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032980 | /0276 |
| Date | Maintenance Fee Events |
| Jul 23 2014 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
| Jul 23 2018 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
| Date | Maintenance Schedule |
| Jun 26 2015 | 4 years fee payment window open |
| Dec 26 2015 | 6 months grace period start (w surcharge) |
| Jun 26 2016 | patent expiry (for year 4) |
| Jun 26 2018 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Jun 26 2019 | 8 years fee payment window open |
| Dec 26 2019 | 6 months grace period start (w surcharge) |
| Jun 26 2020 | patent expiry (for year 8) |
| Jun 26 2022 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Jun 26 2023 | 12 years fee payment window open |
| Dec 26 2023 | 6 months grace period start (w surcharge) |
| Jun 26 2024 | patent expiry (for year 12) |
| Jun 26 2026 | 2 years to revive unintentionally abandoned end. (for year 12) |