Method and apparatus for preventing boosting system bus when charging a battery

Abstract

A controllably alternating buck mode DC-DC converter conducts cycle by cycle analysis of the direction of inductor current flow to decide whether to operate in synchronous buck mode or standard buck mode for the next successive cycle. For each cycle of the pwm waveform controlling the buck mode DC-DC converter, a mode control circuit examines and latches data representative of the direction of inductor current flow relative to the chargeable battery. If the inductor current flow is positive, a decision is made to operate in synchronous buck mode for the next pwm cycle, which allows positive current to charge the battery; if the inductor current drops to zero, a decision is made to operate the converter in standard buck mode for the next pwm cycle, so as to prevent current from flowing out of the battery and boosting the system bus.

Description

CROSS-REFERENCE TO RELATED APPLICATION

then,
(Vi−Vout)/L=2Io/dT=2Io/(T(Vo/Vi)).
Solving for Io,
Io=(1−(Vout/Vi))Vo(T/2L).

It should be noted that in the course of transitioning from standard buck mode to synchronous buck mode, it is not possible to have negative inductor current. As noted above, the present invention prevents the flow of negative inductor current by discriminating between positive inductor current and ‘tending’ toward negative or ‘zero’ inductor current. If positive inductor current is flowing, the phase node voltage is one body diode drop (Vbe) below ground (e.g., −700 mV); for zero inductor current, the phase node voltage is equal to Vout.

When the converter is operating in standard buck mode, the slope of the falling ramp of the inductor current, namely di/dt, is equal to −(Vout+Vbe)/L, where L is the inductance of inductor 27, since LFET 23 has a body diode drop across it, as described above. When the converter is operating in synchronous buck mode, LFET 23 is no longer a diode, but is essentially shorted out, so that the Vbe term goes to zero. This changes the slope di/dt of the falling ramp to −Vout/L.

As will be appreciated from the foregoing description, drawbacks of a conventional synchronous buck mode-based battery charger of the type described above with reference to FIGS. 1-4, are effectively obviated by the controllably alternating buck mode DC-DC converter of the present invention, which uses a cycle by cycle analysis of the direction of inductor current flow to decide whether the converter is to operate in synchronous buck mode or standard buck mode for the next successive cycle. For each cycle of the PWM waveform, that controls the operation of the buck mode DC-DC converter, the invention examines and latches a data bit representative of the direction of inductor current flow relative to the chargeable battery. If the direction of output inductor current flow is positive, a decision is made that the converter is to operate in synchronous buck mode for the next PWM cycle, so as to allow positive current to charge the battery; on the other hand, if the inductor current drops to zero, a decision is made to operate the converter in standard buck mode for the next PWM cycle, so as to prevent current from flowing out of the battery and boosting the system bus.

It may be noted that an alternative methodology of the present invention involves an examination of more than one cycle of the waveform before switching the operational mode. As a non-limiting example, a decision could be made to switch modes after having three consecutive readings each of which indicates that a mode switch should be effected.

While we have shown and described an embodiment in accordance with the present invention, it is to be understood that the same is not limited thereto but is susceptible to numerous changes and modifications as known to a person skilled in the art. We therefore do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.

Claims

1. A controllably alternating buck mode DC-DC converter comprising:

an upper switching stage and a lower switching stage having controlled current flow paths therethrough coupled between an input voltage terminal adapted to receive an input voltage, and a reference voltage terminal adapted to receive a reference voltage, a common node between said upper switching stage and said lower switching stage being coupled through an output inductor to an output port for charging a battery, said upper switching stage having an upper control terminal to which a first pulse width modulation (pwm) waveform is applied for controlling the conduction and non-conduction of said upper switching stage, and wherein said lower switching stage has a lower control terminal to which a second pwm waveform, referenced to said first pwm waveform, is selectively applied for controlling the conduction and non-conduction of said lower switching stage; and

a lower switching stage controller, which is operative,

in response to a positive inductor current flow from said common node to said output port at the end of one or more cycles including a respective ith cycle of said first pwm waveform, to allow said second pwm waveform to be applied to said lower control terminal of said lower switching stage during the (i+1)th cycle of said first pwm waveform, and thereby cause said buck mode DC-DC converter to operate in synchronous buck mode for the (i+1)th cycle of said first pwm waveform, and

in response to inductor current dropping to zero during said one or more cycles including said respective ith cycle of said first pwm waveform, to cause diode emulation of said lower switching stage during the (i+1)th cycle of said first pwm waveform, and thereby cause said buck mode DC-DC converter to operate in standard buck mode for the (i+1)th cycle of said first pwm waveform.

2. The DC-DC converter according to claim 1, wherein said lower switching stage controller is operative to store information representative of the direction of inductor current flow for said ith cycle of said first pwm waveform, and to selectively cause said buck mode DC-DC converter to operate in either synchronous buck mode or standard buck mode for the (i+1)th cycle of said first pwm waveform, based upon said information.

3. The DC-DC converter according to claim 2, wherein said lower switching stage controller comprises:

a phase detector having inputs thereof coupled across the current flow path through said second switching stage, and an output coupled to a logic circuit,

a flip-flop having an input coupled to said output of said phase detector, a clock input coupled to receive said first pwm waveform, and an output coupled to said logic circuit,

said logic circuit being coupled to receive said first pwm waveform and having an output coupled to said lower control terminal of said lower switching stage.

4. The DC-DC converter according to claim 3, wherein said lower switching stage controller further comprises a blanking circuit which is operative to controllably disable said phase detector for a prescribed period of time following the termination of said first pwm waveform.

5. The DC-DC converter according to claim 1, wherein, in response to a positive inductor current flow from said common node to said output port at the end of said one or more cycles including said respective ith cycle of said first pwm waveform, said lower switching stage controller is operative to generate said second pwm waveform as the complement of said first pwm waveform, for application to said lower control terminal of said lower switching stage during the (i+1)th cycle of said first pwm waveform, and thereby cause said buck mode DC-DC converter to operate in synchronous buck mode for the (i+1)th cycle of said first pwm waveform.

6. The DC-DC converter according to claim 1, wherein, in response to a zero inductor current during said one or more cycles including said respective ith cycle of said first pwm waveform, said lower switching stage controller is operative to prevent said second pwm waveform from being applied to said lower control terminal of said lower switching stage during the (i+1)th cycle of said first pwm waveform, and thereby cause said buck mode DC-DC converter to operate in standard buck mode for the (i+1)th cycle of said first pwm waveform.

7. The DC-DC converter according to claim 1, wherein said upper switching stage comprises an upper MOSFET and said lower switching stage comprises a lower MOSFET, and wherein said lower switching stage controller is operative, in response to a positive inductor current flow from said common node to said output port at the end of said one or more cycles including said respective ith cycle of said first pwm waveform, to allow said second pwm waveform to be applied to a gate terminal of said lower MOSFET stage during the (i+1)th cycle of said first pwm waveform, and thereby turn on said lower MOSFET and cause said buck mode DC-DC converter to operate in synchronous buck mode for the (i+1)th cycle of said first pwm waveform and, in response to inductor current dropping to zero during said one or more cycles including said respective ith cycle of said first pwm waveform, to turn off said lower MOSFET during the (i+1)th cycle of said first pwm waveform, and thereby cause said buck mode DC-DC converter to operate in standard buck mode for the (i+1)th cycle of said first pwm waveform.

8. A method of operating a buck mode DC-DC converter comprised of an upper switching stage and a lower switching stage having controlled current flow paths therethrough coupled between an input voltage terminal adapted to receive an input voltage, and a reference voltage terminal adapted to receive a reference voltage, a common node between said upper switching stage and said lower switching stage being coupled through an output inductor to an output port for charging a battery, said upper switching stage having an upper control terminal to which a first pulse width modulation (pwm) waveform is applied for controlling the conduction and non-conduction of said upper switching stage, and wherein said lower switching stage has a lower control terminal to which a second pwm waveform, referenced to said first pwm waveform, is selectively applied for controlling the conduction and non-conduction of said lower switching stage, said method comprising the steps of:

(a) in response to a positive inductor current flow from said common node to said output port at the end of each of one or more cycles including a respective ith cycle of said first pwm waveform, coupling said second pwm waveform to said lower control terminal of said lower switching stage during an (i+1)th cycle of said first pwm waveform, thereby causing said buck mode DC-DC converter to operate in synchronous buck mode for the (i+1)th cycle of said first pwm waveform; and

(b) in response to inductor current dropping to zero during said one or more cycles including said respective ith cycle of said first pwm waveform, producing diode emulation of said lower switching stage during the (i+1)th cycle of said first pwm waveform, thereby causing said buck mode DC-DC converter to operate in standard buck mode for the (i+1)th cycle of said first pwm waveform.

9. The method according to claim 8, wherein step (a) comprises storing information representative of the direction of inductor current flow for said ith cycle of said first pwm waveform, and selectively causing said buck mode DC-DC converter to operate in synchronous buck mode for the (i+1)th cycle of said first pwm waveform, in response to said information being representative of positive inductor current flow.

10. The method according to claim 8, wherein step (b) comprises storing information representative of the direction of inductor current flow for said one or more cycles including said ith cycle of said first pwm waveform, and selectively causing said buck mode DC-DC converter to operate in standard buck mode for the (i+1)th cycle of said first pwm waveform, in response to said information being representative of zero inductor current flow.

11. The method according to claim 8, further comprising the step (c) of controllably disabling steps (a) and (b) for a prescribed period of time following the termination of said first pwm waveform.

12. The method according to claim 8, wherein, in response to a positive inductor current flow from said common node to said output port during said one or more cycles including said respective ith cycle of said first pwm waveform, step (a) comprises generating said second pwm waveform as the complement of said first pwm waveform, for application to said lower control terminal of said lower switching stage during the (i+1)th cycle of said first pwm waveform, thereby causing said buck mode DC-DC converter to operate in synchronous buck mode for the (i+1)th cycle of said first pwm waveform.

13. The method according to claim 8, wherein, in response to a zero inductor current during said one or more cycles including said respective ith cycle of said first pwm waveform, step (b) comprises preventing said second pwm waveform from being applied to said lower control terminal of said lower switching stage during the (i+1)th cycle of said first pwm waveform, thereby causing said buck mode DC-DC converter to operate in standard buck mode for the (i+1)th cycle of said first pwm waveform.

14. A controller for a buck mode DC-DC converter comprised of an upper switching stage and a lower switching stage having controlled current flow paths therethrough coupled between an input voltage terminal adapted to receive an input voltage, and a reference voltage terminal adapted to receive a reference voltage, a common node between said upper switching stage and said lower switching stage being coupled through an output inductor to an output port for charging a battery, said upper switching stage having an upper control terminal to which a first pulse width modulation (pwm) waveform is applied for controlling the conduction and non-conduction of said upper switching stage, and wherein said lower switching stage has a lower control terminal to which a second pwm waveform, referenced to said first pwm waveform, is selectively applied for controlling the conduction and non-conduction of said lower switching stage, said controller comprising:

a storage device which is operative to store information representative of the direction of inductor current flow for one or more cycles including an ith cycle of said first pwm waveform; and

a logic circuit coupled to storage device and said lower switching stage and being operative to selectively cause said buck mode DC-DC converter to operate in one of synchronous buck mode and standard buck mode for an (i+1)th cycle of said first pwm waveform, based upon said information stored by said storage device.

15. The controller according to claim 14, wherein said logic circuit is operative, in response to a positive inductor current flow from said common node to said output port at the end of said one or more cycles including said ith cycle of said first pwm waveform, to allow said second pwm waveform to be applied to said lower control terminal of said lower switching stage during said (i+1)th cycle of said first pwm waveform, and thereby cause said buck mode DC-DC converter to operate in synchronous buck mode for the (i+1)th cycle of said first pwm waveform.

16. The controller according to claim 14, wherein said logic circuit is operative, in response to said inductor current being reduced to zero during one or more cycles including said ith cycle of said first pwm waveform, to cause diode emulation of said lower switching stage during the (i+1)th cycle of said first pwm waveform, and thereby cause said buck mode DC-DC converter to operate in standard buck mode for the (i+1)th cycle of said first pwm waveform.

17. The controller according to claim 14, further comprising a phase detector having inputs thereof coupled across the current flow path through said second switching stage, and an output coupled to said logic circuit, and wherein said memory device comprises a flip-flop having an input coupled to said output of said phase detector, a clock input coupled to receive said first pwm waveform, and an output coupled to said logic circuit, and wherein said logic circuit is coupled to receive said first pwm waveform and having an output coupled to said lower control terminal of said lower switching stage.

18. The controller according to claim 17, wherein said lower switching stage controller further comprises a blanking circuit which is operative to controllably disable said phase detector for a prescribed period of time following the termination of said first pwm waveform.

19. The controller according to claim 14, wherein, in response to a positive inductor current flow from said common node to said output port at the end of said one or more cycles including said ith cycle of said first pwm waveform, said logic circuit is operative to generate said second pwm waveform as the complement of said first pwm waveform, for application to said lower control terminal of said lower switching stage during the (i+1)th cycle of said first pwm waveform, and thereby cause said buck mode DC-DC converter to operate in synchronous buck mode for the (i+1)th cycle of said first pwm waveform.

20. The controller according to claim 14, wherein, in response to a zero inductor current during said one or more cycles including said ith cycle of said first pwm waveform, said logic circuit is operative to prevent said second pwm waveform from being applied to said lower control terminal of said lower switching stage during the (i+1)th cycle of said first pwm waveform, and thereby cause said buck mode DC-DC converter to operate in standard buck mode for the (i+1)th cycle of said first pwm waveform.

21. A method of controlling the operating mode of a buck mode regulator to charge a battery from an input voltage source, the method comprising:

monitoring a signal related to inductor current of the buck mode regulator;

operating the buck mode regulator in a synchronous operating mode during a current switching cycle when the signal related to inductor current exceeds a threshold during an entire previous switching cycle, irrespective of inductor current during the current switching cycle; and

operating the buck mode regulator in a standard operating mode during the current switching cycle when the inductor current reaches less than or equal to approximately zero during the previous switching cycle, irrespective of the inductor current during the current switching cycle.

22. The method of claim 21, wherein operating the buck mode regulator in a standard operating mode during a current switching cycle comprises opening the low side switch for the whole current switching cycle.

23. A method of operating a switching stage controller, comprising:

determining whether a signal related to an inductor current is above a first threshold or below a second threshold at the end of an ith cycle of a pulse width modulation (pwm) waveform;

outputting a control signal to operate a circuit coupled to the switching stage controller in synchronous buck mode during a current switching cycle when the signal related to an inductor current is above the first threshold during a previous switching cycle, irrespective of the inductor current during the current switching cycle; and

outputting a control signal to operate the circuit in standard buck mode during the current switching cycle when the signal related to an inductor current is below the second threshold during the previous switching cycle, irrespective of the inductor current during the current switching cycle.

24. A method for operating a controller for a voltage regulator, comprising:

generating a pulse width modulation (pwm) signal for control of an upper and a lower switch in the voltage regulator; and

outputting a control signal to the voltage regulator based on a feedback signal related to an inductor current of the voltage regulator;

wherein the control signal operates the voltage regulator in synchronous buck mode for an (i+1)th cycle of a pwm waveform of the pwm signal when the feedback signal related to an inductor current flow is above a first threshold during an entire ith cycle of the pwm waveform, irrespective of the inductor current flow during the (i+1)th cycle; and

wherein the control signal operates the voltage regulator in standard buck mode for the (i+1)th cycle of the pwm waveform of the pwm signal when the signal related to an inductor current flow falls below a second threshold during the ith cycle of the pwm waveform, irrespective of the inductor current flow during the (i+1)th cycle.

25. A method of operating an alternating buck mode DC-DC converter, comprising:

applying a first pulse width modulation (pwm) waveform to an upper control terminal of an upper switching stage for controlling the conduction and non-conduction of the upper switching stage;

applying a second pwm waveform to a lower control terminal of a lower switching stage to operate the buck mode DC-DC converter in synchronous buck mode for an (i+1)th cycle of the first pwm waveform in response to a signal at a common node between the lower switching stage and the upper switching stage related to an inductor current flow being above a first threshold during an entire ith cycle of the first pwm waveform; and

applying the second pwm waveform to the lower control terminal to operate the buck mode DC-DC converter in standard buck mode for the (i+1)th cycle of the first pwm waveform in response to the signal related to inductor current flow falling below a second threshold during the ith cycle of the first pwm waveform.

26. A method of operating an alternating buck mode DC-DC converter, comprising:

applying a first pulse width modulation (pwm) signal to an upper control terminal of an upper switching stage for controlling the conduction and non-conduction of the upper switching stage;

applying a second pwm signal to a lower control terminal of a lower switching stage coupled in series with the upper switching stage between an input voltage terminal adapted to receive an input voltage and a reference voltage terminal adapted to receive a reference voltage, wherein the second pwm signal selectively controls the conduction and non-conduction of the lower switching stage;

wherein the second pwm signal operates the buck mode DC-DC converter in synchronous buck mode for an (i+1)th cycle of a pwm waveform of the first pwm signal when a signal related to an inductor current is above a first threshold during an entire ith cycle of the first pwm waveform; and

wherein the second pwm signal operates the buck mode DC-DC converter in standard buck mode for the (i+1)th cycle of the pwm waveform of the first pwm signal when the signal related to an inductor current falls below a second threshold during the ith cycle of the first pwm waveform.

27. A method of operating an alternating buck mode DC-DC converter, comprising:

applying a first pulse width modulation (pwm) waveform to an upper control terminal of an upper switching stage for controlling the conduction and non-conduction of the upper switching stage; and

applying a second pwm waveform to a lower control terminal of a lower switching stage coupled in series with the upper switching stage between an input voltage terminal adapted to receive an input voltage and a reference voltage terminal adapted to receive a reference voltage, wherein the second pwm waveform selectively controls the conduction and non-conduction of the lower switching stage;

wherein the second pwm waveform operates the buck mode DC-DC converter in synchronous buck mode for an (i+1)th cycle of a pwm waveform of the first pwm waveform when a signal related to inductor current flow at a common node between the upper switching stage and lower switching stage coupled through an output inductor to an output port for charging a battery is of at least an output current threshold during an entire ith cycle of the first pwm waveform; and

wherein the second pwm waveform operates the buck mode DC-DC converter in standard buck mode for the (i+1)th cycle of the pwm waveform of the first pwm waveform when the signal related to inductor current flow at the common node falls to approximately zero during one or more cycles including the ith cycle of the first pwm waveform.

28. The method of claim 27, further comprising:

remaining in either standard buck mode or synchronous buck mode for a period of time following a transition of the first pwm waveform.

29. The method of claim 27, wherein the second pwm waveform is an approximate complement of the first pwm waveform.