Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in response to the request, determining whether the first cell is in a disturbed condition based on the read operation. The method includes reading data stored in the first cell in response to the read request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition.
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1. A method for reading memory cells in an array of non-volatile multilevel memory cells, the method comprising:
receiving a request to read data stored in a first cell of a first word line;
performing a read operation on an adjacent cell of a second word line in response to the request;
determining whether the first cell is in a disturbed condition based on the read operation; and
reading data stored in the first cell in response to the request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition.
19. A method for reading memory cells in an array of non-volatile multilevel memory cells, the method comprising:
receiving a request to read data stored in a first cell of a first word line;
performing a read operation on an adjacent cell of a second word line in response to the request;
determining whether the first cell is in a disturbed condition based on the read operation; and
reading data stored in the first cell in response to the request, wherein the reading includes:
using a first bit line sensing period to read data stored in the first cell when the first cell is determined to be in an undisturbed condition; and
using a different bit line sensing period to read data stored in the first cell when the first cell is determined to be in the disturbed condition.
14. A method for reading memory cells in an array of non-volatile multilevel memory cells, the method comprising:
receiving a request to read data stored in a first cell of a first word line;
performing a read operation on an adjacent cell of a second word line in response to the request;
determining whether the first cell is in a disturbed condition based on the read operation; and
reading data stored in the first cell in response to the request, wherein the reading includes:
using a first precharge bit line voltage to read data stored in the first cell when the first cell is determined to be in an undisturbed condition; and
using a different precharge bit line voltage to read data stored in the first cell when the first cell is determined to be in the disturbed condition.
9. A method for reading memory cells in an array of non-volatile multilevel memory cells, the method comprising:
receiving a request to read data stored in a first cell of a word line;
performing a read operation on a second cell of the word line in response to the request, wherein the second cell is adjacent to the first cell;
determining whether the first cell is in a disturbed condition based on the read operation performed on the second cell;
reading data stored in the first cell, based on the read operation performed on the second cell, by:
using a first bit line sensing parameter to read the first cell if it is determined to be in an undisturbed condition; and
using a different bit line sensing parameter to read the first cell if it is determined to be in the disturbed condition.
25. A non-volatile memory device comprising:
an array of non-volatile multilevel memory cells arranged in rows coupled by word lines and columns coupled by bit lines; and
control circuitry coupled to the array of memory cells and configured to execute a method for reading data from the memory cells, wherein the method includes:
receiving a request to read data from a first cell of a first word line;
performing a read operation on an adjacent cell of a second word line in response to the request;
determining whether the first cell is in a disturbed condition based on the read operation; and
reading data from the first cell in response to the request by:
applying a read reference voltage to the first word line;
using a particular sensing parameter if the first cell is determined to be in an undisturbed condition; and
using an adjusted sensing parameter if the first cell is determined to be in the disturbed condition.
30. A non-volatile memory device comprising:
an array of non-volatile multilevel memory cells arranged in rows coupled by word lines and columns coupled by bit lines; and
control circuitry coupled to the array of memory cells and configured to execute a method for reading data from the memory cells, wherein the method includes:
receiving a request to read data from a first cell of a first word line;
performing a read operation on an adjacent cell of a second word line in response to the request;
determining whether the first cell is in a disturbed condition based on the read operation;
reading data from the first cell in response to the request by using a first precharge bit line voltage when the first cell is determined to be in an undisturbed condition; and
reading data from the first cell in response to the request by using a different precharge bit line voltage when the first cell is determined to be in the disturbed condition.
34. A non-volatile memory device comprising:
an array of non-volatile multilevel memory cells arranged in rows coupled by word lines and columns coupled by bit lines; and
control circuitry coupled to the array of memory cells and configured to execute a method for reading data from the memory cells, wherein the method includes:
receiving a request to read data stored in a first cell of a first word line;
performing a read operation on an adjacent cell of a second word line in response to the request;
determining whether the first cell is in a disturbed condition based on the read operation; and
reading data from the first cell in response to the request, wherein the reading includes:
using a first bit line sensing period to read data from the first cell when the first cell is determined to be in an undisturbed condition; and
using a different bit line sensing period to read data from the first cell when the first cell is determined to be in the disturbed condition.
38. A non-volatile memory device comprising:
an array of non-volatile multilevel memory cells arranged in rows coupled by word lines and columns coupled by bit lines; and
control circuitry coupled to the array of memory cells and configured to execute a method for reading data from the memory cells, wherein the method includes:
receiving a request to read data from a first number of cells of a word line that are programmed together;
in response to the request, performing a read operation on a second number of cells of the word line that are programmed together and are adjacent to the first number of cells;
determining whether each of the first number of cells are in a disturbed condition based on the read operation performed on the second number of cells; and
reading data stored in the first number of cells, in response to the request, by:
using a first bit line sensing parameter to read those of the first number of cells determined to be in an undisturbed condition; and
using a different bit line sensing parameter to read those of the first number of cells determined to be in the disturbed condition.
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associating a particular disturbed and a particular undisturbed bit line sensing period with each of the multiple different data states; and
determining which particular disturbed and undisturbed bit line sensing period to use for reading data stored in the first cell based on the determined data state of the adjacent cell.
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This application claims priority to Italian Patent Application Serial No. RM2007A000273, filed May 16, 2007, the specification of which is incorporated herein by reference
The present disclosure relates generally to semiconductor devices and, more particularly, to memory devices having non-volatile multilevel memory cells.
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory, among others.
Flash memory devices are utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
Uses for flash memory include memory for personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices. This information can be used in personal computer systems, among others.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged
A NAND array architecture arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are coupled by rows to word select lines. However each memory cell is not directly coupled to a column bit line by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a source line and a column bit line.
Memory cells in a NAND array architecture can be configured, e.g., programmed, to a desired state. That is, electric charge can be placed on or removed from the floating gate of a memory cell to put the cell into a number of stored states. For example, a single level cell (SLC) can represent two binary states, e.g., 1 or 0. Flash memory cells can also store more than two binary states, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110. Such cells may be referred to as multi state memory cells, multibit cells, or multilevel cells (MLCs). MLCs can allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one bit. MLCs can have more than one programmed state, e.g., a cell capable of representing four bits can have fifteen programmed states and an erased state.
As NAND flash memory is scaled, parasitic capacitance coupling between adjacent memory cell floating gates becomes a problem. Floating gate-to-floating gate interference can cause a wider Vt distribution when the distribution should be tighter. The wider distributions can result in a degraded programming performance as well as other problems.
These problems for single level cell (SLC) NAND array are even greater in a multiple level cell (MLC) NAND array. MLC memory stores multiple bits on each cell by using different threshold levels for each state that is stored. The difference between adjacent threshold voltage distributions may be very small as compared to an SLC memory device. Therefore, the effects of floating gate-to-floating gate coupling in an MLC device are greatly increased.
Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. Various embodiments can compensate for threshold voltage (Vt) shifts of memory cells caused by floating gate to floating gate (Fg-Fg) interference effects. Compensating for such Fg-Fg interference effects can reduce or prevent read errors. Embodiments of the present disclosure can compensate for Fg-Fg interference due to adjacent, e.g., neighboring, cells coupled to an adjacent word line or coupled to an adjacent bit line.
One method embodiment for reading memory cells in an array of non-volatile multilevel memory cells includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in response to the request, determining whether the first cell is in a disturbed condition based on the read operation. In various embodiments, determining whether the first cell is in a disturbed condition includes determining whether the Vt of the adjacent cell has increased since the programming of the first cell. The method includes reading data stored in the first cell in response to the read request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition.
In various embodiments, the cell adjacent to the first cell can be on the same word line, e.g., the first cell can be an odd bit line cell and the adjacent cell can be an even bit line cell. In such embodiments, in response to a request to read data stored in the first cell, e.g., odd bit line cell, a read operation is performed on an adjacent cell coupled to the same word line, e.g., an adjacent even bit line cell.
The adjusted sensing parameter can be modified based on a determined data state of the adjacent cell. In various embodiments, adjusting the sensing parameter includes adjusting a precharge bit line voltage based on the read operation performed on the adjacent cell. In various embodiments, adjusting the sensing parameter includes adjusting a sensing time period based on the read operation performed on the adjacent cell.
In various embodiments, the same read reference voltage can be applied to the first word line to read data stored in the first cell whether or not the first cell is in the disturbed condition. That is, the same read reference voltage can be used to read data from the first cell whether or not the first cell has experienced Fg-Fg interference due to programming of an adjacent cell. In some embodiments, performing the read operation on the adjacent cell includes applying only one read reference voltage to the adjacent cell during the read operation. In such embodiments, the read reference voltage can be a voltage used to determine whether the adjacent cell is in an erase state or in one of a number of program states.
In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how various embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, or mechanical changes may be made without departing from the scope of the present disclosure.
Memory array 100 includes NAND strings 109-1, . . . , 109-M. Each NAND string includes non-volatile memory cells 111-1, . . . , 111-N, each located at an intersection of a word line 105-1, . . . , 105-N and a local bit line 107-1, . . . , 107-M. The non-volatile memory cells 111-1, . . . , 111-N of each NAND string 109-1, . . . , 109-M are connected in series source to drain between a source select gate (SGS), e.g., a field-effect transistor (FET) 113, and a drain select gate (SGD), e.g., FET 119. Source select gate 113 is located at the intersection of a local bit line 107-1 and a source select line 117 while drain select gate 119 is located at the intersection of a local bit line 107-1 and a drain select line 115.
As shown in the embodiment illustrated in
In various embodiments, construction of non-volatile memory cells, 111-1, . . . , 111-N, includes a source, a drain, a floating gate or charge storage layer, and a control gate. Non-volatile memory cells, 111-1, . . . , 111-N, have their control gates coupled to a word line, 105-1, . . . , 105-N respectively. A column of the non-volatile memory cells, 111-1, . . . , 111-N, make up the NAND strings, e.g., 109-1, . . . , 109-M, coupled to a given local bit line, e.g., 107-1, . . . , 107-M respectively. A row of the non-volatile memory cells are commonly coupled to a given word line, e.g., 105-1, . . . , 105-N. An AND array architecture would be similarly laid out except that the string of memory cells would be coupled in parallel between the select gates.
Although not shown in
The method shown in
In the method shown in
Programming the logical pages associated with multilevel memory cells at different times and/or in different sequences has also been used to reduce Fg-Fg interference effects. For instance,
In
As one of ordinary skill in the art will appreciate, various encoding schemes and/or programming algorithms can be used to reduce Fg-Fg interference. Embodiments of the present disclosure for reading non-volatile multilevel memory cells can be applied to memory cells programmed according various algorithms and are not limited a particular programming process or encoding scheme such as that described in connection with
The example illustrated in
The example illustrated in
The Vt distributions 333-1 and 333-2 shown in
As shown in the lower graph of
For instance, consider a number of cells of a selected word line, some of which have been programmed to data state 331-1 (“01”) and some of which have been programmed to data state 331-2 (“00”). Subsequent to programming the cells of the selected word line, a number of cells adjacent to the cells of the selected word line, e.g., cells of an adjacent word line that share a bit line, experience programming. Some of the adjacent cells will have an increased Vt level due to the subsequent programming and will disturb the programmed cells of the selected word line, e.g., the altered Vt levels of the adjacent cells will cause a Vt level increase of the selected word line cells such that those selected word line cells belong to disturbed Vt distributions 335-1 and 335-2.
On the other hand, adjacent cells which do not have an increased Vt level due to the subsequent programming will not disturb the programmed cells of the selected word line, such that those cells belong to Vt undisturbed distributions 331-1 and 331-2. As such, in this example, the programmed memory cells of the selected word line will belong to either undisturbed distributions 331-1 and 331-2 or to disturbed distributions 335-1 and 335-2, depending on the Vt level shifts experienced by the subsequently programmed adjacent cells. As shown in
Therefore, performing a read operation on an adjacent cell, e.g., a neighboring cell coupled to an adjacent word line and sharing a bit line with a target cell to be read or a neighboring cell coupled to a bit line adjacent to the target cell's bit line, can be used to determine whether the target cell belongs to a disturbed distribution, e.g., 335-1 and 335-2, or to an undisturbed distribution, e.g., 331-1 and 331-2. The read of the adjacent cell can be used to determine whether the adjacent cell has experienced a Vt shift subsequent to programming of the target cell to a final state.
As such, in various embodiments of the present disclosure, a read operation is performed on a cell adjacent to a target cell in response to a request to read data stored in the target cell. That is, when a request to read data from a target cell is received, a read of an adjacent cell is first performed. In such embodiments, the read of the adjacent cell is used to determine a sensing parameter to be used to read the target cell.
In various embodiments, and as described in greater detail in connection with
During a read operation, a read reference voltage Vread is applied to the selected word line, e.g., to the control gate of cells 442-1 and 442-2, while a pass through voltage is applied to unselected word lines such that the unselected word line cells are turned “on,” e.g., in a conducting state. If the read reference voltage Vread applied to the control gates is greater than the Vt level of the memory cells, then the cell will turn “on” and conduct current between its source and drain. If Vread is less than the Vt level of the cell, then the cell will be “off” and will not conduct current or will conduct less current than when the cell is “on.” In various embodiments, the voltage level of a bit line can be sensed by a sensing module coupled to the bit line, e.g., sensing module 552-1 or 552-3 shown in
In various embodiments, the bit lines associated with cells being read, e.g., cells 442-1 and 442-2, are precharged to a particular precharge voltage level, e.g., precharge voltage level 445. In this example, the precharge voltage level 445 is 1.0V. However, embodiments of the present disclosure are not limited to a particular precharge bit line voltage. In such embodiments, the voltage level of the bit line decreases as current flows between source and drain depending on the reference read voltage applied to the selected word line. In various embodiments, the state of a cell being read can be determined based on whether the bit line voltage discharges by a predetermined amount during a predetermined bit line sensing period, or based on whether the bit line voltage reaches a predetermined threshold value during the predetermined sensing period.
For example, in the embodiments shown in
As shown in the embodiment illustrated in
In the example shown in
On the other hand, the BLV associated with the undisturbed cell, e.g., cell B 442-2, discharges by more than 500 mV, e.g., by 700 mV in this case, in response to the applied read reference voltage Vread. That is, the BLV associated with cell B after sensing period t1 indicates that cell B is “on” such that a sensing module would determine cell B to be in the 441 state, e.g., the correct state to which cell B was programmed.
As one of ordinary skill in the art will appreciate, and as described above, the amount of Fg-Fg interference, e.g., the Vt level shift amount, experienced by a target cell, e.g., a cell on WL(N), can depend on the data state to which the adjacent cell, e.g., the adjacent cell on WL(N+1), was programmed. For instance, if the adjacent cells on WL(N+1) are programmed according to the method shown in
Various embodiments of the present disclosure can reduce or prevent errors associated with reading memory cells of a first word line, e.g., WL(N) by compensating for Fg-Fg interference effects caused by programming of adjacent cells of an adjacent word line, e.g., WL(N+1). For instance, as described further below in connection with
In various embodiments, the adjusted sensing parameter can be an adjusted precharge hit line voltage and/or an adjusted bit line sensing period. In such embodiments, and as described further in connection with
In various embodiments, in response to a request to read data from a target cell of WL(N), a read operation is performed on a cell of WL(N+1) adjacent to the target cell in order to compensate for possible Fg-Fg interference effects of the WL(N+1) cell on the programmed state of the WL(N) target cell. In some embodiments, the read performed on the adjacent cell of WL(N+1) includes determining the actual data stored in the adjacent cell, e.g., the adjacent cell's programmed data state. In such embodiments, multiple read operations using different read reference voltages applied to WL(N+1) may be performed to determine a particular data state of the adjacent cell. The determined WL(N+1) data can be stored in a cache, e.g., cache 554-1/554-3 shown in
Therefore, in various embodiments, not all of the data states to which the adjacent cell can be programmed are states for which Fg-Fg interference is compensated. That is, in various embodiments, an adjusted sensing parameter, e.g., an adjusted precharge bit line voltage, is only used to read a target cell of WL(N) if the data state determined by the read of the adjacent WL(N+1) cell is a state having an associated Vt shift amount, e.g., 234-1, 234-2, or 234-3 shown in
In some embodiments, the read operation performed on the adjacent cell of WL(N+1) does not involve determining the actual data stored in the adjacent cell. For instance, in some embodiments, the read of the WL(N+1) cell includes using a single read reference voltage to determine whether the WL(N+1) cell has a Vt level above or below the particular read reference voltage value. As one example, in some embodiments, the read operation performed on the WL(N+1) cell is performed using a single read reference voltage to determine whether the WL(N+1) cell is in an erase state. In such embodiments, the read reference voltage can be 0V or another voltage, e.g., 0.1V, 0.5, among other read reference voltages that can be used to distinguish between an erase state and one or more program states.
An indication of whether the WL(N+1) cell is in the erase state can be stored in a data latch associated with the corresponding bit line of the WL(N+1) cell. For instance, the data latch can store a logic low, e.g., “0,” if the WL(N+1) cell is in the erase state and a logic high, e.g., “1,” if the WL(N+1) is in a state other than the erase state, e.g., state A, B, or C.
In such embodiments, the sensing circuitry, e.g., sensing module 552-1/552-3 shown in
As an example, and as shown in
As mentioned above and described further in connection with
The graph shown in the embodiment of
In the embodiment of
As described above in connection with
In the embodiment illustrated in
As described above, the particular adjusted precharge bit line voltage used to read WL(N) memory cells determined to be in a disturbed condition based on a performed read operation on adjacent WL(N+1), can depend on the determined WL(N+1) data, e.g., the particular data state of the adjacent WL(N+1) cell and/or Vt level shift amount associated with the programming thereof. That is, the precharge bit line voltage used to read WL(N) cells determined to be in an undisturbed condition and the adjusted precharge bit line voltage used to read WL(N) cells determined to be in a disturbed condition are not limited to the examples shown in
The graph shown in the embodiment of
In the embodiment of
In the embodiment illustrated in
As shown in
In the embodiments illustrated in
The embodiment shown in
The embodiment shown in
In the embodiment illustrated in
As one of ordinary skill in the art will appreciate, the sense modules 552-1 and 552-3 can be coupled to control circuitry, e.g., control circuitry 770 shown in
Although not shown in
As shown in
As described herein above, in various embodiments of the present disclosure, based on a request to read data from target cells of a first word line, e.g., 536-1 and 536-3 of word line N, a read operation is first performed on the cells adjacent to the target cells, e.g., adjacent cells 530-1 and 530-3 of word line N+1. The read operation performed on adjacent cells 530-1 and 530-3 can be used to determine whether the target cells 536-1 and/or 536-3 will be in a disturbed condition due to Fg-Fg interference effects. The determination of whether the target cells 536-1 and 536-3 are disturbed can depend on the data state of the adjacent cells 530-1 and 530-3, respectively. A target cell, e.g., 536-1 and/or 536-3, considered to be in a disturbed condition, will have a higher Vt level due to Fg-Fg interference from an adjacent cell. Various embodiments of the present disclosure can compensate for the increased Vt level due to Fg-Fg interference, e.g., the disturbed cell can be read as though its Vt level is lower than its actual value, which can reduce or prevent a read of the disturbed cell producing an error.
At block 620, the method includes performing a read operation on an adjacent cell of a second word line, e.g., an adjacent word line WL(N+1), in response to the request. That is, in order to read data from a target cell of WL(N), a read operation is first performed on a cell adjacent to the target cell on WL(N+1), e.g., a cell on WL(N+1) sharing a bit line with the target cell on WL(N).
At block 630, the method includes determining whether the first cell, e.g., the target cell, is in a disturbed condition based on the read operation, e.g., based on the read operation performed on the WL(N+1) cell. In various embodiments, the method includes storing a disturb status indicator in a data latch associated with a bit line of the target cell and the adjacent cell based on the read operation. In some embodiments, the data latch can store a logic “1” to indicate that the WL(N+1) cell is in a state associated with Fg-Fg interference of the target cell on WL(N), and can store a logic “0” to indicate that the WL(N+1) cell is in a state not associated with Fg-Fg interference of the target cell on WL(N).
At block 640, the method includes reading data stored in the target cell in response to the request by applying a read reference voltage to the first word line WL(N) and adjusting a sensing parameter if the target cell is in the disturbed condition. In various embodiments, the method includes applying the same read reference voltage to word line WL(N) to read data stored in the target cell whether or not the target cell is in the disturbed condition.
In various embodiments, and as described in connection with
In various embodiments, the determination of whether the target cell is in a disturbed condition is based on the actual data of the WL(N+1) cell. The method can include modifying the adjusted sensing parameter based on a determined data state of the adjacent cell, e.g., the WL(N+1) cell.
In various embodiments, and as described in connection with
In various embodiments, performing the read operation on the adjacent cell includes applying only one read reference voltage to the word line WL(N+1). In some embodiments, the target cell is determined to be in an undisturbed condition if the read performed on the adjacent WL(N+1) cell results in a determination that the WL(N+1) cell is in the erase state. In such embodiments the target cell can be determined to be in a disturbed condition if the read performed on the adjacent WL(N+1) cell results in a determination that the WL(N+1) cell is not in the erase state., e.g., the Vt level of the WL(N+1) cell has shifted due to programming performed on the WL(N+1) cell subsequent to the target cell being programmed to a particular data state.
For clarity, the electronic memory system 700 has been simplified to focus on features with particular relevance to the present disclosure. The memory device 720 includes an array of non-volatile memory cells 730, which can be floating gate flash memory cells with a NAND architecture. The control gates of each row of memory cells are coupled with a word line, while the drain regions of the memory cells are coupled to bit lines. The source regions of the memory cells are coupled to source lines, as the same has been illustrated in
The embodiment of
The memory array 730 of non-volatile cells can include non-volatile multilevel memory cells read according to embodiments described herein. The memory device 720 reads data in the memory array 730 by sensing voltage and/or current changes in the memory array columns using sense/buffer circuitry that in this embodiment can be read/latch circuitry 750. The read/latch circuitry 750 can include a number of sensing modules, e.g., 552-1 and 552-3 shown in
Control circuitry 770 decodes signals provided by control connections 772 from the processor 710. These signals can include chip signals, write enable signals, and address latch signals that are used to control the operations on the memory array 730, including data read, data write, and data erase operations. In various embodiments, the control circuitry 770 is responsible for executing instructions from the processor 710 to perform the operating and programming embodiments of the present disclosure. The control circuitry 770 can be a state machine, a sequencer, or some other type of controller. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device detail of
In some embodiments, memory module 800 will include a housing 805 (as depicted) to enclose one or more memory devices 810, though such a housing is not essential to all devices or device applications. At least one memory device 810 includes an array of non-volatile multilevel memory cells that can be read according to embodiments described herein. Where present, the housing 805 includes one or more contacts 815 for communication with a host device. Examples of host devices include digital cameras, digital recording and playback devices, PDAs, personal computers, memory card readers, interface hubs and the like. For some embodiments, the contacts 815 are in the form of a standardized interface. For example, with a USB flash drive, the contacts 815 might be in the form of a USB Type-A male connector. For some embodiments, the contacts 815 are in the form of a semi-proprietary interface, such as might be found on CompactFlash™ memory cards licensed by SanDisk Corporation, Memory Stick™ memory cards licensed by Sony Corporation, SD Secure Digital™ memory cards licensed by Toshiba Corporation and the like. In general, however, contacts 815 provide an interface for passing control, address and/or data signals between the memory module 890 and a host having compatible receptors for the contacts 815.
The memory module 800 may optionally include additional circuitry 820, which may be one or more integrated circuits and/or discrete components. For some embodiments, the additional circuitry 820 may include a memory controller for controlling access across multiple memory devices 810 and/or for providing a translation layer between an external host and a memory device 810. For example, there may not be a one-to-one correspondence between the number of contacts 815 and a number of 810 connections to the one or more memory devices 810. Thus, a memory controller could selectively couple an I/O connection (not shown in
The additional circuitry 820 may further include functionality unrelated to control of a memory device 810 such as logic functions as might be performed by an ASIC. Also, the additional circuitry 820 may include circuitry to restrict read or write access to the memory module 800, such as password protection, biometrics or the like. The additional circuitry 820 may include circuitry to indicate a status of the memory module 800. For example, the additional circuitry 820 may include functionality to determine whether power is being supplied to the memory module 800 and whether the memory module 800 is currently being accessed, and to display an indication of its status, such as a solid light while powered and a flashing light while being accessed. The additional circuitry 820 may further include passive devices, such as decoupling capacitors to help regulate power requirements within the memory module 800.
Methods, devices, modules, and systems for reading non-volatile multilevel memory cells have been shown. Various embodiments can compensate for threshold voltage (Vt) shills of memory cells caused by floating gate to floating gate (Fg-Fg) interference effects in order to reduce or prevent read errors.
One method embodiment for reading memory cells in an array of non-volatile multilevel memory cells includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in response to the request, determining whether the first cell is in a disturbed condition based on the read operation. In various embodiments, determining whether the first cell is in a disturbed condition includes determining whether the Vt of the adjacent cell has increased since the programming of the first cell. The method includes reading data stored in the first cell in response to the read request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition.
Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of various embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.
In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.
Santin, Giovanni, Moschiano, Violante, Incarnati, Michele
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