A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.
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1. A structure having a first device in a first area and a second device in a second area on a substrate, comprising:
an interfacial layer having a first thickness formed on said first area;
a high dielectric-constant (k) dielectric stack having a second thickness formed on overlying said interfacial layer and not overlying said second area;
a first gate electrode formed on said high k dielectric stack;
an ultra thin dielectric layer having a third thickness disposed on the second region area; and
a second gate electrode formed on said ultra thin dielectric layer.
0. 32. A structure having a first device in a first area and a second device in a second area on a substrate, the structure comprising:
a high dielectric-constant (k) dielectric stack having a first thickness overlying the first area and not overlying the second area, the high k dielectric stack comprising a metal oxide;
a first gate electrode formed overlying said high k dielectric stack;
an ultra thin silicon oxynitride or dioxide layer having a second thickness disposed overlying the second area; and
a second gate electrode formed overlying said ultra thin silicon oxynitride or dioxide layer.
0. 24. A structure having a first device in a first area and a second device in a second area on a substrate, the structure comprising:
a high dielectric-constant (k) dielectric stack having a first thickness overlying the first area and not overlying the second area;
a first gate electrode formed over and physically contacting said high k dielectric stack;
an ultra thin dielectric layer having a second thickness disposed overlying the second area; and
a second gate electrode formed over and physically contacting said ultra thin dielectric layer, the first gate electrode is a same material as the second gate electrode.
10. A structure having a first device in a first area, a second device in a second area, and a third device in a third area on a semiconductor substrate, comprising:
an interfacial layer having a first thickness formed on said first area;
a high dielectric-constant (k) dielectric stack having a second thickness formed on said interfacial layer;
a first gate electrode formed on said high k dielectric stack;
an ultra thin dielectric layer having a third thickness formed on the second area;
a second gate electrode formed on said ultra thin dielectric layer;
a second gate dielectric layer having a fourth thickness formed on said third area; and
a third gate electrode formed on said second dielectric layer.
23. A structure that includes a mosfet which is a low power device formed on a first device area and an adjacent mosfet which is a high performance device formed on a second device area on a substrate, comprising:
a substrate having shallow trench isolation (STI) regions that separate a first device area from a second device area, said first and second device areas include lightly doped and heavily doped source/drain regions;
an interfacial layer having a first thickness formed on said first device area;
a high k dielectric stack having a second thickness formed on said interfacial layer;
a first gate electrode with a spacer on each of its two sides formed on said high k dielectric stack;
an ultra thin dielectric layer having a third thickness disposed on the second region device area; and
a second gate electrode with a spacer on each of its two sides formed on said ultra thin dielectric layer.
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0. 25. The structure of claim 24 wherein the high k dielectric stack is comprised of one or more of Ta2O5, TiO2, Al2O3, ZrO2, HfO2, Y2O3, L2O3, and their aluminates and silicates.
0. 26. The structure of claim 24 wherein the first thickness is from about 15 to 100 angstroms.
0. 27. The structure of claim 24 wherein the ultra thin dielectric layer is comprised of silicon oxide or silicon oxynitride with an effective oxide thickness of less than about 10 angstroms.
0. 28. The structure of claim 24 wherein the ultra thin dielectric layer is comprised of silicon oxide.
0. 29. The structure of claim 24 wherein the ultra thin dielectric layer is comprised of silicon oxynitride.
0. 30. The structure of claim 24 further comprising an interfacial layer formed overlying the first area.
0. 31. The structure of claim 30 wherein the interfacial layer is comprised of silicon nitride, silicon oxide, or silicon oxynitride.
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This application is a continuation of U.S. Ser. No. 10/282,387, filed Oct. 29, 2002 now U.S. Pat No. 6,706,581.
The present invention relates to a method of semiconductor manufacturing. In particular, the method involves forming two or more gate dielectric layers comprised of different materials during the fabrication of integrated circuits for system on a chip (SOC) technology.
Complimentary metal oxide semiconductor (CMOS) field effect transistor (FET) technology is being driven to smaller gate electrode sizes by a constant demand for higher performance. As stated in an article “Outlook on New Transistor Materials” by L. Peters in Semiconductor International, Oct. 1, 2001 edition, the next generation 70 nm and 50 nm technology nodes will need new gate dielectric materials in order to accommodate a shrinking gate size. A high k dielectric option comprised of a metal oxide is a leading candidate to replace the traditional oxide or oxynitride layer. A higher k value in materials such as Ta2O5, TiO2, Al2O3, ZrO2, HfO2, Y2O3, L2O5 an their aluminates and silicates will enable an increase in the physical dielectric thickness to suppress tunneling current which causes a high gate leakage current in transistors. The high k dielectric material can be formed as an amorphous layer or as a monocrystalline layer. The interfacial layer for the gate dielectric includes oxides, nitrides, oxynitrides, and aluminates. In some cases an interfacial layer is omitted and the gate dielectric material is formed directly on silicon.
The thickness of the gate oxide is critical to the performance of the device. There is a constant need for thinner oxides to allow a higher speed device with lower power consumption. Current technology requires gate oxide thicknesses of about 50 Angstroms or less. For ultra thin silicon dioxide gates, leakage current will increase tremendously as thickness is reduced. This will cause a large current in the standby mode (IOFF) and a large standby power consumption, thereby making products with these devices commercially unacceptable. Thus, new gate dielectric materials are required to suppress gate leakage as the gate dielectric thickness approaches 20 nm or less.
With the introduction of system on a chip (SOC) technology, there is a need to form multiple gate dielectric thicknesses on a substrate to enable different functions to perform simultaneously. For example, circuits for I/O connections, high performance devices, and low power devices must be fabricated on the same substrate. While low power circuits currently require an effective gate oxide thickness (EOT) of 12 to 15 Angstroms and high performance circuits need an EOT in the range of 8 to 12 Angstroms, the IC industry predicts the driver for high k dielectrics will be the low power application with an estimated EOT=1.8 nm in 2005. Silicon oxynitride (SiON) can function adequately as the gate dielectric for high performance devices until 2005, but for low power devices the switch to high k dielectrics must occur for an EOT<17 Angstroms in order to satisfy the leakage requirements.
A method for forming dual gate oxide layers having different thicknesses is described in U.S. Pat. No. 6,265,325 in which a field oxide separates two device areas. After a thermal oxide layer is grown and a polysilicon layer is deposited, a photoresist mask is used to selectively uncover the substrate in one device area. A second oxide layer is grown that is thinner than the first oxide. Then a second polysilicon layer is formed over both device areas. A planarization step is employed to make the second polysilicon layer coplanar with the first polysilicon layer.
Another method for fabricating a dual oxide gate structure is provided in U.S. Pat. No. 5,960,289. An oxide in the range of 50 to 240 Angstroms thick is grown between shallow trench isolation (STI) regions and is protected by subsequently depositing a thin silicon oxynitride (SiON) layer. A photoresist layer is coated and patterned and serves as an etch mask for selectively removing the SiO2 and SiON over one device region. A thin oxide which is 20 to 60 Angstroms thick is then grown over the exposed device region while SiON prevents any additional oxide growth on the other device region. This prior art and the previous case do not address extendibility to gate dielectric thicknesses less than 20 Angstroms where high k dielectric materials will be needed.
Related U.S. Pat. Nos. 6,159,782 and 6,248,675 introduce a high k dielectric approach for manufacturing an N-channel MOSFET and a P-channel MOSFET on the same substrate. High temperature processes such as activation anneal of implanted ions and silicidation anneal are performed on a dummy gate electrode and sacrificial gate dielectric so as to preserve the integrity of a Ta2O5 high k dielectric that is deposited later and is sensitive to temperatures over 800° C. Once the dummy gate electrode is removed by etching to form a gate opening, a conformal layer of SiON is deposited followed by a conformal layer of Ta2O5. The opening is filled with amorphous silicon, planarized, and is then annealed at <600° C. to produce a permanent gate electrode. However, the method does not teach how to form a dielectric layer for a high performance device and a high k dielectric layer for a low power device on the same substrate for a SOC application.
Therefore, a method is needed whereby a gate dielectric layer with an EOT of less than 10 nm for a high performance device and a high k dielectric layer with an EOT preferably <10 nm for a low power device can be formed on the same substrate for current and future SOC applications.
An objective of the present invention is to provide a method of forming a SiON dielectric layer and a high k dielectric layer on the same substrate during the fabrication of a semiconductor device, micro-electromechanical (MEMS) device, or other device requiring the formation of a gate electrode on a substrate.
A further objective of the present invention is to provide a method of forming a high k dielectric layer that is scalable to the 70 nm and 50 nm technology nodes, preferably with an EOT that is <1.8 nm for a low power device.
A still further objective of the present invention is to provide a dual gate dielectric scheme that is compatible with a conventional dual or triple thickness SiO2 process.
A still further objective is to provide an efficient, low cost dual gate dielectric process in which the high k dielectric layer can be annealed simultaneously with the growth of the second dielectric layer.
These objectives are achieved by first providing a substrate with device areas separated by regions of insulating material such as STI features. In the first embodiment, an interfacial layer comprised of SiO2, SiON, or Si3N4 is deposited on the substrate. A high k dielectric material is then deposited by a chemical vapor deposition (CVD), metal-organic CVD (MOCVD), or atomic layer CVD (ALD) process. The high k dielectric material is selected from a group of metal oxides including Ta2O5, TiO2, Al2O3, ZrO2, HfO2, Y2O3, L2O3 and their aluminates and silicates. The high k dielectric material may comprise a single layer of one metal oxide or several layers including two or more metal oxides. A photoresist is coated and patterned on the high k dielectric layer to uncover the substrate in a region that will form the high performance device. After the high k dielectric and interfacial layers are removed in exposed regions, the photoresist is stripped and the substrate is cleaned. An ultra thin SiON layer with an EOT of preferably <10 nm is then deposited by using a silicon source gas in combination with NH3, NO or N2 with O2. During the deposition of the second dielectric layer, the high k dielectric layer is annealed in an in-situ process. A post-deposition anneal involving NH3 or a nitrogen containing gas may be added to further reduce leakage current and lower EOT. Conventional processing is followed to complete the construction of a MOSFET that is a low power device from the region containing the high k dielectric layer and a MOSFET that is a high performance device from the region containing the SiON dielectric layer.
In a second embodiment, a substrate is provided in which STI regions separate device areas that will become a low power device, a high performance device, and an I/O device. An interfacial layer comprised of SiON, Si3N4 or SiO2 is deposited on the substrate. A high k dielectric material is then deposited by a CVD, MOCVD, or ALD process. The high k dielectric material is selected from a group metal oxides and their aluminates and silicates described in the first embodiment. The high k dielectric material may comprise a single layer of one metal oxide or several layers including two or more metal oxides. A photoresist is coated and patterned on the high k dielectric layer to uncover the substrate in a region that will form the high performance device and which will form the I/O device. After the high k dielectric and interfacial layers are removed from exposed regions, the photoresist is stripped and the substrate is cleaned. An ultra thin SiON layer with an EOT of preferably <10 nm is then deposited by using a silicon source gas in combination with NH3, NO or N2 with O2. During the deposition of the second dielectric layer that will become part of the high performance device, the high k dielectric layer is annealed. A second photoresist is then coated and patterned to expose the high k dielectric layer above the I/O device area. An etch selectively removes the SiON layer over the third device area. After a photoresist strip and a cleaning step, an oxide layer is grown on the third device area to form a gate dielectric layer with a thickness that is consistent with an I/O device.
The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the present invention.
The present invention provides a method for forming a high k dielectric layer and an SiON dielectric layer on the same substrate. In the first embodiment, the high k dielectric layer is incorporated into a low power device and the SiON dielectric layer is incorporated into a high performance device.
While the drawings in
An interfacial layer 15 is deposited on substrate 11 to a thickness between 0 and 30 Angstroms and consists of a material such as SiO2, SiON, or silicon nitride. The interfacial layer 15 is preferably formed by a rapid thermal process (RTP) in a temperature range of about 500° C. to 1000° C. although a plasma enhanced CVD or a low pressure CVD can also be used for the deposition. When the layer is SiON, the RTP preferably involves a silane or silicon containing gas as well as NH3. Optionally, the RTP may include N2O, O2 or NO in combination with NH3, or N2 and O2 instead of NH3.
A high k dielectric stack 16 is then formed on the interfacial layer 15 by a CVD, MOCVD, or ALD process. The interfacial layer may not be required in some cases but generally an interfacial layer 15 is preferred in order to enable a smooth interface between the substrate 11 and the high k dielectric stack 16. A pre-gate cleaning step which is suitable for high-k deposition can be inserted before the high k dielectric stack 16 deposition. Such a cleaning step typically involves a hydrophilic or hydrophobic technique that is well known to those skilled in the art. The high k dielectric stack 16 may consist of a single layer or may be two or more layers comprising one or more materials selected from the group including Ta2O5, TiO2, Al2O3, ZrO2, HfO2, Y2O3, L2O3 and their aluminates and silicates. A preferred thickness of the high k dielectric stack 16 is from about 15 to 100 Angstroms.
Referring to
Referring to
An ultra thin dielectric layer 18 is then grown on device area 14 and during the process the high k dielectric stack 16 is annealed. When dielectric layer 18 is silicon oxynitride, layer 18 preferably has an EOT<10 nm. Layer 18 also covers STI regions 12 that are exposed after removal of interfacial layer 15 and high k dielectric stack 16. The annealing is a rapid thermal process and is performed in a temperature range of about 500° C. to 1000° C. for about 10 to 500 seconds and may include O2, N2, NO, NH3, or any combination of the aforementioned gases. When only an oxygen ambient is employed, a dielectric layer 18 comprised of SiO2 is formed instead of SiON. The annealing improves the quality of the high k dielectric material and lowers the leakage current in the MOSFET that is formed from the dielectric stack 16
For example, when the high k dielectric stack 16 is a layer of HfO2 that is deposited on an SiON interfacial layer that has been formed under conditions including ammonia at 560° C., the top curve 60 in the plot depicted in
When the high k dielectric stack 16 is comprised of ZrO2 and Al2O3 layers, then an anneal with NH3 is especially effective in reducing the leakage current as illustrated in
Referring to
Referring to
The advantage of the first embodiment over prior art is that MOSFET 26 contains a high k dielectric layer 16 that enables the low power device to meet future requirements of <1.8 nm EOT. Gate leakage current has been suppressed to an acceptable level. Furthermore, on the same substrate, a MOSFET 27 has been fabricated which contains a SiON gate dielectric layer that is extendable to <1 nm EOT to satisfy future requirements for 50 and 70 nm technology nodes. The method can be readily implemented in a manufacturing scheme at a minimal cost, especially when the high k dielectric anneal step is performed in-situ with the silicon oxynitride deposition of the second gate dielectric layer.
In a second embodiment, a method is provided for forming three distinct devices on the same substrate. A high k dielectric layer is incorporated in a low power device, and silicon oxynitride or SiO2 layers are incorporated in high performance and I/O devices. While the drawings in
Referring to
An interfacial layer 36 is deposited on substrate 31 to a thickness between about 0 and 15 Angstroms and consists of a material such as SiO2, SiON, or silicon nitride. The interfacial layer 36 is preferably formed by a rapid thermal process (RTP) in a temperature range of between 500° C. and 1000° C. although a plasma enhanced CVD or a low pressure CVD can also be used for the deposition. When the layer 36 is silicon oxynitride, the RTP preferably involves a silane or silicon containing source gas as well as NH3. Optionally, the RTP may include N2O, O2 or NO in combination with NH3, or N2 and O2 instead of NH3.
A high k dielectric stack 37 is then formed on the interfacial layer 36 by a CVD, MOCVD, or ALD process. The interfacial layer may not be required in some cases but generally an interfacial layer 36 is preferred in order to enable a smooth interface between the substrate 31 and the high k dielectric stack 37. A pre-gate cleaning step which is suitable for high-k deposition can be inserted before the high k dielectric stack 37 deposition. Such a cleaning step typically involves a hydrophilic or hydrophobic technique that is well known to those skilled in the art. The high k dielectric stack 37 may consist of a single layer or may be two or more layers comprising one or more materials selected from the group including Ta2O5, TiO2, Al2O3, ZrO2, HfO2, Y2O3, L2O3 and their aluminates and silicates. A preferred thickness of the high k dielectric stack 37 is from about 15 to 100 Angstroms.
Referring to
Referring to
An ultra thin dielectric layer 39 is then grown on device areas 34, 35 and during the process the high k dielectric stack 37 is annealed. When the dielectric layer 39 is silicon oxynitride, layer 39 preferably has an EOT<10 nm. Layer 39 also covers STI regions 32 that are exposed after removal of interfacial layer 36 and high k dielectric stack 37. The annealing is a rapid thermal process and is performed in a temperature range of about 500° C. to 1000° C. for about 10 to 500 seconds and may include O2, N2, NO, NH3, or any combination of the aforementioned gases. When only an oxygen ambient is employed, a dielectric layer 39 comprised of SiO2 is formed instead of SiON. The annealing improves the quality of the high k dielectric material and lowers the leakage current in the MOSFET that is formed from the dielectric stack 37.
For example, when the high k dielectric stack 37 is a layer of HfO2 that is deposited on a SiON interfacial layer that has been formed under conditions involving ammonia at 560° C., the top curve 60 in the plot depicted in
When the high k dielectric stack 37 is comprised of ZrO2 and Al2O3 layers, then an anneal with NH3 is especially effective in reducing the leakage current as illustrated in
Referring to
Referring to
Referring to
The method is compatible with dual oxide dielectric thicknesses since dielectric layers 39 and 41 may both be SiO2 and have differing thicknesses. Those skilled in the art will recognize that the method can be expanded to include three or more gate dielectric layers with differing SiO2 thicknesses by repeating the steps depicted in
An advantage of the second embodiment over prior art is that a device containing a high k dielectric layer which enables the low power device to meet future requirements of <1.8 nm EOT is formed on the same substrate with a high performance device having a gate dielectric EOT that is extendable to <1 nm for 50 nm and 70 nm technology nodes. Furthermore, an I/O device that provides greater SOC capability is also formed on the same substrate. Gate leakage current has been suppressed to an acceptable level in the low power device. The method can be readily implemented in a manufacturing scheme at a minimal cost, especially when the high k dielectric anneal step is performed in-situ with the deposition of the second gate dielectric layer.
While this invention has been particularly shown and described with reference to, the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention.
Chen, Shih-Chang, Chen, Chi-Chun, Yao, Liang-Gi, Wang, Ming-Fang, Yang, Chih-Wei, Hou, Tou-Hung
Patent | Priority | Assignee | Title |
9373501, | Apr 16 2013 | International Business Machines Corporation | Hydroxyl group termination for nucleation of a dielectric metallic oxide |
9831084, | Apr 16 2013 | International Business Machines Corporation | Hydroxyl group termination for nucleation of a dielectric metallic oxide |
Patent | Priority | Assignee | Title |
5960289, | Jun 22 1998 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region |
6048769, | Feb 28 1997 | Intel Corporation | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
6087236, | Nov 24 1998 | Intel Corporation | Integrated circuit with multiple gate dielectric structures |
6144063, | Mar 25 1998 | Advanced Micro Devices, Inc. | Ultra-thin oxide for semiconductors |
6159782, | Aug 05 1999 | GLOBALFOUNDRIES Inc | Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant |
6211034, | Apr 14 1997 | Texas Instruments Incorporated | Metal patterning with adhesive hardmask layer |
6248675, | Aug 05 1999 | GLOBALFOUNDRIES Inc | Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant using lowered temperatures |
6265325, | Apr 26 1999 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD ; AVAGO TECHNOLOGIES GENERAL IP PTE LTD | Method for fabricating dual gate dielectric layers |
6309936, | Sep 30 1998 | Advanced Micro Devices, Inc. | Integrated formation of LDD and non-LDD semiconductor devices |
6362059, | Jun 09 2000 | NEC Electronics Corporation | Production of a semiconductor device having a P-well |
6406956, | Apr 30 2001 | Taiwan Semiconductor Manufacturing Company | Poly resistor structure for damascene metal gate |
6420742, | Jun 16 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Ferroelectric memory transistor with high-k gate insulator and method of fabrication |
6436749, | Sep 08 2000 | International Business Machines Corporation | Method for forming mixed high voltage (HV/LV) transistors for CMOS devices using controlled gate depletion |
6455330, | Jan 28 2002 | Taiwan Semiconductor Manufacturing Company | Methods to create high-k dielectric gate electrodes with backside cleaning |
6468851, | Jan 02 2002 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating CMOS device with dual gate electrode |
6482726, | Oct 17 2000 | Advanced Micro Devices, Inc. | Control trimming of hard mask for sub-100 nanometer transistor gate |
6495422, | Nov 09 2001 | Taiwan Semiconductor Manfacturing Company | Methods of forming high-k gate dielectrics and I/O gate oxides for advanced logic application |
6524910, | Sep 27 2000 | Chartered Semiconductor Manufacturing LTD | Method of forming dual thickness gate dielectric structures via use of silicon nitride layers |
6528858, | Jan 11 2002 | GLOBALFOUNDRIES U S INC | MOSFETs with differing gate dielectrics and method of formation |
6597046, | Nov 24 1998 | Intel Corporation | Integrated circuit with multiple gate dielectric structures |
6638877, | Nov 03 2000 | Texas Instruments Incorporated | Ultra-thin SiO2using N2O as the oxidant |
6713353, | Apr 26 1999 | Renesas Electronics Corporation | Method of manufacturing a semiconductor integrated circuit device |
6727130, | Apr 11 2001 | Samsung Electronics Co., Ltd. | Method of forming a CMOS type semiconductor device having dual gates |
6730566, | Oct 04 2002 | Texas Instruments Incorporated | Method for non-thermally nitrided gate formation for high voltage devices |
6759302, | Jul 30 2002 | Taiwan Semiconductor Manufacturing Company | Method of generating multiple oxides by plasma nitridation on oxide |
20060091469, |
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