Transitioning from startup code to application code during initialization of a processor based device

Abstract

Method and apparatus for initializing a processor based device having a processor that controls an electrical load, such as a motor. The electrical load is initially operationally controlled using startup code executed by the processor. processor control of the electrical load is next temporarily released so that the electrical load operates in an open control mode while the startup code is displaced with application code during a “brain transplant” operation. processor operational control of the electrical load is thereafter resumed using the application code and the device is placed in an operational ready mode. The apparatus preferably comprises a data storage device and the electrical load preferably comprises a spindle motor configured to rotate a data storage medium on which the application code is stored, as well as an actuator motor which supports a data transducing head used to access the application code.

Description

1 00 100. Preferably, such scheme also should ensure that subsequent upgrades to the startup code and/or the application code maintain the necessary compatibility between these respective code sets to prevent a failure condition (a “crash”) in the device during the initialization process.

Accordingly, preferred embodiments of the present invention provide a novel initialization approach that is descriptively referred to as a “brain transplant” technique. Instead of maintaining processor control of the active subsystems (electrical loads) while phasing out the startup code and phasing in the application code, the transplant approach generally involves establishing a short “blackout” period during which processor control is released, the spindle motor 106 and the VCM 116 are left operating in an open control mode, and the respective code systems are quickly swapped. Such a sequence is generally represented by FIG. 8.

As shown by Step 1 in FIG. 8, upon receipt of a command to initialize the device 100, the startup code resident in the boot ROM 136 is loaded into a first memory location 220. This first memory location, MEM 1, represents a memory space that is used to supply the instructions executed by the processor 132; in other words, the processor 132 is configured to execute whatever is loaded into MEM 1.

The physical embodiment of the MEM 1 location 220 will vary depending on the hardware configuration of the device 100 as well as the code itself; for purposes of the presently discussed embodiment, with reference again to FIG. 3 it will be contemplated that the MEM 1 location 220 preferably includes portions of the tightly-coupled RAM 134 and the buffer 140, but is not so limited.

During step 2 in FIG. 8, the startup code is sequentially executed by the processor 132. Resulting operations can include an initialization of various electronic components, a spinup operation whereby the motor control circuit 148 is instructed to accelerate the discs 108 to the-operational velocity, and movement of the heads 112 out over the disc recording surfaces by the servo loop 150. The heads 112 are moved to the associated guard tracks and the application code is transferred (via preamp 144 and read/write channel 142) to a second memory location 222 (MEM 2) of the device 100.

The MEM 2 location 222 preferably represents a staging area where code can be stored but not necessarily executed by the processor; thus, MEM 2 represents a location where code can be temporarily stored pending transfer to MEM 1. Preferably, the MEM 2 location 222 represents portions of the buffer 140, although this is not limiting. As shown in FIG. 8, the HDA 101 is under processor control (via the startup code) during Step 2.

Because of programming space constraints, the startup code preferably is configured to provide sufficient control of the servo and spindle control circuits to successfully transfer the application code to the MEM 2 location 222, but may not include all of the available adaptive features and aspects (e.g., adaptive parameters of the filter 152, FIG. 4) that are employed during normal operation.

Once the application code has been successfully loaded into the MEM 2 location 222, the sequence moves to Step 3, wherein the brain transplant operation occurs. Generally, during this step processor control of the HDA 10.1 is suspended (released), the application code (or at least an initial portion thereof) is moved to the MEM 1 location 220, and the startup code is displaced (removed, overwritten, or otherwise ignored) from the MEM 1 location.

Once the transfer of the application code to the MEM 1 location 220 is successfully completed, Step 4 of FIG. 8 commences with the resumption of processor control and the normal operation of the device under the control of the application code, including data transfer operations between the host and the discs 108. Step 4 continues until the device is deactivated, after which the foregoing steps are repeated upon receipt of the next initialization command.

It will be recognized based on the foregoing discussion that placing the spindle motor 106 and VCM 116 into a suspended processor control configuration, even for a short time, will likely result in some amount of spindle motor speed variation and VCM position drift. Position and timing synchronization may be lost and, if sufficient care is not taken, damage to the device I 00 may occur.

In preferred embodiments, the amount of speed variation in the spindle motor 106 during the blackout period is reduced by having the processor 132 load a predetermined current limit value to the DAC 210 (FIG. 7) and instructing the control logic block 148 (FIG. 6) to switch from embedded motor speed control to bemf-based commutation control of the motor 106.

This bemf-based commutation control relies on the gross detection of the zero crossing points to time the next commutation state transitions (i.e., the application of the next current pulses). Thus, motor speed will be maintained to a degree since the circuitry will adjust the timing of the pulses, but the magnitudes of the current pulses applied to the commutation states will generally remain fixed in relation to the pre-established current limit value.

In this way, spindle motor speed may drift during the blackout period by some amount (e.g., ±20% of nominal speed), but the motor will still be operating in a range sufficient to maintain the aerodynamic flight of the heads 112 and to enable a relatively fast re-synchronization with the servo timing marks after processor control is resumed.

Preventing or reducing VCM drift is preferably carried out in a number of alternative ways. In one preferred approach, just before disengagement of the processor the average amount of bias current being applied at that point to nominally maintain the selected head 112 over the corresponding guard band track is determined. The processor 132 then commands this value to the coil driver 158 (FIG. 4) so that this same amount of current continues to be supplied to the coil 114 while the processor is temporarily disengaged.

In another approach, just before disengagement of the processor 132 a seek operation is commanded to move the actuator 110 against an inner or outer limit stop (mechanisms used to limit the stroke of the actuator 110 as shown at 224, 226 in FIG. 1). The processor 132 then commands a modest current value with an appropriate orientation so that the actuator 110 remains safely biased against the selected limit stop 224, 226 by the applied current.

In another alternative approach, the actuator 110 is moved to an area across the discs 108 previously determined to have little or no bias forces (due to flex circuit or windage effects), and either little or no current is applied to the coil 114 so that the heads 112 remain in the same general vicinity during the black out period.

In a worst case scenario, the actuator 110 is commanded to park the heads (such as on the landing zones in FIG. 1 at the innermost diameters of the discs 108 or on a ramp loading system at the outermost diameters of the discs) and the actuator 110 is securely latched with the latch 118. Parking the heads 112 and latching the actuator 110 substantially guarantees that the actuator 110 will not drift during the blackout period, but does increase the time to place the device 100 in the final operational ready state upon resumption of processor control.

Regardless of the particular alternatives that are selected to effect open mode control, it will be noted that the spindle motor 106 and the VCM 116 continue to operate during the blackout period, but without processor intervention. This allows the code swap to occur quickly without the need to perform processor operational commands for the rest of the device 100 until after the swap is completed.

It will be noted that the startup code is configured to place the various electrical loads in the aforedesrcribed aforedescribed open control mode as the substantially finals. final executed steps of the startup code. The last instruction of the startup code preferably instructs the processor 132 to perform the code swap and execute the first instruction of the loaded application code.

The initial instructions of the loaded application code operate to enable the processor to quickly resume control of the electrical loads. While the particular steps will depend upon the configuration of the device 100, in a preferred embodiment the application code generally first instructs the spindle motor control circuitry 148 to resume sensor based motor speed control.

This results in the control logic block 176 determining the actual motor velocity in relation to the zero crossing (ZX) signals from the bemf detection circuitry 180 and adjusting the DAC 210 to bring the motor velocity back up to a value approximating the operational velocity.

Next, the servo loop 150 initiates a synchronization of the demodulation circuit 146 (a “demod sync”), which involves decoding the Gray code (track address) and the timing marks to acquire and thereafter continually track the radial and angular position of the selected head with respect to the associated disc 108. More particularly, the demod sync operation enables the servo loop hardware to locate (and thereafter track) the head 112 with respect to the associated disc 108.

When the blackout period involves parking the actuator 110 or biasing the actuator against one of the limit stops 224, 226, it may be necessary to first advance the heads 112 out over the disc recording surfaces in order to allow the servo loop 150 to begin transducing the servo sectors 122 on the disc 108.

Depending upon the configuration of the device 100, it may take multiple revolutions of the discs 108 and the successful detection of multiple index positions before the demod sync operation is declared successful. In the meantime, after the detection of just a few timing marks, an accurate determination of the existing rotational velocity of the motor 106 can be achieved. Thus, the processor switches over to embedded motor based control during the demod sync operation.

Finally, once both the motor control circuitry 148 indicates that both the spindle motor 106 and VCM 116 have acquired synchronization and are in a ready state, the processor proceeds with remaining portions of the application code and the device 100 enters normal operation (step 4 of FIG. 8).

Assuming that the code swap can be carried out in around 0.5 milliseconds, ms (0.5×10⁻³ seconds), and the demod sync operation can be successfully carried out in around another 24.5 ms (i.e., a little over four revolutions of the discs 108 at a rotational speed of 10,000 rpm, or about 6 ms/rev), the total transition from startup to application code can be completed in about 25 ms. This has been found to be one or more orders of magnitude faster than existing phased-in code swapping approaches that attempt to maintain processor control throughout, and represents significant reductions in overall device initialization time.

FIG. 9 provides a flow chart for a DEVICE INITIALIZATION routine 250, generally representative of steps carried out in accordance with preferred embodiments of the present invention to initialize the device 100. It is understood that the device 100 is initially in a deactivated state (i.e., in a turned-off or powered down sleep mode).

At step 252, an initialization command is received, resulting in the loading and execution of the startup code (from ROM 136 to MEM 1, FIG. 8) by the processor 132.

During the execution of the startup code, as shown by step 254, the processor 132 initiates processor controlled operation of one or more electrical loads of the device (in this case the spindle motor 106, the VCM 116, the associated control circuitry 148, the read/write channel 142, etc.).

At step 256, the application code is preferably accessed and loaded into a second memory location (MEM 2, FIG. 8) pending transfer. At step 258, processor control of the electrical load(s) is released, preferably as discussed above, while the startup code is displaced by the application code. Finally, at step 260 processor control of the electrical load(s) is resumed using the loaded application code and the device enters normal operation. The process thereafter ends at step 262.

While presently preferred embodiments have been directed to a data storage device, the present invention as claimed below is riot not necessarily so limited. Rather, any number of different types of processor based devices that utilize electrical loads that are controlled by the processor (such as lasers or other light sources, robotic systems, capacitive and inductive charging systems, other types of motor based systems, etc.) are contemplated as being well within the scope of the present disclosure.

It will now be understood that the present invention (as embodied herein and as claimed below) is generally directed to a method and apparatus for initializing a processor based device 100 having a processor 132 that controls an electrical load, such as a motor 106, 116.

In accordance with preferred embodiments, the method preferably comprises controlling the electrical load with startup code executed by the processor. Processor control is next released so that the electrical load operates in an open control mode while the startup code is displaced with application code. Processor control of the electrical load is then reinstated using the application code.

Preferably, the startup code is supplied from a boot read only memory (ROM) 136, and the controlling step comprises loading the startup code into a first memory location 220 accessed by the processor. Moreover, the controlling step further preferably comprises loading the application code into a second memory location 222 accessible by the processor.

The electrical load preferably comprises a spindle motor 106 that supports a data storage medium 108, so that the controlling step comprises using the motor to rotate the data storage medium at an operational velocity and retrieving the application code from the rotating data storage medium.

The apparatus preferably comprises an electrical load 106, 116, a memory location 134, 140, 220, and a programmable processor 132 coupled to the memory location and adapted to control the electrical load

During an initialization process 250 the processor executes startup code loaded into the memory location to initiate operational control of the load, temporarily releases operational control of the electrical load so that the electrical load continues to operate in an open control mode while the startup code in the memory location is displaced with application code, and resumes operational control of the electrical load using the application code.

For purposes of the appended claims and consistent with the foregoing discussion, the term “open control mode” will be understood to include a mode of operation whereby the electrical load continues to operate using settings established by the processor prior to the release of processor control and without further processor regulation or intervention, a mode that is not under processor control or simply a mode that is not under any control.

The term “operational control” will be understood to include a mode of operation whereby the processor engages in continual active regulation, intervention or verification to maintain the continued operation of the load, or simply a mode where the processor controls the load.

It will be clear that the present invention is well adapted to attain the ends and advantages mentioned as well as those inherent therein. While presently preferred embodiments have been described for purposes of this disclosure, numerous changes may be made which will readily suggest themselves to those skilled in the art and which are encompassed in the appended claims.

Claims

1. A method, comprising:

controlling an electrical load with a first code executed by a processor;

releasing processor control so that the electrical load operates in an open control mode while the first code is displaced with a second code; and

reinstating processor control of the electrical load using the second code.

2. The method of claim 1, wherein the first code of the controlling step is supplied from a boot read only memory (ROM).

3. The method of claim 1, wherein the controlling step comprises loading the first code into a first memory location accessed by the processor.

4. The method of claim 3, wherein the controlling step further comprises loading the second code into a second memory location accessible by the processor.

5. The method of claim 4, wherein the releasing step comprises moving the second code from the second memory location into the first memory location, thereby displacing the first code from the first memory location.

6. The method of claim 1, wherein the electrical load is a motor.

7. The method of claim 6, wherein the motor supports a data storage medium, and wherein the controlling step comprises using the motor to rotate the data storage medium at an operational velocity and retrieving the second code from the rotating data storage medium.

8. The method of claim 1 wherein the processor operationally controls the electrical load.

9. The method of claim 1, wherein at least one control signal is applied to the electrical load during the open control mode of the releasing step.

10. A method, comprising:

using a processor to execute startup code loaded into a memory location to initiate operational control of an electrical load;

continuing to operate the electrical load while processor operational control of the electrical load is temporarily suspended to load application code to the memory location; and

resuming operational control of the electrical load using the application code.

11. The method of claim 10, wherein the startup code of the using step is supplied from a boot read only memory (ROM).

12. The method of claim 10, wherein the memory location of the using step is characterized as a first memory location, and wherein the using step further comprises loading the application code into a second memory location accessible by the processor.

13. The method of claim 12, wherein the continuing step comprises moving the application code from the second memory location into the first memory location, thereby displacing the startup code from the first memory location.

14. The method of claim 10, wherein the electrical load comprises a motor supporting a data storage medium, and wherein the using step comprises energizing the motor to rotate the data storage medium at an operational velocity and retrieving the application code from the rotating data storage medium.

15. The method of claim 14, wherein the using step further comprises using the startup code to energize an actuator motor to bring a data transducing head into alignment with a track defined on the data storage medium, and utilizing the head to transduce the application data from said track.

16. An apparatus, comprising:

an electrical load;

a memory location; and

a programmable processor coupled to the memory location and adapted to control the electrical load, wherein during an initialization process the processor executes startup code loaded into the memory location to initiate operational control of the load, temporarily releases operational control of the electrical load so that the electrical load continues to operate in an open control mode while application code is loaded to the memory location, and resumes operational control of the electrical load using the application code.

17. The apparatus of claim 16, further comprising a boot read only memory (ROM) which stores the startup code, wherein the startup code is loaded from the boot ROM to the memory location for execution by the processor.

18. The apparatus of claim 16, wherein the memory location of the using step is characterized as a first memory location, and wherein the apparatus further comprises a second memory location accessible by the processor and into which the processor loads the application code.

19. The apparatus of claim 16, wherein the electrical load comprises a motor supporting a data storage medium, and wherein the execution of the startup code by the processor results in the energizing of the motor to rotate the data storage medium at an operational velocity.

20. The apparatus of claim 19, further comprising an actuator motor coupled to a data transducing head, and wherein the execution of the startup code by the processor further results in the energizing of the actuator motor to bring the head into alignment with a track defined on the data storage medium, the head transducing the application data from said track.

21. A method, comprising:

measuring a parameter from a center tap node of an impedance element in an electrical circuit;

providing power to the electrical circuit with the impedance element as a function of the parameter of the center tap node and an execution of a first application code by a processor;

at least limiting execution of the first application code by the processor;

providing, while execution of the first application code is at least limited, power to the impedance element as a function of the parameter of the center tap node;

storing a second application code to be used in place of the first application code; and

providing power to the electrical circuit with the impedance element as a function of the parameter and an execution of the second application code by the processor.

22. The method of claim 21, wherein the impedance element is an inductive element.

23. The method of claim 21, wherein the center tap node is located between at least two elements of the same impedance type and arranged in series and wherein the step of providing power includes providing a voltage across the two elements of the same impedance type.

24. The method of claim 21, further including the steps of monitoring current provided to the electrical circuit and limiting power provided to the impedance element in response to the monitored current.

25. The method of claim 21, wherein the first application code includes initialization steps for providing power to the impedance element, the initialization steps including

applying a first power-providing profile to the impedance element upon startup;

detecting a property of the impedance element exceeding a threshold;

applying, in response to the threshold having been exceeded, an intermediate power-providing profile to the impedance element;

detecting that the property of the impedance element is approaching a final value; and

maintaining, in response to the detection of the property of the impedance element approaching a final value, the detected property at the final value by controlling the current provided to the impedance element.

26. The method of claim 21, wherein the parameter measured from the center tap node is maintained within a predetermined tolerance.

27. A method comprising:

detecting an initial state of an impedance element of a storage device;

applying, in response to the initial state, startup power to the impedance element of the storage device;

modulating the applied startup power to limit current provided to the impedance element according to a current-limit value;

detecting a parameter of the impedance element; and

modifying the current-limit value in response to the detected parameter.

28. The method of claim 27, wherein the impedance element is an inductance.

29. The method of claim 27, further including the step of updating an application code that controls the modification of the current limit value.

30. The method of claim 27, further including the step of updating a first application code that controls the application of power to the storage device by

halting execution of the first application code;

controlling power to the impedance element of the storage device in an open control mode while the execution of the first application code is halted;

replacing the first application code with a second application code; and

executing the second application code.

31. A storage device, comprising:

a non-volatile storage circuit;

an electrical impedance circuit;

a current sensor configured and arranged to sense current through the electrical impedance circuit;

a control circuit configured and arranged to provide power to the electrical impedance circuit; and

a programmable processor adapted to,

during an initialization procedure, execute a first code that

receives an indication of sensed current from the current sensor, and

limits, in response to the sensed current, power provided by the control circuit,

after the initialization procedure,

apply power to the electrical impedance circuit by placing the control circuit into a closed control mode configured to maintain a parameter of the electrical impedance circuit,

place the control circuit into an open control mode for providing power to the electrical impedance circuit,

modify the first code, while the control circuit is in the open control mode, and

execute the modified first code.

32. The storage device of claim 31, wherein the electrical impedance circuit is an inductive circuit.

33. The storage device of claim 32, wherein the electrical impedance circuit includes two elements arranged in series.

34. The storage device of claim 32, wherein the electrical impedance circuit includes two elements arranged in series and a center tap representing a circuit node between the two elements, and wherein the programmable processor is further adapted to monitor a voltage on the center tap and to limit, in response to the monitored voltage on the center tap, power provided by the control circuit.