Method and apparatus for initializing a processor based device having a processor that controls an electrical load, such as a motor. The electrical load is initially operationally controlled using startup code executed by the processor. processor control of the electrical load is next temporarily released so that the electrical load operates in an open control mode while the startup code is displaced with application code during a “brain transplant” operation. processor operational control of the electrical load is thereafter resumed using the application code and the device is placed in an operational ready mode. The apparatus preferably comprises a data storage device and the electrical load preferably comprises a spindle motor configured to rotate a data storage medium on which the application code is stored, as well as an actuator motor which supports a data transducing head used to access the application code.
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1. A method, comprising:
controlling an electrical load with a first code executed by a processor;
releasing processor control so that the electrical load operates in an open control mode while the first code is displaced with a second code; and
reinstating processor control of the electrical load using the second code.
10. A method, comprising:
using a processor to execute startup code loaded into a memory location to initiate operational control of an electrical load;
continuing to operate the electrical load while processor operational control of the electrical load is temporarily suspended to load application code to the memory location; and
resuming operational control of the electrical load using the application code.
0. 27. A method comprising:
detecting an initial state of an impedance element of a storage device;
applying, in response to the initial state, startup power to the impedance element of the storage device;
modulating the applied startup power to limit current provided to the impedance element according to a current-limit value;
detecting a parameter of the impedance element; and
modifying the current-limit value in response to the detected parameter.
16. An apparatus, comprising:
an electrical load;
a memory location; and
a programmable processor coupled to the memory location and adapted to control the electrical load, wherein during an initialization process the processor executes startup code loaded into the memory location to initiate operational control of the load, temporarily releases operational control of the electrical load so that the electrical load continues to operate in an open control mode while application code is loaded to the memory location, and resumes operational control of the electrical load using the application code.
0. 21. A method, comprising:
measuring a parameter from a center tap node of an impedance element in an electrical circuit;
providing power to the electrical circuit with the impedance element as a function of the parameter of the center tap node and an execution of a first application code by a processor;
at least limiting execution of the first application code by the processor;
providing, while execution of the first application code is at least limited, power to the impedance element as a function of the parameter of the center tap node;
storing a second application code to be used in place of the first application code; and
providing power to the electrical circuit with the impedance element as a function of the parameter and an execution of the second application code by the processor.
0. 31. A storage device, comprising:
a non-volatile storage circuit;
an electrical impedance circuit;
a current sensor configured and arranged to sense current through the electrical impedance circuit;
a control circuit configured and arranged to provide power to the electrical impedance circuit; and
a programmable processor adapted to,
during an initialization procedure, execute a first code that
receives an indication of sensed current from the current sensor, and
limits, in response to the sensed current, power provided by the control circuit,
after the initialization procedure,
apply power to the electrical impedance circuit by placing the control circuit into a closed control mode configured to maintain a parameter of the electrical impedance circuit,
place the control circuit into an open control mode for providing power to the electrical impedance circuit,
modify the first code, while the control circuit is in the open control mode, and
execute the modified first code.
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0. 22. The method of claim 21, wherein the impedance element is an inductive element.
0. 23. The method of claim 21, wherein the center tap node is located between at least two elements of the same impedance type and arranged in series and wherein the step of providing power includes providing a voltage across the two elements of the same impedance type.
0. 24. The method of claim 21, further including the steps of monitoring current provided to the electrical circuit and limiting power provided to the impedance element in response to the monitored current.
0. 25. The method of claim 21, wherein the first application code includes initialization steps for providing power to the impedance element, the initialization steps including
applying a first power-providing profile to the impedance element upon startup;
detecting a property of the impedance element exceeding a threshold;
applying, in response to the threshold having been exceeded, an intermediate power-providing profile to the impedance element;
detecting that the property of the impedance element is approaching a final value; and
maintaining, in response to the detection of the property of the impedance element approaching a final value, the detected property at the final value by controlling the current provided to the impedance element.
0. 26. The method of claim 21, wherein the parameter measured from the center tap node is maintained within a predetermined tolerance.
0. 28. The method of claim 27, wherein the impedance element is an inductance.
0. 29. The method of claim 27, further including the step of updating an application code that controls the modification of the current limit value.
0. 30. The method of claim 27, further including the step of updating a first application code that controls the application of power to the storage device by
halting execution of the first application code;
controlling power to the impedance element of the storage device in an open control mode while the execution of the first application code is halted;
replacing the first application code with a second application code; and
executing the second application code.
0. 32. The storage device of claim 31, wherein the electrical impedance circuit is an inductive circuit.
0. 33. The storage device of claim 32, wherein the electrical impedance circuit includes two elements arranged in series.
0. 34. The storage device of claim 32, wherein the electrical impedance circuit includes two elements arranged in series and a center tap representing a circuit node between the two elements, and wherein the programmable processor is further adapted to monitor a voltage on the center tap and to limit, in response to the monitored voltage on the center tap, power provided by the control circuit.
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Accordingly, preferred embodiments of the present invention provide a novel initialization approach that is descriptively referred to as a “brain transplant” technique. Instead of maintaining processor control of the active subsystems (electrical loads) while phasing out the startup code and phasing in the application code, the transplant approach generally involves establishing a short “blackout” period during which processor control is released, the spindle motor 106 and the VCM 116 are left operating in an open control mode, and the respective code systems are quickly swapped. Such a sequence is generally represented by
As shown by Step 1 in
The physical embodiment of the MEM 1 location 220 will vary depending on the hardware configuration of the device 100 as well as the code itself; for purposes of the presently discussed embodiment, with reference again to
During step 2 in
The MEM 2 location 222 preferably represents a staging area where code can be stored but not necessarily executed by the processor; thus, MEM 2 represents a location where code can be temporarily stored pending transfer to MEM 1. Preferably, the MEM 2 location 222 represents portions of the buffer 140, although this is not limiting. As shown in
Because of programming space constraints, the startup code preferably is configured to provide sufficient control of the servo and spindle control circuits to successfully transfer the application code to the MEM 2 location 222, but may not include all of the available adaptive features and aspects (e.g., adaptive parameters of the filter 152,
Once the application code has been successfully loaded into the MEM 2 location 222, the sequence moves to Step 3, wherein the brain transplant operation occurs. Generally, during this step processor control of the HDA 10.1 is suspended (released), the application code (or at least an initial portion thereof) is moved to the MEM 1 location 220, and the startup code is displaced (removed, overwritten, or otherwise ignored) from the MEM 1 location.
Once the transfer of the application code to the MEM 1 location 220 is successfully completed, Step 4 of
It will be recognized based on the foregoing discussion that placing the spindle motor 106 and VCM 116 into a suspended processor control configuration, even for a short time, will likely result in some amount of spindle motor speed variation and VCM position drift. Position and timing synchronization may be lost and, if sufficient care is not taken, damage to the device I 00 may occur.
In preferred embodiments, the amount of speed variation in the spindle motor 106 during the blackout period is reduced by having the processor 132 load a predetermined current limit value to the DAC 210 (
This bemf-based commutation control relies on the gross detection of the zero crossing points to time the next commutation state transitions (i.e., the application of the next current pulses). Thus, motor speed will be maintained to a degree since the circuitry will adjust the timing of the pulses, but the magnitudes of the current pulses applied to the commutation states will generally remain fixed in relation to the pre-established current limit value.
In this way, spindle motor speed may drift during the blackout period by some amount (e.g., ±20% of nominal speed), but the motor will still be operating in a range sufficient to maintain the aerodynamic flight of the heads 112 and to enable a relatively fast re-synchronization with the servo timing marks after processor control is resumed.
Preventing or reducing VCM drift is preferably carried out in a number of alternative ways. In one preferred approach, just before disengagement of the processor the average amount of bias current being applied at that point to nominally maintain the selected head 112 over the corresponding guard band track is determined. The processor 132 then commands this value to the coil driver 158 (
In another approach, just before disengagement of the processor 132 a seek operation is commanded to move the actuator 110 against an inner or outer limit stop (mechanisms used to limit the stroke of the actuator 110 as shown at 224, 226 in
In another alternative approach, the actuator 110 is moved to an area across the discs 108 previously determined to have little or no bias forces (due to flex circuit or windage effects), and either little or no current is applied to the coil 114 so that the heads 112 remain in the same general vicinity during the black out period.
In a worst case scenario, the actuator 110 is commanded to park the heads (such as on the landing zones in
Regardless of the particular alternatives that are selected to effect open mode control, it will be noted that the spindle motor 106 and the VCM 116 continue to operate during the blackout period, but without processor intervention. This allows the code swap to occur quickly without the need to perform processor operational commands for the rest of the device 100 until after the swap is completed.
It will be noted that the startup code is configured to place the various electrical loads in the aforedesrcribed aforedescribed open control mode as the substantially finals. final executed steps of the startup code. The last instruction of the startup code preferably instructs the processor 132 to perform the code swap and execute the first instruction of the loaded application code.
The initial instructions of the loaded application code operate to enable the processor to quickly resume control of the electrical loads. While the particular steps will depend upon the configuration of the device 100, in a preferred embodiment the application code generally first instructs the spindle motor control circuitry 148 to resume sensor based motor speed control.
This results in the control logic block 176 determining the actual motor velocity in relation to the zero crossing (ZX) signals from the bemf detection circuitry 180 and adjusting the DAC 210 to bring the motor velocity back up to a value approximating the operational velocity.
Next, the servo loop 150 initiates a synchronization of the demodulation circuit 146 (a “demod sync”), which involves decoding the Gray code (track address) and the timing marks to acquire and thereafter continually track the radial and angular position of the selected head with respect to the associated disc 108. More particularly, the demod sync operation enables the servo loop hardware to locate (and thereafter track) the head 112 with respect to the associated disc 108.
When the blackout period involves parking the actuator 110 or biasing the actuator against one of the limit stops 224, 226, it may be necessary to first advance the heads 112 out over the disc recording surfaces in order to allow the servo loop 150 to begin transducing the servo sectors 122 on the disc 108.
Depending upon the configuration of the device 100, it may take multiple revolutions of the discs 108 and the successful detection of multiple index positions before the demod sync operation is declared successful. In the meantime, after the detection of just a few timing marks, an accurate determination of the existing rotational velocity of the motor 106 can be achieved. Thus, the processor switches over to embedded motor based control during the demod sync operation.
Finally, once both the motor control circuitry 148 indicates that both the spindle motor 106 and VCM 116 have acquired synchronization and are in a ready state, the processor proceeds with remaining portions of the application code and the device 100 enters normal operation (step 4 of
Assuming that the code swap can be carried out in around 0.5 milliseconds, ms (0.5×10−3 seconds), and the demod sync operation can be successfully carried out in around another 24.5 ms (i.e., a little over four revolutions of the discs 108 at a rotational speed of 10,000 rpm, or about 6 ms/rev), the total transition from startup to application code can be completed in about 25 ms. This has been found to be one or more orders of magnitude faster than existing phased-in code swapping approaches that attempt to maintain processor control throughout, and represents significant reductions in overall device initialization time.
At step 252, an initialization command is received, resulting in the loading and execution of the startup code (from ROM 136 to MEM 1,
During the execution of the startup code, as shown by step 254, the processor 132 initiates processor controlled operation of one or more electrical loads of the device (in this case the spindle motor 106, the VCM 116, the associated control circuitry 148, the read/write channel 142, etc.).
At step 256, the application code is preferably accessed and loaded into a second memory location (MEM 2,
While presently preferred embodiments have been directed to a data storage device, the present invention as claimed below is riot not necessarily so limited. Rather, any number of different types of processor based devices that utilize electrical loads that are controlled by the processor (such as lasers or other light sources, robotic systems, capacitive and inductive charging systems, other types of motor based systems, etc.) are contemplated as being well within the scope of the present disclosure.
It will now be understood that the present invention (as embodied herein and as claimed below) is generally directed to a method and apparatus for initializing a processor based device 100 having a processor 132 that controls an electrical load, such as a motor 106, 116.
In accordance with preferred embodiments, the method preferably comprises controlling the electrical load with startup code executed by the processor. Processor control is next released so that the electrical load operates in an open control mode while the startup code is displaced with application code. Processor control of the electrical load is then reinstated using the application code.
Preferably, the startup code is supplied from a boot read only memory (ROM) 136, and the controlling step comprises loading the startup code into a first memory location 220 accessed by the processor. Moreover, the controlling step further preferably comprises loading the application code into a second memory location 222 accessible by the processor.
The electrical load preferably comprises a spindle motor 106 that supports a data storage medium 108, so that the controlling step comprises using the motor to rotate the data storage medium at an operational velocity and retrieving the application code from the rotating data storage medium.
The apparatus preferably comprises an electrical load 106, 116, a memory location 134, 140, 220, and a programmable processor 132 coupled to the memory location and adapted to control the electrical load
During an initialization process 250 the processor executes startup code loaded into the memory location to initiate operational control of the load, temporarily releases operational control of the electrical load so that the electrical load continues to operate in an open control mode while the startup code in the memory location is displaced with application code, and resumes operational control of the electrical load using the application code.
For purposes of the appended claims and consistent with the foregoing discussion, the term “open control mode” will be understood to include a mode of operation whereby the electrical load continues to operate using settings established by the processor prior to the release of processor control and without further processor regulation or intervention, a mode that is not under processor control or simply a mode that is not under any control.
The term “operational control” will be understood to include a mode of operation whereby the processor engages in continual active regulation, intervention or verification to maintain the continued operation of the load, or simply a mode where the processor controls the load.
It will be clear that the present invention is well adapted to attain the ends and advantages mentioned as well as those inherent therein. While presently preferred embodiments have been described for purposes of this disclosure, numerous changes may be made which will readily suggest themselves to those skilled in the art and which are encompassed in the appended claims.
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
4130769, | Nov 01 1974 | Canon Kabushiki Kaisha; Canon Seiki Kabushiki Kaisha | Brushless DC motor |
4169990, | Jun 14 1974 | General Electric Company | Electronically commutated motor |
4405885, | Jul 23 1980 | Matsushita Electric Industrial Co., Ltd. | Brushless dc motor |
4531079, | May 27 1982 | Papst Licensing GmbH | Brushless DC drive motor for signal recording means |
4631459, | Dec 25 1984 | Matsushita Electric Industrial Co., Ltd. | Brushless DC motor |
4633150, | Dec 25 1984 | Matsushita Electric Industrial Co., Ltd. | Driving circuit for brushless DC motors |
4712050, | Mar 17 1986 | Hitachi, Ltd. | Control system for brushless DC motor |
4742282, | Oct 15 1985 | Sanyo Electric Co., Ltd. | Brake pulse forming circuit for a video tape recorder |
4748386, | Sep 20 1985 | Sanyo Electric Co., Ltd. | Controller of brushless DC motor |
4888533, | Feb 22 1988 | MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD , 1006, OAZA KADOMA, KADOMA-SHI, OSAKA-FU 571 JAPAN; MATSUSHITA REFRIGERATION COMPANY, 22, 3-CHOME, TAKAIDAHONDORI HIGASIOSAKA-SHI, OSAKA-FU 577 JAPAN | Brushless DC motor |
4896807, | Apr 15 1988 | Quad/Tech, Inc. | Web guide apparatus |
4926101, | Jul 25 1988 | Kabushiki Kaisha Toshiba | DC motor stop detector and DC motor brake apparatus |
4992710, | Sep 27 1989 | Seagate Technology LLC | Position detection for a brushless DC motor with sample time optimization |
5001405, | Sep 27 1989 | Seagate Technology LLC | Position detection for a brushless DC motor |
5010283, | Jan 13 1988 | SANKYO SEIKI MFG CO , LTD , KOMAGANE WORKS | Motor control circuit |
5028852, | Jun 21 1990 | Seagate Technology LLC | Position detection for a brushless DC motor without hall effect devices using a time differential method |
5117165, | Jun 29 1990 | Seagate Technology LLC | Closed-loop control of a brushless DC motor from standstill to medium speed |
5159246, | Aug 18 1990 | Victor Company of Japan, Ltd. | Detection of relative position between magnetic pole and drive coil in brushless DC motor |
5166583, | Nov 30 1989 | Goldstar Co., Ltd.; Goldstar Electron Co., Ltd. | Driving methods and driving circuits for brushless DC motors without rotor position sensors |
5184038, | Jan 23 1990 | Kawasaki Jukogyo Kabushiki Kaisha | Method of coupling magnetic position detecting device with brushless dc motor and the coupling structure thereof |
5189574, | Nov 04 1988 | Kabushiki Kaisha Toshiba | Flexible information storing disk apparatus having laminar air flow |
5254914, | Jun 29 1990 | Seagate Technology LLC | Position detection for a brushless DC motor without Hall effect devices using a mutual inductance detection method |
5274310, | Jan 24 1991 | Kabushikigaisha Sekogiken | High-speed DC motor with added charge voltage |
5285135, | Sep 23 1992 | SGS-Thomson Microelectronics, Inc. | Automatic adjustment of commutation delay for brushless DC motor for improved efficiency |
5298839, | Mar 20 1991 | Fujitsu Limited | Electrical angle control system for a brushless DC motor in a magnetic disk apparatus |
5334917, | Jun 25 1991 | W SCHLAFHORST AG & CO | System and method for optimally driving a DC motor |
5343127, | Oct 31 1991 | SGS-Thomson Microelectronics, S.r.l. | Start-up procedure for a brushless, sensorless motor |
5378976, | Apr 10 1992 | Matsushita Electric Industries Co., Ltd. | Brushless DC motor without a position sensor |
5397972, | Oct 31 1991 | SGS-Thomson Microelectronics, S.r.l. | Start-up procedure for a brushless, sensorless motor |
5428276, | Sep 23 1992 | SGS-Thomson Microelectronics, Inc. | Automatic adjustment of commutation delay for brushless DC motor for improved efficiency |
5541488, | Apr 11 1994 | Sundstrand Corporation | Method and apparatus for controlling induction motors |
5631999, | Sep 06 1995 | Seagate Technology LLC | Adaptive compensation for hard disc drive spindle motor manufacturing tolerances |
5703449, | Oct 19 1990 | Seiko Epson Corporation | Controller for brushless DC motor without position sensor |
5777448, | Mar 31 1993 | Kabushiki Kaisha Toshiba | Circuit for controlling brushless DC motor |
5780983, | Mar 15 1994 | Seiko Epson Corporation | Brushless DC motor drive apparatus |
5841252, | Mar 31 1995 | Seagate Technology LLC | Detection of starting motor position in a brushless DC motor |
5870363, | Oct 25 1996 | CSR TECHNOLOGY INC | Optical disk motor servo and method for closed loop speed control |
5929577, | Oct 13 1995 | Unitrode Corporation | Brushless DC motor controller |
5963706, | Oct 23 1997 | KANG, KI CHEOL | Control system for multi-phase brushless DC motor |
5982119, | Mar 09 1994 | Matsushita Electric Industrial Co., Ltd. | Motor drive apparatus including braking means |
5982571, | Jun 30 1997 | Maxtor Corporation | Disk drive with closed loop commutator and actuator oscillator |
5998946, | Oct 08 1997 | Daewoo Electronics Corporation | Method and apparatus for controlling a rotation of a sensorless and brushless DC motor |
6078158, | Dec 04 1998 | Western Digital Technologies, INC | Disk drive motor spin-up control |
6160367, | Jul 07 1998 | III Holdings 10, LLC | Apparatus and method for driving motor |
6405311, | Jul 28 1998 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Method for storing board revision |
20020167287, | |||
20040003223, | |||
20040019776, | |||
20040078679, |
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