The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.
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0. 29. A semiconductor memory device comprising:
data terminals;
a memory;
a data buffer comprising latches to latch in data received on the data terminals to be stored in the memory; and
means for providing an internal clock in response to at least one preamble received on at least one of the data terminals to which at least a portion of the data is appended,
wherein the latches of the data buffer are responsive to the internal clock provided by the means for providing.
0. 35. A semiconductor memory device, comprising:
data terminals;
a data input buffer connected to receive data at each of multiple data input periods from the data terminals;
a memory configured to receive and store the data from the data input buffer; and
a detection circuit to detect a preamble received by the data input buffer preceding the data on the data terminals and which consists of logic low signals provided on multiple ones of the data terminals for a time period no less than multiple data input periods.
0. 37. A semiconductor memory device, comprising:
data terminals including first and second terminals;
a data input buffer connected to receive data from the data terminals;
a memory configured to receive and store the data from the data input buffer; and
a detection circuit to detect a preamble received by the data input buffer preceding the data on the data terminals and which comprises a parallel preamble signal comprising a first logic level on the first terminal and a second logic level, different from the first logic level on the second terminal.
0. 14. A semiconductor memory device comprising:
a memory portion;
a data terminal;
a data input buffer connected to receive data to be stored in the memory from the data terminal;
a clock selection circuit having an output on which a selected clock is provided, the selected clock corresponding to one of a plurality of internal clock signals and being selected in response to a timing of a preamble signal provided to the semiconductor memory device on the data terminal during a write operation; and
an internal clock generator having a plurality of internal clock outputs on which respective ones of the plurality of internal clock signals are provided,
wherein the clock selection circuit includes a plurality of inputs connected to receive respective ones of the plurality of internal clock signals.
0. 34. A semiconductor memory device comprising:
data terminals;
a data input buffer connected to receive data from the data terminals;
a memory configured to receive and store the data from the data input buffer; and
a clock selection circuit having an output on which a selected clock is provided, the selected clock corresponding to one of a plurality of internal clock signals and being selected in response to a preamble received by the data input buffer preceding the data on the data terminals and which consists of logic low signals provided on multiple ones of the data terminals,
wherein the preamble to which the clock selection circuit is responsive consists of logic low signals provided on multiple ones of the data terminals during a time period equal to n data input time periods, wherein n is an integer greater or equal to 1.
1. A semiconductor memory device comprising:
a memory cell for storing data;
an internal clock generator for generating a first internal clock signal, a second internal clock signal or a third internal clock signal in response to a mode control signal;
a command/address input unit for transferring an externally input command/address signal to inside of the semiconductor memory device in synchronization with the first internal clock signal;
a controller for outputting a plurality of control signals and an address signal in response to the command/address signal so as to control operation of the semiconductor memory device, the controller having a mode register for generating the mode control signal;
a control circuit for selecting between a first mode and a second mode in response to the mode control signal, wherein in the first mode the control circuit selects both of an externally input first clock signal and an externally input second clock signal and in the second mode the control circuit selects only one of the externally input first clock signal and the externally input second clock signal;
a data input unit for receiving data in synchronization with the second internal clock signal;
a data output unit for outputting data including a preamble in synchronization with the third internal clock signal; and
a data processing unit for storing data inputted through the data input unit in the memory cell according to the control signals of the control unit, or transferring the data from the memory cell to the data output unit, wherein the preamble is added to a header of the outputted data and is indicative of start of the data;
wherein:
in the first mode the internal clock generator generates the first internal clock signal in response to the externally input first clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the externally input second clock signal, and
in the second mode the internal clock generator generates the first internal clock signal in response to the one of the externally input first clock signal and the externally input second clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the one of the externally input first clock signal and the externally input second clock signal.
10. A semiconductor memory device inputting and outputting data including a preamble, the semiconductor memory device comprising:
a memory cell for storing data through a plurality of data lines;
an internal clock generator for generating a first internal clock signal, a second internal clock signal or a third internal clock signal in response to a mode control signal;
a command/address input unit for transferring an externally input command/address signal to inside of the semiconductor memory device in synchronization with the internal command/address clock signal;
a controller for outputting a plurality of control signals and an address signal in response to the command/address signal so as to control operation of the semiconductor memory device, the controller having a mode register for generating the mode control signal;
a control circuit for selecting between a first mode and a second mode in response to the mode control signal, wherein in the first mode the control circuit selects both of an externally input first clock signal and an externally input second clock signal and in the second mode the control circuit selects only one of the externally input first clock signal and the externally input second clock signal;
a data input unit for receiving data including a preamble in synchronization with any one of the plurality of internal clock signals;
a data output unit for outputting data including a preamble in synchronization with any one of the plurality of internal clock signals; and
a data processing unit for storing data inputted through the data input unit in the memory cell according to a control signal of the control unit, or transferring the data from the memory cell to the data output unit,
wherein the data output unit comprises a preamble generator for generating the preamble and adding the preamble to the output data, and
wherein:
in the first mode the internal clock generator generates the first internal clock signal in response to the externally input first clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the externally input second clock signal, and
in the second mode the internal clock generator generates the first internal clock signal in response to the one of the externally input first clock signal and the externally input second clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the one of the externally input first clock signal and the externally input second clock signal.
2. The semiconductor memory device of
5. The semiconductor memory device of
6. The semiconductor memory device of
7. The semiconductor memory device of
8. The semiconductor memory device of
9. The semiconductor memory device of
a preamble detecting circuit for latching inputted data including the preamble; and
a data input buffer for inputting an input data in synchronization with the second internal clock signal to the data input unit according to a preamble detection signal from the preamble detection circuit.
11. The semiconductor memory device of
a preamble detector for detecting a preamble of inputted data and generating a preamble detecting signal;
a clock selector for receiving the plurality of internal clock signals and selecting and outputting one of the plurality of internal clock signals in response to the preamble detecting signal; and
a data input buffer for receiving inputted data in synchronization with the internal clock signal selected by the clock selector.
12. The semiconductor memory device of
13. The semiconductor memory device of
0. 15. The semiconductor memory device of claim 14, further comprising:
a control circuit having an output provided to the clock selection circuit to control the selection of the clock selection circuit in response to the preamble signal provided on the data terminal.
0. 16. The semiconductor memory device of claim 15, wherein the output of the control circuit is responsive to the preamble signal provided on the data input terminal immediately prior to receipt of data.
0. 17. The semiconductor memory device of claim 15, further comprising:
a plurality of data terminals,
wherein the data terminal is one of the plurality of data terminals, and
wherein the preamble signal is composed of multiple signals provided on the plurality of data terminals.
0. 18. The semiconductor memory device of claim 17, wherein the semiconductor memory device further comprises a data processing unit configured to store data appended to the preamble received by the data terminals.
0. 19. The semiconductor memory device of claim 18, wherein the control circuit is logically connected to receive signals from all of the data terminals.
0. 20. The semiconductor memory device of claim 17, wherein the data buffer comprises a plurality of latches and the selected clock is provided to the plurality of latches to latch data provided to the data terminals.
0. 21. The semiconductor memory device of claim 20, further comprising an address terminal separate from the data terminals so that address and data are provided on separate terminals to the semiconductor memory device.
0. 22. The semiconductor memory device of claim 17, further comprising an address terminal separate from the data terminal so that address and data are provided on separate terminals to the semiconductor memory device.
0. 23. The semiconductor memory device of claim 17, wherein the data input buffer comprises a plurality of latches and the selected clock is provided to the plurality of latches to latch data provided to the data terminals.
0. 24. The semiconductor memory device of claim 23, further comprising an address terminal separate from the data terminal so that address and data are provided on separate terminals to the semiconductor memory device.
0. 25. The semiconductor memory device of claim 23, wherein the
plurality of internal clock signals have the same frequency and are out of phase with each other.
0. 26. The semiconductor memory device of claim 25, wherein the plurality of internal clock signals comprise 1 through n internal clock signals having a phase of 1×m through n×m degrees, respectively, where n and m are integers.
0. 27. The semiconductor memory device of claim 25, wherein the plurality of latches are responsive to a latching portion of the selected clock to latch data on corresponding data terminals, and wherein the clock selection circuit is configured to provide the selected clock as the internal clock signal having latching portion near in time to the middle of a data bit receiving period.
0. 28. The semiconductor memory device of claim 27, wherein the latching portion of the selected clock is an edge of the selected clock.
0. 30. The semiconductor memory device of claim 29, wherein the means for providing the internal clock provides the internal clock to have a phase responsive to the at least one preamble.
0. 31. The semiconductor memory device of claim 30, further comprising a clock generation circuit to provide a plurality of clocks which are out of phase with each other, and wherein the means for providing an internal clock selects the internal clock from one of the plurality of clocks provided by the clock generation circuit.
0. 32. The semiconductor memory device of claim 29, further comprising a data processing unit having an input to receive the data from the data buffer and an output to store the data in the memory.
0. 33. The semiconductor memory device of claim 29, further comprising an address terminal so that address and data are provided on separate terminals to the semiconductor memory device.
0. 36. The semiconductor memory device of claim 35, wherein the preamble to which the clock selection circuit is responsive consists of logic low signals provided on multiple ones of the data terminals during a time period equal to n data input time periods, wherein n is an integer greater or equal to 1.
0. 38. The semiconductor memory device of claim 37, wherein the data terminals comprise even terminals and odd terminals, the first terminal is an odd terminal, the second terminal is an even terminal, and the preamble to which the clock selection circuit is responsive is a parallel preamble signal comprising the first logic level on the odd terminals and the second logic level on the even terminals.
0. 39. The semiconductor device of claim 38, wherein the preamble to which the clock selection circuit is responsive is a parallel preamble signal comprising the first logic level on the odd terminals and the second logic level on the even terminals during a time period equal to n data input time periods, wherein n is an integer greater or equal to 2.
0. 40. The semiconductor memory device of claim 37, wherein the preamble to which the clock selection circuit is responsive is a parallel signal preamble comprising the first logic level on the first terminal and the second logic level on the second terminal at a first time period and the second logic level on the first terminal and the first logic level on the second terminal at a second time period immediately following the first time period.
0. 41. The semiconductor memory device of claim 37, wherein the data terminals comprise even terminals and odd terminals, the first terminal is an odd terminal, the second terminal is an even terminal, and the preamble to which the clock selection circuit is responsive is a parallel signal preamble comprising the first logic level on the odd terminals and the second logic level on the even terminals at a first time period and the second logic level on the odd terminals and the first logic level on the even terminals at a second time period immediately following the first time period.
0. 42. The semiconductor memory device of claim 37, wherein the data terminals comprise first, second, third and fourth terminals, and the preamble to which the clock selection circuit is responsive is a parallel signal preamble comprising, during a first time period, the first logic level on the first and fourth terminals and the second logic level on the second and third terminals, and during a second time period immediately following the first time period, the first logic level on the first and third terminals and the second logic level on the second and fourth terminals.
0. 43. The semiconductor device of claim 42, wherein the first, second, third and fourth terminals are nth, nth+1, nth+2 and nth+3 data terminals, respectively.
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This application, filed on Jun. 30, 2011, is a divisional reissue application of reissue application Ser. No. 12/895,094, filed on Sep. 30, 2010 now abandoned, which is a reissue application of U.S. Pat. No. 7,457,192, issued on Nov. 25, 2008 and filed on Dec. 1, 2006 as U.S. patent application Ser. No. 11/607,311, which is a continuation-in-part application of U.S. patent application Ser. No. 10/894,823, filed Jul. 19, 2004 now U.S. Pat. No. 7,170,818, which relies for priority on Korean Patent Application Nos. 2003-49770, filed on Jul. 21, 2003 and 2004-36908, filed on May 24, 2004. The, the contents of all of the above documents which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a double data rate synchronous semiconductor memory device, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting into the outputted data a preamble notifying a start of data.
2. Description of the Related Art
Generally, a synchronous semiconductor memory device receives and outputs data in synchronization with an external system clock. Synchronous semiconductor memory devices are classified into single data rate synchronous semiconductor memory devices (hereinafter, referred to as SDR SDRAM) and double data rate synchronous semiconductor memory devices (hereinafter, referred to as DDR SDRAM).
While the SDR SDRAM operates in synchronization with rising edges or falling edges, the DDR SDRAM operates in synchronization with both rising edges and falling edges. Accordingly, the operation frequency of the DDR SDRAM is double that of the SDR SDRAM with respect to the same system clock. Since the DDR SDRAM transmits data at high frequency, a data strobe signal DS is used to latch such high frequency data.
A data strobe signal DS is generated by a data source when data is outputted. That is, when data is inputted from a master such a chipset or hub to a DDR SDRAM, the data strobe signal DS is generated by the master and inputted to the DDR SDRAM along with data. On the contrary, when data is outputted from the DDR SDRAM, the data strobe signal DS is generated in the DDR SDRAM and outputted to the master along with data. The side that receives the data recognizes input of data by the data strobe signal DS. That is, the data strobe signal DS plays a role of a synchronization clock for the semiconductor memory device to recognize data.
Such a data strobe signal DS keeps a high impedance state (between a high level and a low level) before the data are outputted from the data source. The data strobe signal DS is changed to a low level before one cycle from the time that data is outputted. The data strobe signal DS is toggled according to variation of a window of the data. After the data is outputted completely, the data strobe signal DS returns to a high impedance state.
As shown in
Here, the structure of the stub bus or the point-to-point bus is a structure in which memories 502 and 506 included in memory modules 500 and 504 are connected to a connection line 508 on a board by point-to-point in connection structure for communication between memory modules, as shown in
Referring to
Accordingly, the present invention is directed to a semiconductor memory device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
In order to overcome the problems described above, it is an object of the present invention to provide a semiconductor memory device for receiving and outputting data in synchronization with a free-running clock instead of a data strobe signal, in which the outputted data include a preamble notifying a start of the data. The present invention also provides a memory module using the semiconductor memory device.
In accordance with the present invention, there is provided a semiconductor memory device receiving an externally input data read command and an externally input address signal in response to a predetermined externally input clock signal, and outputting data including a preamble in response to the clock signal.
In one aspect, the invention is directed to a semiconductor memory device that includes a memory cell for storing data, an internal clock generator for generating a first internal clock signal, a second internal clock signal or a third internal clock signal in response to a mode control signal and a command/address input unit for transferring an externally input command/address signal to inside of the semiconductor memory device in synchronization with the first internal clock signal. The semiconductor memory device further includes a controller for outputting a plurality of control signals and an address signal in response to the command/address signal so as to control operation of the semiconductor memory device. The controller has a mode register for generating the mode control signal. The semiconductor memory device further includes a control circuit for selecting between a first mode and a second mode in response to the mode control signal. In the first mode the control circuit selects both of an externally input first clock signal and an externally input second clock signal and in the second mode the control circuit selects only one of the externally input first clock signal and the externally input second clock signal. The semiconductor memory device further includes a data input unit for receiving data in synchronization with the second internal clock signal, a data output unit for outputting data including a preamble in synchronization with the third internal clock signal, and a data processing unit for storing data inputted through the data input unit in the memory cell according to the control signals of the control unit, or transferring the data from the memory cell to the data output unit. The preamble is added to a header of the outputted data and is indicative of start of the data. In the first mode the internal clock generator generates the first internal clock signal in response to the externally input first clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the externally input second clock signal. In the second mode the internal clock generator generates the first internal clock signal in response to the one of the externally input first clock signal and the externally input second clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the one of the externally input first clock signal and the externally input second clock signal.
In one embodiment, the preamble added to each data outputted through the data lines has the same level.
In one embodiment, the level of the preamble is a high level. In another embodiment, the level of the preamble is a low level.
In one embodiment, the preamble added to data outputted through neighboring data lines among the plurality of data lines has different level.
In one embodiment, in the second mode, the semiconductor memory device generates the first to third internal clock signals using the externally input first clock signal.
In one embodiment, in the second mode, the semiconductor memory device generates the first to third internal clock signals using the externally input second clock signal.
In one embodiment, if data including the preamble from the outside, the semiconductor memory device detects the preamble included in the input data unit to latch an input data. In another embodiment, the data input unit further includes a preamble detecting circuit for latching inputted data including the preamble and a data input buffer for inputting an input data in synchronization with the second internal clock signal to the data input unit according to a preamble detection signal from the preamble detection circuit.
In another aspect, the present invention is directed to a semiconductor memory device inputting and outputting data including a preamble. The semiconductor memory device includes a memory cell for storing data through a plurality of data lines, an internal clock generator for generating a first internal clock signal, a second internal clock signal or a third internal clock signal in response to a mode control signal and a command/address input unit for transferring an externally input command/address signal to inside of the semiconductor memory device in synchronization with the internal command/address clock signal. The semiconductor memory device further includes a controller for outputting a plurality of control signals and an address signal in response to the command/address signal so as to control operation of the semiconductor memory device. The controller has a mode register for generating the mode control signal. The semiconductor memory device further includes a control circuit for selecting between a first mode and a second mode in response to the mode control signal. In the first mode the control circuit selects both of an externally input first clock signal and an externally input second clock signal and in the second mode the control circuit selects only one of the externally input first clock signal and the externally input second clock signal. The semiconductor memory device further includes a data input unit for receiving data including a preamble in synchronization with any one of the plurality of internal clock signals, a data output unit for outputting data including a preamble in synchronization with any one of the plurality of internal clock signals and a data processing unit for storing data inputted through the data input unit in the memory cell according to a control signal of the control unit, or transferring the data from the memory cell to the data output unit. The data output unit comprises a preamble generator for generating the preamble and adding the preamble to the output data. In the first mode the internal clock generator generates the first internal clock signal in response to the externally input first clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the externally input second clock signal. In the second mode the internal clock generator generates the first internal clock signal in response to the one of the externally input first clock signal and the externally input second clock signal, and generates the second internal clock signal or the third internal clock signal in response to a predetermined control signal and the one of the externally input first clock signal and the externally input second clock signal.
In one embodiment, the data input unit includes a preamble detector for detecting a preamble of inputted data and generating a preamble detecting signal, a clock selector for receiving the plurality of internal clock signals and selecting and outputting one of the plurality of internal clock signals in response to the preamble detecting signal and a data input buffer for receiving inputted data in synchronization with the internal clock signal selected by the clock selector. In another embodiment, the plurality of internal clock signals have different phases from each other. In another embodiment, the plurality of internal clock signals have phase difference of 45°.
In another aspect, the invention is directed to a semiconductor memory device receiving an externally input clock signal, receiving an externally input data read command in response the external clock signal, and outputting data including a preamble in response to the clock signal, wherein the preamble is added to a header of the outputted data and indicates a start of the data.
In one embodiment, the preamble added to each data outputted through the data lines has the same level. In one embodiment, the level of the preamble is a high level. Alternatively, the level of the preamble is a low level.
In one embodiment, the preamble added to data outputted through neighboring data lines among the plurality of data lines has different levels.
In one embodiment, if data includes the preamble from the outside, the semiconductor memory device detects the preamble included in the input data unit to latch an input data.
The semiconductor memory device can further comprise: a control logic for generating a plurality of internal clock signals in response to the clock signal, receiving an externally input command/address signal in synchronization with the internal clock signals, and outputting an address signal to input and output data and a predetermined control signal; a memory cell for storing data in response to the address signal and the control signal or latching and outputting the stored data; and a data input/output unit for adding the preamble to the data outputted from the memory cell and outputting the data with the added preamble in response to the control signal and one internal clock signal, and storing the data received in the memory cell,
In one embodiment, the clock signal includes a first clock signal and a second signal that are different from each other, a first internal clock signal for synchronizing the command/address signal is generated in response to the first clock signal, and a second internal clock signal and a third internal clock signal being a synchronizing signal for input/output data is generated in response to the second clock signal and the control signal. The data input/output unit can comprise a preamble generator for adding the preamble to the outputted data. The data input/output unit can further comprise a preamble detector for detecting the preamble and latching inputted data.
In another aspect, the invention is directed to a semiconductor memory device comprising: a memory cell for storing data; an internal clock generator for generating a first internal clock signal in response to an externally input first clock signal, and generating a second internal clock signal or a third internal clock signal in response to a predetermined control signal and an externally input second clock signal; a command/address input unit for transferring an externally input command/address signal to inside of the semiconductor memory device in synchronization with the first internal clock signal; a controller for outputting a plurality of control signals and an address signal in response to the command/address signal so as to control operation of the semiconductor memory device; a data input unit for receiving data in synchronization with the second internal clock signal; a data output unit for outputting data including a preamble in synchronization with the third internal clock signal; and a data processing unit for storing data inputted through the data input unit in the memory cell according to the control signals of the control unit, or transferring the data from the memory cell to the data output unit, wherein the preamble is added to a header of the outputted data and is indicative of start of the data. The preamble added to each data outputted through the data lines can have the same level. In one embodiment, the level of the preamble is a high level. Alternatively, the level of the preamble is a low level. In one embodiment, the preamble added to data outputted through neighboring data lines among the plurality of data lines has different levels. The semiconductor memory device can generate the first to third internal clock signals using only the first clock signal. In one embodiment, the semiconductor memory device generates the first to third internal clock signals using only the second clock signal. In one embodiment, if data includes the preamble from the outside, the semiconductor memory device detects the preamble included in the input data unit to latch an input data. The data input unit can further comprise: a preamble detecting circuit for latching inputted data including the preamble; and a data input buffer for inputting an input data in synchronization with the second internal clock signal to the data input unit according to a preamble detection signal from the preamble detection circuit.
In another aspect, the invention is directed to a semiconductor memory device inputting and outputting data including a preamble, the semiconductor memory device comprising: a memory cell for storing data through a plurality of data lines; an internal clock generator for generating a internal command/address clock signal in response to an externally input first clock signal, and generating a plurality of internal clock signals in response to a predetermined control signal and an externally input second clock signal; a command/address input unit for transferring an externally input command/address signal to inside of the semiconductor memory device in synchronization with the internal command/address clock signal; a controller for outputting a plurality of control signals and an address signal in response to the command/address signal so as to control operation of the semiconductor memory device; a data input unit for receiving data including a preamble in synchronization with any one of the plurality of internal clock signals; a data output unit for outputting data including a preamble in synchronization with any one of the plurality of internal clock signals; and a data processing unit for storing data inputted through the data input unit in the memory cell according to a control signal of the control unit, or transferring the data from the memory cell to the data output unit. The data output unit comprises a preamble generator for generating the preamble and adding the preamble to the output data.
In one embodiment, the data input unit comprises: a preamble detector for detecting a preamble of inputted data and generating a preamble detecting signal; a clock selector for receiving the plurality of internal clock signals and selecting and outputting one of the plurality of internal clock signals in response to the preamble detecting signal; and a data input buffer for receiving inputted data in synchronization with the internal clock signal selected by the clock selector. In one embodiment, the plurality of internal clock signals have different phases from each other. In one embodiment, the plurality of internal clock signals have phase difference of 45°.
In another aspect, the invention is directed to a memory module having a plurality of semiconductor memory devices for receiving a command/address signal and receiving and outputting data in response to one clock signal inputted, the memory module comprising: a data line connected to the plurality of semiconductor memory devices and being a path for receiving and outputting data; a command/address line being a path for transferring the command/address signal via the semiconductor memory devices; and a clock line being a path for supplying the semiconductor memory devices with the clock signal. Data outputted through the data line includes a preamble indicative of start of the data.
In one embodiment, data inputted through the data line further includes a preamble indicative of start of the data.
In one embodiment, the clock line is connected to each of the plurality of semiconductor memory devices independently.
In one embodiment, the clock line is connected via all the plurality of semiconductor memory devices.
In one embodiment, the memory module further comprises a register circuit including a phase lock loop circuit.
In one embodiment, the memory module has a stub bus structure.
In one embodiment, the memory module has a short-loop-through bus structure.
In another aspect, the invention is directed to a memory module having a plurality of semiconductor memory devices for receiving a command/address signal in response to an externally input first clock signal and receiving and outputting data in response to a second clock signal, the memory module comprising: a data line connected to the plurality of semiconductor memory devices and being a path for receiving and outputting data; a command/address line being a path for transferring the command/address signal via the semiconductor memory devices; a first clock line being a path for supplying the semiconductor memory devices with the first clock signal; and a second clock line being a path for supplying the semiconductor memory devices with the second clock signal. Data outputted through the data line includes a preamble indicative of start of the data.
In one embodiment, data inputted through the data line further includes a preamble indicative of start of the data.
In one embodiment, the first clock line is connected via all the plurality of semiconductor memory devices.
In one embodiment, the second clock line is connected to each of the plurality of semiconductor memory devices independently.
In one embodiment, the memory module further comprises a register circuit including a phase lock loop circuit.
In one embodiment, the memory module has a stub bus structure.
In one embodiment, the memory module has a short-loop-through bus structure.
In another aspect, the invention is directed to a memory module having a plurality of semiconductor memory devices, the memory module comprising: a channel for connecting to an exterior of the memory module; a hub connected to the channel, for transferring a clock signal and a command/address signal inputted from the exterior through the channel to the semiconductor memory devices and allowing the semiconductor memory devices to receive and output data from and to the exterior; a data line connected to the hub and the plurality of semiconductor memory devices and being a path for transferring data; a command/address line being a path for transferring the command/address signal via the semiconductor memory devices from the hub; and a clock line for supplying the semiconductor memory devices with the clock signal. Data outputted to the exterior through the channel includes a preamble indicative of start of the data.
In one embodiment, data inputted from the exterior through the channel further includes a preamble indicative of start of the data.
In one embodiment, the clock line is connected to each of the plurality of semiconductor memory devices independently.
In one embodiment, the clock line is connected via all the plurality of semiconductor memory devices.
In another aspect, the invention is directed to a memory module having a plurality of semiconductor memory devices, the memory module comprising: a channel for connecting to an exterior of the memory module; a hub connected to the channel, for transferring a first clock signal, a second clock signal and a command/address signal inputted through the channel to the semiconductor memory devices and allowing the semiconductor memory devices to receive and output data from and to the exterior through the channel; a data line connected to the hub and the plurality of semiconductor memory devices and being a path for transferring data; a command/address line being a path for transferring the command/address signal via the semiconductor memory devices from the hub; and a first clock line being a path for supplying the semiconductor memory devices with the first clock signal; and a second clock line being a path for supplying the semiconductor memory devices with the second clock signal. Data outputted to the exterior through the channel includes a preamble indicative of start of the data.
In one embodiment, data inputted from the exterior through the channel further includes a preamble indicative of start of the data.
In one embodiment, the first clock line is connected via all the plurality of semiconductor memory devices.
In one embodiment, the second clock line is connected to each of the plurality of semiconductor memory devices independently.
The foregoing and other objects, features and advantages of the invention will be apparent from the more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
Referring to
The internal clock generator 702 generates a plurality of internal clocks in response to a command/address clock CA_CLK and external data clock Data_CLK. More particularly, the internal clock generator 702 generates an internal command/address clock CAi_clk in response to the CA_CLK applied from the exterior, and generates a data input internal clock Din_clk for inputting data according to a predetermined control signal Ctr1 inputted from a controller 704 in response to the Data_CLK signal, or generates a data output internal clock Dout_clk for outputting data. That is, when a write command Write is inputted from the exterior through a command/address input unit 700, the internal clock generator 702 generates a Din_clk for data input. When a read command Read is inputted from the exterior through a command/address input unit 700, the internal clock generator 702 generates a Dout_clk for data output. Din_clk may be a plurality of clock signals having different phases on conditions (that the input data includes a preamble).
The controller 704 generates control signals Ctrl and Ctr12 for controlling a read or write operation of the memory device according to a command/address signal CA inputted from the command/address input unit 700, and transfers address signal ADDR to a memory cell 712. The controller 704 includes a mode register 703 for setting and controlling various operation options of the memory.
A data processing unit 710 supplies a path for inputting and outputting data between the memory cell 712 and either of a data input unit 706 and a data output unit 708 according to an operation control signal Ctr2 inputted from the controller 704. The data processing unit 710 can detect the start and end of data when inputting data including information on CAS latency and burst data length BL and not including a preamble.
The data output unit 708 transferring data inputted from the data processing unit 710 to the exterior in synchronization with Dout_clk when reading data.
In one example, a preamble of the same level can be added to the header of data outputted through all data-lines. That is, as shown in
In another example, preambles of different levels can be added to the header of data outputted through neighboring data lines. That is, as shown in
The device receiving data to which a preamble is added requires a circuit for detecting the preamble and latching data essentially. The configuration of the circuit depends on the type of the preambles.
The data input unit 706 transfers data inputted from the exterior to the data processing unit 710 in synchronization with Din_clk signal.
If the output of the first amplifier 1204 is high level in a first period, it is set to supply the data input buffer 1104 with a clock through the latch circuit 1200. The clock signals P0 to P315 having different phases are inputted to a clock input stage CK of flip-flops in the preamble detector 1100. Here, inputted clock signals P0 to P315 have phase difference of 45° as shown in
If the output of the second amplifier 1206 is high level in the second period, a signal of high level is inputted to an input stage of flip-flops in the preamble detector 1100. Signals Q0 to Q315 are outputted sequentially according to the clock signals P0 to P315 having different phases. Referring to
The clock selector 1102 detects phase of the first signal Q225 inputted by the preamble detector 1100, selects the clock signal P135 that leads the first signal Q225 in phase by 90° and applies the clock signal P135 to the data input buffer 1104. The data input buffer 1104 latches the inputted data DQ0 to DQ3 in synchronization with the clock signal PSEL=P135 and stores the latched data in the memory cell 712. Here, a clock signal that leads phase by 90° is selected to change the clock signal at the center of the data valid time as shown in
When the data is inputted completely, a burst end circuit 1202 applies a signal indicative of end of data to the latch circuit 1200 and the latch circuit 1200 resets the flip-flops of the data input buffer 1104.
The circuit for latching a preamble as described above should be implemented in the same way not only in a semiconductor memory device but also) in other devices receiving data including a preamble. The configuration of circuit can be implemented according to the type of the preamble.
In the embodiment described above, two separate clock signals CA_CLK and Data_CLK are inputted so as to receive a command/address signal and data from the exterior. However, if the phase difference between the two clock signals CA_CLK and Data_CLK is small (less than or equal to 0.5 tCK where tCK is one period of a system clock), it is possible to input a command/address signal and to receive and output data only by any one of the two clock signals. In
As described above, since a memory module including a hub communicates with the controller or another memory module through the hub on the memory module, all the lines go to the hub. Accordingly, the thickness of the memory module can be thicker depending on the number of the lines. In this case, as described above, the number of lines disposed on the memory module is reduced and the thickness of the memory module can be reduced by using only one clock signal of CA_CLK and Data_CLK.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
As described above, the semiconductor memory device can obtain stable setup of data and hold time margin even in high frequency operation. Time skew due to time delay can be prevented when a memory module is implemented. The number of the lines used to supply a clock signal can be reduced when a memory module is implemented, so that the thickness of the memory module can be reduced greatly.
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