Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltage

Abstract

first of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc.

Description

1D1E 1F, in the first embodiment of the present invention, first of all, a semiconductor substrate 100 having a first well 100A 110A and a second well 100B 110B is provided, and then a plurality of isolation regions 120 are formed and defined in the semiconductor substrate 100, as shown in FIG. 1A, and simultaneously a first device region 130A is formed in the first well 100A 110A, a second device region 130B is formed beside the first well 100A 110A, a third device region 130C is formed between the second well 100B 110B and the second device region 130B and a fourth device region 130D is formed in the second well 100B 110B. Afterward, a first dielectric layer 140A having a first thickness is formed on the semiconductor substrate 100, wherein the first dielectric layer 140A is a high-voltage dielectric layer. Then an ion-implanting process 150 is performed to form a control gate 160 of the single-level EEPROM in the second device region 130B under the first dielectric layer 140A. Subsequently, as shown in FIG. 1B, a first etching process 170A is performed to remove a part of the first dielectric layer 140A located on the semiconductor substrate 100 of the first well 100A 110A and the second well 100B 110B, and then, as shown in FIG. 1C, a second dielectric layer 140B having a second thickness is formed on the partial semiconductor substrate 100 located on the first well 100A 110A and the second well 100B 110B, wherein the second thickness is about less than the first thickness. Next, as shown in FIG. 1C 1D, a second etching process 170B is performed to remove a part of the second dielectric layer 140B located on the fourth device region 130D to form the dielectric layer 140B, as. As shown in FIG. 1D 1E, a third dielectric layer 140C having a third thickness is formed on the first device region 130A, the second device region 130B and the fourth device region 130D, wherein the third dielectric layer 140C is a low-voltage dielectric layer, and the third thickness is about less than the second thickness; and further, the third dielectric layer 140C and the second dielectric layer 140B are stacked from each other to form a fourth dielectric layer 140D having a fourth thickness on the first device region 130A; and further, the third dielectric layer 140C and the first dielectric layer 140A are stacked from each other to form a fifth dielectric layer 140E having a fifth thickness on the second device region 130B. Accordingly, the fifth thickness of the fifth dielectric layer 140E on the second device region 130B is more than the first thickness of the first dielectric layer 140A on the third device region 130C; the first thickness of the first dielectric layer 140A on the third device region 130C is more than the fourth thickness of the fourth dielectric layer 140D on the first device region 130A; the fourth thickness of the fourth dielectric layer 140D on the first device region 130A is more than the third thickness of the third dielectric layer 140C on the fourth device region 130D. Then, as shown in FIG. 1E 1F, a plurality of gates 180 are individually formed and defined on these dielectric layers of the first device region 130A, the second device region 130B, the third device region 130C and the fourth device region 130D, wherein there is the same gate located on the first device region 130A and the second device region 130B, and this gate serves as the floating gate of the single-level EEPROM; especially, the first part 180A of the floating gate is located on the dielectric layer of the first device region 130A and the second part 180B of the floating gate is located on the dielectric layer of the second device region 130B. Accordingly, this invention can fabricate the single-level EEPROM operated in environment with high/low-voltage, wherein the third device region 130C can be operated in the opposite electric field about 18V, such as −6V to 12V, −12V to 6V, −9V to 9V etc. The opposite electric field means the voltage difference between the highest voltage and the lowest voltage in which the third device region 130C can be operated.

As illustrated in FIG. 2A, in the second embodiment of the present invention, first of all, a semiconductor substrate 200 having a first conductivity is provided, wherein the first conductivity comprises P-type dopant. Then a first deep well 210A and a second deep well 210B is formed in the semiconductor substrate 200, wherein the first deep well 210A and the second deep well 210B have a second conductivity, such as N-type dopant. Afterward, a plurality of active regions are defined by conventional implanting process and the isolating process to form a plurality of isolating regions 220 and wells 230 in the semiconductor substrate 200, wherein a first well 230A having the first conductivity is formed in the first deep well 210A; a second well 230B having the second conductivity is formed in the adjacent region beside the first deep well 210A; a third well 230C having the first conductivity is formed in the adjacent region beside the second deep well 210B; a fourth well 230D having the second conductivity is formed in the adjacent region between the second deep well 210B and the third well 230C; a fifth well 230E having the first conductivity and the sixth well 230F having the second conductivity are formed in the second deep well 210B; and further, the first well 230A and the second well 230B are the single-level EEPROM device region 200A, and the third well 230C and the fourth well 230D are the high-voltage device region 200B, and the fifth well 230E and the sixth well 230F are the low-voltage device region 200C. Moreover, a plurality of isolating regions 220 are individually on the positions as shown in FIG. 2A, and these isolating regions 220 comprises field-oxide layer (FOX) Subsequently, a first dielectric layer 240A having a first thickness is formed on the semiconductor substrate 200, wherein the first dielectric layer 240A is a high-voltage dielectric layer, and the first thickness is about 200 Å to 600 Å.

Referring to FIG. 2B, in this embodiment, a depletion layer 250 is formed in the second well 230B to reduce the resistances, wherein the depletion layer 250 is a doped region having the second conductivity, such as n n⁻ dopant. Then sequentially establish the threshold voltage(Vt)of the single-level EEPROM in the first well 230A and the threshold voltage (Vt) of the high-voltage device in the third well 230C and the fourth well 230D. Afterward, partial first dielectric layer 240A located on the semiconductor substrate 200 of the first deep well 210A and the second deep well 210B is removed, and then a second dielectric layer 240B having a second thickness is formed on the partial semiconductor substrate 200 located on the first well 210A and the second well 210B, wherein the second thickness is about 60 Å to 80 Å. Subsequently, partial second dielectric layer 240B located on the second deep well 210B is removed, and then a third dielectric layer 240C having a third thickness is formed on the first deep well 210A, the second well 230B and the second deep well 210B, wherein the third dielectric layer 240C is a low-voltage dielectric layer, and the third thickness is about 50 Å to 70 Å; and further, the third dielectric layer 240C and the second dielectric layer 240B are stacked from each other to form a fourth dielectric layer 240D having a fourth thickness on the first deep well 210A; and further, the third dielectric layer 240C and the first dielectric layer 240A are stacked from each other to form a fifth dielectric layer 240E having a fifth thickness on the second well 230B. Accordingly, the fifth thickness of the fifth dielectric layer 240E on the second well 230B is more than the first thickness of the first dielectric layer 240A on the second device region 200B; the first thickness of the first dielectric layer 240A on the second device region 200B is more than the fourth thickness of the fourth dielectric layer 240D on the first deep well 210A; the fourth thickness of the fourth dielectric layer 240D on the first deep well 240C is more than the third thickness of the third dielectric layer 240C on the second deep well 210B.

Referring to FIG. 2C, in this embodiment, a plurality of gates 260 are individually formed and defined on these dielectric layers of the first well 230A, the second well 230B, the third well 230C, the fourth well 230D, the fifth well 230E and the sixth well 230F, wherein there is the same gate located on the first well 230A and the second well 230B, and this gate serves as the floating gate 260A of the single-level EEPROM; especially, the first part of the floating gate 260A is located on the fourth dielectric layer 240D of the first well 230A and the second part of the floating gate 260A is located on the fifth dielectric layer 240E of the second well 230B. Then the first doped region 270A and the second doped region 270B are individually formed in the third well 230C and the fourth well 230D, wherein the first doped region 270A has the second conductivity, such as n⁻ n dopant, and the second doped region 270B has the first conductivity, such as p⁻ p dopant. Subsequently, the third doped region 270C is formed in the first well 230A under the first part of the floating gate 260A to define the source region of the floating gate 260A of the single-level EEPROM located under one side of the first part of the floating gate 260A, wherein the third doped region 270C has the second conductivity, such as n⁻ n dopant. Then the fourth doped region 270D and the fifth doped region 270E are individually formed in the fifth well 230E and the sixth well 230F, wherein the fourth doped region 270D has the second conductive, such as n⁻ dopant; and the fifth doped region 270E has the first conductive, such as p⁻ dopant. Next, the second doped region 270B in the fourth well 230D and the fifth doped region 270E in the sixth well 230F are heavy doped, wherein the heavy dopant comprises the first conductivity, such as p⁺ dopant. Finally, the third doped region 270C in the first well 230A, the depletion layer 250 in the second well 230B, the first doped region 270A in the third well 230C and the fourth doped region 270D in the fifth well 230E are heavy doped, and a sixth doped region 270F is formed in the first well 230A under beside the first part of the floating gate 260A to define the drain region of the floating gate 260A under and the other side of the first part of the floating gate 260A, and a seventh doped region 270G is formed in the depletion layer 250 located under beside one side of the second part of the floating gate 260A to serve as the control gate of the single-level EEPROM such that this control gate is located in the second well 230B under the second part of the floating gate 260A, wherein the heavy dopant comprises the second conductivity, such as n⁺ dopant. Accordingly, this invention can fabricate the single-level EEPROM operated in environment with high/low-voltage, wherein the high-voltage device region 200B can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V ˜6V, −9V˜9V etc.

In these embodiments of the present invention, as discussed above, this invention can utilize formation of tri-well to embed the single-level EEPROM therein, wherein the tri-well comprises an N-well, a P-well and a deep N-well. Furthermore, the present invention constructs the low-voltage device in a deep N-well, the floating gate of the single-level EEPROM on another deep N-well and the control gate of the single-level EEPROM in the N-well located nearby the deep N-well. Accordingly, the single-level EEPROM can be operated in environment with low-voltage and high-voltage area with positive/negative voltage. Therefore, this invention can simultaneously fabricate single-level EEPROM and the high/low voltage devices thereof, so this invention can reduce the complication and costs in the conventional process to correspond to economic effect. On the other hand, the single-level EEPROM of the present invention can be operated in the opposite electric field with wide range, wherein the high-voltage range utilized in the present invention is about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc. Furthermore, the devices fabricated by this invention can simultaneously input and output the positive/negative voltages without transforming voltage state, so this invention can support more diverse application field for the devices or products that need the positive/negative voltages to operate. Therefore, the method of the present invention is the best fabrication process of single-level EEPROM for deep sub-micron semiconductor process.

Obviously, many modifications and variations of the present invention are possible in light of the above teachings. It is to be understood that within the scope of the appended claims, the present invention may be practiced other than as specifically described herein.

Although the specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from what is intended to be limited solely by the appended claims.

Claims

1. A method for forming a single-level electrically erasable and programmable read only memory, the method comprising:

providing a semiconductor substrate having a first well and a second well;

defining and forming a plurality of isolation regions in the semiconductor substrate, and simultaneously, a first device region is formed in the first well, a second device region is formed adjacent said first well, a third device region is formed between said second well and said second device region and a fourth device region is formed in said second well;

forming a first dielectric layer having a first thickness on said semiconductor substrate;

performing an ion-implanting process to form a control gate in said second device region under said first dielectric layer;

removing a portion of said first dielectric layer located on said semiconductor substrate of said first well and said second well;

forming a second dielectric layer having a second thickness on a remaining portion of said first dielectric layer said semiconductor substrate located on said first well and said second well;

removing a portion of said second dielectric layer located on said fourth device region;

forming a third dielectric layer having a third thickness on said first device region, said second device region and said fourth device region, wherein said third dielectric layer and said second dielectric layer are stacked from each other to form a fourth dielectric layer having a fourth thickness on said first device region; and further, said third dielectric layer and said first dielectric layer are stacked from each other to form a fifth dielectric layer having a fifth thickness on said second device region; and

forming and defining a plurality of gates on these dielectric layers of said first device region, said second device region, said third device region and said fourth device region, wherein there is the same gate located on said first device region and said second device region, which serves as the floating gate.

2. The method according to claim 1, wherein said first dielectric layer is a high-voltage dielectric layer.

3. The method according to claim 1, wherein said second thickness is about less than said first thickness.

4. The method according to claim 1, wherein said third dielectric layer is a low-voltage dielectric layer.

5. The method according to claim 1, wherein said third thickness is about less than the second thickness.

6. The method according to claim 1, wherein said fifth thickness of said fifth dielectric layer on said second device region is more than said first thickness of said first dielectric layer on said third device region; and further, said first thickness of said first dielectric layer on said third device region is more than said fourth thickness of said fourth dielectric layer on said first device region; and further, said fourth thickness of said fourth dielectric layer on said first device region is more than said third thickness of said third dielectric layer on said fourth device region.

7. The method according to claim 1, wherein the first part of said floating gate is located on the dielectric layer of said first device region and the second part of said floating gate is located on the dielectric layer of said second device region.

8. The method according to claim 1, wherein said third device region can be operated in the opposite electric field about 18V.

9. The method according to claim 8, wherein the opposite electric field comprises the range −6V to 12V, −12V to 6V and −9V to 9V.