There are included steps of forming a silicon nitride layer on a silicon layer or a silicon oxide layer, loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere, and selectively etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine gas consisting of any one of CH2F2, CH3F, or CHF3 and an inert gas to the dry etching atmosphere. Hence, in the etching process of the silicon nitride layer, the etching selectivity of the silicon nitride layer to Si or SiO2 can be enhanced and also etching anisotropy can be enhanced.
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0. 11. A method of etching a silicon nitride layer comprising the steps of;
forming a silicon nitride layer on a silicon layer or a silicon oxide layer above a substrate;
loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere; and
selectivity etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine compound gas comprising of any one of CH2F2, CH3F, and an inert gas to the dry etching atmosphere,
wherein an anisotropy of the etching, an etching rate of the silicon nitride layer, and an etching selectivity of the silicon nitride layer with respect to the silicon layer or the silicon oxide layer are simultaneously enhanced by controlling a flow rate of the fluorine compound gas.
10. A method of etching a silicon nitride layer comprising the steps of:
forming a silicon nitride layer on a silicon layer or a silicon oxide layer above a substrate;
loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere; and
selectivity etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine compound gas consisting of any one of CH2F2, CH3F, and CHF3 and an inert gas to the dry etching atmosphere,
wherein an anisotropy of the etching, an etching rate of the silicon nitride layer, and an etching selectivity of the silicon nitride layer with respect to the silicon layer or the silicon oxide layer are simultaneously enhanced by controlling a flow rate of the fluorine compound gas.
0. 13. A method of etching a silicon nitride layer comprising the steps of:
forming a silicon nitride layer on a silicon layer or a silicon oxide layer above a substrate;
loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere; and
selectivity etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine compound gas comprising of any one of CH2F2, CH3F, and an inert gas to the dry etching atmosphere,
wherein a flow rate of the fluorine compound gas is set to 5 to 50 sccm, a flow rate of the inert gas is set more than three times a flow rate of the fluorine compound gas, a pressure of the dry etching atmosphere is set to 10 to 500 mTorr, and a rf power applied to the silicon nitride layer is set to 1.1 to 5.5 W/cm2, and said substrate is heated in a range of 20° C. to 95° C.
0. 15. A method of manufacturing a semiconductor device comprising the steps of:
forming a plurality of gate electrodes at a distance on a semiconductor substrate separately;
forming insulating side walls on side surfaces of the gate electrodes;
forming a silicon nitride layer to cover the insulating side walls, the gate electrodes, and the semiconductor substrate;
forming an interlayer insulating layer on the silicon nitride layer;
forming contact holes vertically between the gate electrodes by patterning the interlayer insulating layer; and
etching the silicon nitride layer via the contact holes in an atmosphere into which a fluorine compound gas comprising of any one of CH2F2, CH3F, and an inert gas are introduced,
wherein a pressure of the atmosphere is set to 250 mTorr or more, and a flow rate of the fluorine compound gas is set to ⅕ or less of a flow rate of the inert gas.
0. 12. A method of etching a silicon nitride layer comprising the steps of:
forming a silicon nitride layer on a silicon layer or a silicon oxide layer above a substrate;
loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere; and
selectively etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine compound gas comprising of any one of CH2F2, CH3F, and an inert gas to the dry etching atmosphere,
wherein a pressure of the dry etching atmosphere is set to 10 to 500 mTorr, and said substrate is heated in a range of 20° C. to 95° C., and
wherein an anisotropy of the etching, an etching rate of the silicon nitride layer, and an etching selectivity of the silicon nitride layer with respect to the silicon layer or the silicon oxide layer are simultaneously enhanced by controlling a flow rate of the fluorine compound gas.
0. 14. A method of manufacturing a semiconductor device comprising the steps of:
forming gate electrodes in a device forming region of a silicon substrate via an insulating layer;
forming an insulating layer made of a silicon nitride or silicon nitride oxide to cover the gate electrodes and the device forming region; and
etching the insulating layer in a vertical direction in an atmosphere into which a fluorine compound gas comprising of any one of CH2F2, CH3F, and an inert gas are introduced, so as to remain the insulating layer on side surfaces of the electrodes as side walls,
wherein a flow rate of the fluorine compound gas is set to 5 to 50 sccm, a flow rate of the inert gas is set more than three times a flow rate of the fluorine compound gas, a pressure of the dry etching atmosphere is set to 10 to 500 mTorr, and a rf power applied to the silicon nitride layer is set to 350 to 700 W, and said substrate is heated in a range of 20° C. to 95° C.
1. A method of etching a silicon nitride layer comprising the steps of:
forming a silicon nitride layer on a silicon layer or a silicon oxide layer above a substrate;
loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere; and
selectivity etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine compound gas consisting of any one of CH2F2, CH3F, and CHF3 and an inert gas to the dry etching atmosphere,
wherein a flow rate of the fluorine compound gas is set to 5 to 50 sccm, a flow rate of the inert gas is set more than three times a flow rate of the fluorine compound gas, a pressure of the dry etching atmosphere is set to 10 to 500 mTorr, and a rf power applied to the silicon nitride layer is set to 1.1 to 5.5 W/cm2, and a temperature of said substrate is set heated in a range of 20° C. to 95° C. so as to enhance an etching selectivity of the silicon nitride layer with respect to the silicon layer or the silicon oxide layer.
7. A method of manufacturing a semiconductor device comprising the steps of:
forming a plurality of gate electrodes at a distance on a semiconductor substrate separately;
forming insulating side walls on side surfaces of the gate electrodes;
forming a silicon nitride layer to cover the insulating side walls, the gate electrodes, and the semiconductor substrate;
forming an interlayer insulating layer on the silicon nitride layer;
forming contact holes vertically between the gate electrodes by patterning the interlayer insulating layer; and
etching the silicon nitride layer via the contact holes in an atmosphere into which a fluorine compound gas consisting of any one of CH2F2, CH3F, and CHF3 and an inert gas are introduced,
wherein a pressure of the atmosphere is set to 250 mTorr or more, and a flow rate of the fluorine compound gas is set to ⅕ or less of a flow rate of the inert gas, so as to enhance both an anisotropic etching in a vertical direction and an etching selectivity of the silicon nitride layer with respect to the silicon layer or the silicon oxide layer.
8. A method of manufacturing a semiconductor device comprising the steps of:
forming gate electrodes in a device forming region of a silicon substrate via an insulating layer;
forming an insulating layer made of a silicon nitride or silicon nitride oxide to cover the gate electrodes and the device forming region; and
etching the insulating layer in a vertical direction in an atmosphere into which a fluorine compound gas consisting of any one of CH2F2, CH3F, and CHF3 and an inert gas are introduced, so as to remain the insulating layer on side surfaces of the electrodes as side walls,
wherein a flow rate of the fluorine compound gas is set to 5 to 50 sccm, a flow rate of the inert gas is set more than three times a flow rate of the fluorine compound gas, a pressure of the dry etching atmosphere is set to 10 to 500 mTorr, and a rf power applied to the silicon nitride layer is set to 350 to 700 W, and a temperature of said substrate is set heated in a range of 20° C. to 95° C. so as to enhance an etching selectivity of the silicon nitride layer with respect to the silicon layer or the silicon oxide layer.
0. 16. A method of manufacturing a semiconductor device comprising the steps of:
forming grooves in a semiconductor substrate to be adjacent to a device forming region of the semiconductor substrate;
filling buried insulating material made of silicon oxide in the grooves;
forming a gate electrode on the device forming region of the semiconductor substrate via a gate insulating layer;
forming impurity diffusion layers on side surfaces of the gate electrode on the semiconductor substrate;
forming a silicon nitride layer to cover the impurity diffusion layer, the buried insulating material, and the gate electrode; and
etching partially the silicon nitride layer in an atmosphere into which a fluorine compound gas comprising of any one of CH2F2, CH3F, and an inert gas are introduced, so as to form a contact hole in a region spreading from the groove to the impurity diffusion layer,
wherein a flow rate of the fluorine compound gas is set to 5 to 50 sccm, a flow rate of the inert gas is set more than three times a flow rate of the fluorine compound gas, a pressure of the dry etching atmosphere is set to 10 to 500 mTorr, and a rf power applied to the silicon nitride layer is set to 350 to 700 W, and said substrate is heated in a range of 20° C. to 95° C.
9. A method of manufacturing a semiconductor device comprising the steps of:
forming grooves in a semiconductor substrate to be adjacent to a device forming region of the semiconductor substrate;
filling buried insulating material made of silicon oxide in the grooves;
forming a gate electrode on the device forming region of the semiconductor substrate via a gate insulating layer;
forming impurity diffusion layers on side surfaces of the gate electrode on the semiconductor substrate;
forming a silicon nitride layer to cover the impurity diffusion layer, the buried insulating material, and the gate electrode; and
etching partially the silicon nitride layer in an atmosphere into which a fluorine compound gas consisting of any one of CH2F2, CH3F, and CHF3 and an inert gas are introduced, so as to form a contact hole in a region spreading from the groove to the impurity diffusion layer,
wherein a flow rate of the fluorine compound gas is set to 5 to 50 sccm, a flow rate of the inert gas is set more than three times a flow rate of the fluorine compound gas, a pressure of the dry etching atmosphere is set to 10 to 500 mTorr, and a rf power applied to the silicon nitride layer is set to 350 to 700 W, and a temperature of said substrate is set heated in a range of 20° C. to 95° C. so as to enhance an etching selectivity of the silicon nitride layer with respect to the silicon layer or the silicon oxide layer.
2. A method of etching a silicon nitride layer according to
3. A method of etching a silicon nitride layer according to
4. A method of etching a silicon nitride layer according to
5. A method of etching a silicon nitride layer according to
6. A method of etching a silicon nitride layer according to
a distance between the two electrodes is set to 5 to 70 mm.
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1. Field of the Invention
The present invention relates to a method of etching a silicon nitride layer and a method of manufacturing a semiconductor device including a step of patterning the silicon nitride layer.
2. Description of the Prior Art
With the development of miniaturization of the semiconductor integrated circuit (LSI), a SAC (Self Alignment Contact) technique and a BLC (Border Less Contact) technique have been employed to arrange the wirings from an impurity diffusion layer to a field insulating film.
According to the SAC technique, in the event that wirings are connected to two MOS transistors which employ one impurity diffusion layer as a common constituent element and the wirings are to be connected to a common impurity diffusion layer between two gate electrodes, connecting positions of the wirings are regulated by an insulating layer formed on surfaces of two gate electrodes.
Like the above, with the use of the SAC technique, the wirings can be easily and firmly connected to the impurity diffusion layer between the gate electrodes which are narrowed together with the miniaturization.
According to the BLC technique, grooves are formed in a device isolation region of a semiconductor substrate, then silicon oxide is filled in the grooves, then an impurity diffusion layer is formed on a semiconductor substrate, then wirings are formed in a region spreading from the impurity diffusion layer to the device isolation region.
If such BLC technique is employed, an alignment margin in the contact area between the wiring and the impurity diffusion layer can be increased.
Next, examples of the semiconductor device employing the SAC technique and the BLC technique in the prior art will be explained hereunder.
SAC technique
As shown in
In such condition, after a thin protection film 106 made of SiO2 is formed on an overall surface, a covering layer 107 made of Si3N4 is formed and then an interlayer insulating layer 108 made of BPSG and an intermediate layer 109 made of SiO2 are formed on the covering layer 107.
Subsequently, in order to form contact holes in the interlayer insulating layer 108 and the intermediate layer 109, a photoresist 110 having windows 111 over gaps between the side walls 105 is formed.
In turn, as shown in
Next, as shown in
After the photoresist 110 has been removed, wirings are formed on the interlayer insulating layer 108, though not particularly depicted, and then the wirings are connected to the impurity diffusion layers 101 via clearances between the contact holes 112 and clearances between the side walls 105.
BLC technique
First, steps of forming up to a structure shown in
A groove 112 is formed is formed in the device isolation region of the silicon substrate 121, and then a buried insulating film 123 made of silicon oxide is filled into the groove 122. As a method of filling the buried insulating film 123 into the groove 122, such a method can be employed, for example, that the buried insulating film 123 is formed by CVD (Chemical Vapor Deposition) in the groove 122 and on the silicon substrate 121 and then the buried insulating film 123 on a surface of the silicon substrate 121 is removed by polishing.
A gate insulating film 124, a gate electrode 125, and a gate covering insulating film 126 are then formed in an active region. Then, low-impurity concentration regions 127a, 127d are formed by ion-implanting the impurity into the silicon substrate 121 on both sides of the gate electrode 125 at a low dosage by use of the gate electrode 125 as a mask.
Then, an insulating film 128 made of silicon nitride and silicon nitride oxide is formed on the silicon substrate 121, the gate covering insulating film 126, and the low-impurity concentration regions 127a, 127d.
Thereafter, as shown in
Then, as shown in
The LDD structure impurity diffusion layers 129a, 129d can be formed on both sides of the gate electrode 125 by the high-impurity concentration regions 129s, 129d and the low-impurity concentration regions 127a, 127d.
As shown in
Thus, a MOS transistor can be formed in the active region.
After this, as shown in
Then, a plurality of contact holes 134a, 134d are formed in the silicon nitride film 132 and the interlayer insulating film 133 by the photolithography technique. These contact holes 134s, 134d are formed on two silicide layers 131s, 131d in the active region. In this case, if miniaturization of the semiconductor device is considered, a diameter of the contact holes 134s, 134d cannot be formed to have a wide margin in size rather than the high-impurity concentration regions 129s, 129d and as a result the contact holes 134s, 134d can be formed to cross over the buried insulating film 123.
Then, the wirings (not shown) are provided to the LDD structure impurity diffusion layers 129s, 129d via the contact holes 124s, 134d.
With the above, the common SAC technique and the common BCL technique have been described.
Meanwhile, for example, as set forth in Patent Application Publication (KOKAI) 6-12765, it has been deduced that an etching rate of Si3N4 can be enhanced rather than that of Si if one of CH2F2 and CH3F is employed as an etching gas to etch a covering layer made of silicon nitride, and that the etching rate of Si3N4 can be enhanced up to about ten times those of SiO2 and Si if the flow rate of the gas is changed and the pressure is set higher.
In general, if Si3N4 is etched by use of a gas mixture which consists of a fluorine compound gas as a major gas such as CF4, SF6, or NF3, oxygen, etc., following etching performance has been derived.
Si etching rate>Si3N4 etching rate>SiO2 etching rate
In this case, a value α/β obtained by dividing the etching rate α of Si3N4 by the etching rate β of SiO2 (referred to as an “etching selectivity of Si3N4 to SiO2” hereinafter) has been 2 to 3. Therefore, such gas mixture can be used for the SAC and the BLC, but such gas mixture enables only isotropic etching. Besides, damage of the silicon substrate is increased under such SiNx etching condition.
According to the inventors' experiment using another etching gas which includes CF4 and CHF3 mainly, following etching performance has been derived.
SiO2 etching rate>Si3N4 etching rate>Si etching rate
In this case, the etching selectivity of Si3N4 to SiO2 has been in the range of 0.5 to 1 and such another etching gas enables anisotropic etching. Such another etching gas can be used for information of the contact hole and removal of the LOCOS nitride film.
Meanwhile, followings have arisen as problems in the SAC technique.
If the fluorine gas is used as the etching gas, the etching selectivity of Si3N4 to SiO2 or Si has been enhanced, but such fluorine gas has enabled only isotropic etching. Hence, a patterning accuracy of the silicon nitride layer has been degraded.
For instance, as shown in
On the contrary, it may be considered that an etching time can be shortened in order to prevent the side etching of the covering layer 107. However, in this case, because of insufficient etching, the covering layer 107 has remained on the side surfaces of the side walls 105. Thus, respective areas of the impurity diffusion layers 101 which are exposed on the side of the side walls 105 are made small. Under such condition, a contact resistance between the wiring passing through the contact hole 112 and the impurity diffusion layer 101 is likely to be increased.
In addition, in order to completely remove the covering layer 107 on the side surfaces of the side walls 105, it may also be considered that the etching selectivity of Si3N4 to SiO2 can be made small to thus enhance anisotropy. In this case, there has been caused such a disadvantage that side surfaces of the SiO2 cap layer 104 covering the gate electrode 103 is etched and thus short-circuit between the wiring formed in the contact hole 112 and the gate electrode 103 would be caused.
Further, if overetching is carried out to remove completely the covering layer 107 between two gate electrodes 103, upper edges of the side walls 105 are also removed so that a part of the gate electrode 103 is exposed. As a result, the gate electrode 103 is short-circuited to a plug passing through the contact hole 112.
While, followings have arisen as problems in the BLC technique.
For example, if the etching selectivity of the silicon nitride to the silicon oxide cannot be enhanced when the silicon nitride film 132 is etched via the contact holes 134s, 134d formed in the interlayer insulating film 133, a surface of the buried insulating film 123 made of silicon oxide is etched to thus expose a part of the silicon substrate 121, as shown in
The side wall 128 has been formed of silicon oxide in the above explanation. However, if the side wall 128 is formed of silicon nitride, the etching selectivity of the silicon nitride to the silicon substrate must be enhanced. More particularly, as shown on the left side in
As described above, in the above prior art, there has been such a problem that the etching selectivity of the silicon nitride to the silicon oxide and the anisotropy have trade-off relations with each other.
It is an object of the present invention to provide a method of etching a silicon nitride layer which is capable of enhancing an etching selectivity of silicon nitride to silicon and silicon oxide and enhancing etching anisotropy of the silicon nitride, and a method of manufacturing a semiconductor device including such etching step.
The method of etching a silicon nitride layer comprising the steps of forming a silicon nitride layer on a silicon layer or a silicon oxide layer; loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere; and selectively etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine compound gas consisting of any one of CH2F2, CH3F, and CHF3 and an inert gas to the dry etching atmosphere.
According to the present invention, the silicon nitride layer is dry-etched by using the fluorine compound gas composed of any one of CH2F2, CH3, and CHF3 and the inert gas such as Ar, He, etc. With the use of these gases, the etching rate of the silicon nitride layer can be enhanced ten times or more the etching rate of the silicon oxide layer or the silicon layer beneath the silicon nitride layer and in addition the anisotropic etching thereof can be achieved.
That is to say, the etching selectivity of the silicon nitride layer to the silicon oxide layer and the silicon layer can be enhanced and simultaneously side etching upon patterning of the silicon nitride layer can be suppressed.
Such etching performance can remarkably appear when the flow rate of the inert gas is set more than three times the flow rate of the fluorine compound gas, in a ratio between the fluorine compound gas introduced into the chamber and the inert gas.
Hence, in the step of forming the semiconductor device employing the SAC technique, because such etching process is employed, the silicon nitride layer can be excessively etched not to remain the silicon nitride on the side surfaces of the side walls of the gate electrodes. In addition, the silicon oxide layer covering the gate electrodes is never removed by etching. As a result, the contact region formed between two side walls can be prevented from being narrowed and also short-circuit between the gate electrodes and conductive layers in the contact holes can be prevented.
Also, in the step of forming the semiconductor device employing the BLC technique, if the etching method is applied under the above conditions, etching of the silicon oxide layer which is buried in the groove in the neighboring of the device forming region can be suppressed and the silicon substrate is difficult to be exposed from the side walls of the groove. Consequently, the electrodes formed to cross over the boarder between the groove and the silicon substrate can be avoided from being connected to the silicon substrate beneath the impurity diffusion layer.
Furthermore, the impurity diffusion layer becomes difficult to be etched by virtue of the RIE which is used to form the side wall made of silicon nitride or silicon nitride oxide on both sides of the gate electrode of the MOS transistor, so that the increase of the leakage current and the increase of electric resistance due to the thinned impurity diffusion layer can be avoided.
In order to carry out the patterning of the silicon nitride layer as an oxidation preventing mask upon selective oxidation of the silicon substrate, the etching selectivity of the silicon nitride layer to the silicon substrate or the silicon oxide layer formed thereunder can be improved even if the silicon nitride layer is etched under the above conditions. As a result, crystal defects in the silicon substrate due to the etching of the silicon nitride layer can be prevented and also contamination of the silicon oxide layer can be prevented.
Other and further objects and features of the present invention will become obvious in an understanding of the embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims.
Embodiments of the present invention will be explained in detail with reference to the accompanying drawings hereinafter. It should be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings and the explanation of the same or similar parts or elements will be omitted or simplified.
An electrode 3 on which a water (substrate) W is loaded and a gas shower 4 which opposes to the electrode 3 at a distance L are arranged in a quartz chamber 2 of the RIE equipment 1. The gas shower 4 has a plurality of gas injecting holes 4a on the side opposing to the electrode 3. A gas pipe 4b is connected to a part of the gas shower 4. The gas shower 4 is made of conductive material such as aluminum, and can function as the other electrode (4).
A radio frequency power supply RF of a frequency f is connected to the electrode 3, while an earth wire is connected to the gas shower 4.
In
It has been found by the inventors of the present invention that, if an interior of the chamber 2 of the RIE equipment 1 is reduced in pressure, then a fluorine compound gas such as CH2F2, CH3F, or CHF3 and an inert gas such as Ar, He, etc. are introduced into the chamber 2, and then a silicon nitride (Si3N4) film, a silicon oxide (SiO2) film, and a silicon (Si) layer on the wafer W are etched with the use of products obtained by plasmanizing these gases, vertical anisotropic etching of Si3N4 is made possible under the situation that the etching selectivity of Si3N4 to SiO2 or Si is enhanced.
Therefore, results of etching of Si3N4, SiO2, and Si by introducing CH2F2 as the fluorine compound gas and the argon (Ar) gas as the inert gas into the chamber 2 will be explained hereunder. A six-inch silicon wafer has been used as the wafer W herein.
For examination of etching, experiments have been carried out by changing conditions of the distance L between the electrodes and the power supply frequency f of the RIE equipment. The case where the distance L between the electrodes and the power supply frequency f are selected as 70 mm and 13.56 MHZ respectively is set as the first equipment constituting condition, and the case where the distance L between the electrodes and the power supply frequency f are selected as 10 mm and 400 kHz respectively is set as the second equipment constituting condition.
Hence, in order to enhance the etching selectivity of the Si3N4 film to the SiO2 film, it has been evident that it is effective that the argon gas must be introduced and its flow rate must be controlled.
What is derived from the characteristic curves in
When a relationship between an etching rate and a pressure in the chamber 2 has been examined, the results shown in
In the experiment shown in
According to
With the above explanation, it has been found that the etching selectivity of the Si3N4 film to the SiO2 film can be controlled arbitrarily by changing the etching atmospheric pressure.
In addition, it has also been found that, when the Si3N4 film is etched with the use of the CH2F2 gas and the Ar gas, the etching selectivity of the Si3N4 film to the SiO2 film or the Si layer can be enhanced and simultaneously the etching rate can be increased as the flow rate of the argon gas is increased.
In this case, even if the etching rate of the Si3N4 film is increased, i.e., even if the etching selectivity of the Si3N4 film to the SiO2 film is set to more than 10, the Si3N4 film beneath the contact hole is seldom side-etched and therefore good patterns have been obtained.
Next, the results shown in
According to further experiment by the inventors of the present invention, it has been found that preferably the flow rate of the fluorine gas is set to 5 to 50 seem, the flow rate of the inert gas is set three times or more that of the fluorine gas, the etching atmospheric pressure is set to 10 to 500 mTorr, and power applied to the silicon nitride layer is set to 1.1 to 5.5 W/cm2.
Even if another fluorine gas and another inert gas are employed, the same results as the above-mentioned results can be obtained.
Next, when the distance L between the electrodes and the power supply frequency f are set to 10 mm and 400 kHz respectively, the etching rates and the etching selectivities have been examined. In this case, CH2F2 and Ar as the gases used in etching are set to 36 sccm and 290 sccm respectively, the pressure in the etching atmosphere is set to 350 mTorr, and the supplied power of the radio frequency power supply is set to 500 W.
Then, as shown in
Points 1˜3 are possible reasons for the effect of temperature. The sputter ability of ion depends on the Ar flow, the power and the pressure in the atmosphere.
The area on which the radicals stick depends on the temperature, and the sticking amount depends on the frequency of the radio frequency power supply. The high selective ion assist etching is done by adjusting the radical sticking probability and the ion sputter etching at the bottom of the contact hole to suppress the fluorine radical (F*) production and to hasten the CFx* production.
During the experiments to obtain characteristic curves shown in
The result shown in
Next, in order to examine change of the etching rate due to differences in the distance L between the electrodes and the power supply frequency f, the results shown in
This is because ion in the plasma can be effectively catched by the silicon substrate side by making the distance L between the electrodes smaller or making the power supply frequency f lower, so that the higher etching rate of the silicon nitride can be obtained.
Other than the distance L between the electrodes and the power supply frequency f, the etching conditions to detect the characteristics shown in
Next, in the SAC technique shown in
The etching selectivity near the shoulder of the side walls 29 has appeared as distribution shown in
In order to enhance the etching selectivity of the silicon nitride film to the silicon oxide film, it is preferable to set the substrate heating temperature to 20 to 95° C. and to set the power of the radio frequency power supply to more than 350 W. The range of these conditions resides in the left side area rather than a dot-dash line in
Where the temperature labeled on the abscissas in
In turn, an example of the case where the above technique is applied to manufacture of a semiconductor device will be explained hereunder.
In this first example, there will be explained a step of forming a field oxide film on a silicon substrate by the selective oxidation method using the RIE equipment 1 shown in
First, as shown in
Next, as shown in
After this, as shown in
If the fluorine gas and the argon gas are employed to pattern the Si3N4 film for use in selective oxidation as above, the SiO2 film 12 in the device isolation region has not been etched and has still remained though it is thin, so that the surface of the silicon substrate 11 has not been exposed. As a result, the surface of the silicon substrate 11 can be protected by the SiO2 film 12 and therefore contamination and generation of crystal defect upon etching can be prevented.
First of all, steps of forming a configuration shown in
The field oxide film 22 is formed on the silicon substrate 21 by the selective oxidation method. The field oxide film 22 is formed to surround a device forming region A. Formation of this field oxide film 22 may be carried out according to common conditions, otherwise it may be carried out along the steps being explained in the first example. An about 60 Å thick gate insulating layer 23 made of SiO2 is formed in the device forming region A.
Then, a polysilicon layer 24, a silicide layer 25, and a first cap layer 26 made of SiO2 are formed in sequence on the overall silicon substrate 21 to have thicknesses of 500 Å, 700 Å, and 800 Å respectively. The silicide film 25 is made of tungsten silicide, titanium silicide, etc. and is formed by the salicide technique. The polysilicon layer 24, the silicide layer 25, and the first cap layer 26 are patterned like stripes, as shown in
These word lines WL are formed to pass through on the gate insulating layer 23 or the field oxide film 22. Portions of the word lines WL passing through on the gate insulating layer 23 may function as the gate electrode of the MOS transistor. The word line WL may be formed to pass through not only on the field oxide film 22 but also boarders between the field oxide film 22 and the device forming region A. In addition, a plurality of word lines WL are arranged at a distance in the device forming region A.
Next, an impurity of one conductivity type is introduced into a surface layer of the silicon substrate 21 using the word lines WL and the field oxide films 22 as a mask to thus form a shallow impurity diffusion layer 27 with low impurity concentration. The impurity has an opposite conductivity type to that being included in the silicon substrate 21.
Subsequently, as shown in
After this, the impurity is introduced into both sides of the gate electrode WL in the device forming regions A while using the side walls 29, the first cap layer 26, etc. as a mask and then activated so as to form a deep impurity diffusion layer 30 of high impurity concentration. The source layer and the drain layer in the LDD structure of the MOS transistor are constructed by the deep impurity diffusion layer 30 and the above shallow impurity diffusion layer 27.
Next, as shown in
Thereafter, windows 35a are formed by exposing and developing the photoresist 35. The windows 35a in the photoresist 35 are formed to be positioned over high concentration impurity diffusion layers 30 to which the capacitor is electrically connected, as described later.
Then, as shown in
Thereafter, as shown in
According to such conditions, since the etching rate of the first blanket layer 32 is high and anisotropic etching in the vertical direction can be achieved, the side etching hardly occurs in the first blanket layer 32 but the first protection film 32 still remains. Accordingly, since there is no possibility that the lateral recesses occur in the first covering film 32 on the first cap layers 26, the storage contact holes 36 are never connected. In addition, selectivity and anisotropy of the etching can be sufficiently assured, the first covering layer 32 on the side surfaces of the side walls 29 can be completely removed by excessively etching the first covering layer 32 and therefore the storage contact holes 36 can be prevented from being narrowed on the side surfaces of the side walls 39. In this case, the word lines WL are never exposed from the side walls 29 and the first cap layers 26.
In turn, under the condition shown in
As shown in
After this, an underlying layer 38 of 200 Å thickness is formed on the first intermediate layer 34 and the storage contact layers 37. In addition, as shown in
Then, as shown in
Then, the first covering layer 32, the first protection film 31, and the gate insulating layer 23 positioned below the openings 40 are etched by RIE to form lower portions of the bit line contact holes 41. The etching conditions are set to the same as in the case where the lower portions of the storage contact holes 36 are formed. As a consequence, such a condition can be achieved that side etching of the first covering layer 32 on the side surfaces of the bit line contact holes 41 scarcely occurs, and the first covering layer 32 do not remain on the side surfaces of the side walls 29, and also the word lines WL are not exposed from the side walls 29 and the first cap layers 26.
After this, as shown in
A polysilicon layer 42, a silicide layer 43, and a second cap layer 44 are formed sequentially by CVD in the bit line contact holes 41 and on the underlying layer 38. These layers 42, 43, and 44 are formed under the same conditions as layer growth conditions used to form the word lines WL. In this case, since no first covering layer 32 remains on the side surfaces of the side walls 29 in the bit line contact holes 41 because of vertical anisotropic etching of the first covering layer 32, a contacting area between the polysilicon layer 42 and the high concentration impurity diffusion layer 30 can be assured as designed. Further, since the word lines WL are never exposed from the side walls 29 and the first cap layers 26, the polysilicon 42 constituting the bit line contact portion is in no way brought into contact with the word line WL.
The polysilicon layer 42, the silicide layer 43, and the second cap layer 44 are patterned to form the bit lines BL. A part of the bit line BL is connected to the high concentration impurity diffusion layer 30 via the bit line contact holes 41. Then, insulating side walls 45 are formed on the side surface of the bit line BL in the same manner as the side walls 29 on the side surfaces of the word lines WL are formed.
Then, as shown in
Next, the second protection film 46, the second covering layer 47, and the second interlayer insulating layer 48 are patterned to form capacitor forming openings 49 on the storage contact layer 37. Capacitors each being made up of storage electrode, a dielectric film, and an opposing electrode are formed in the capacitor forming openings 49 respectively.
As constituent material for the side walls 29, 45, Si3N4 in place of SiO2 may be employed together with the above process. However, is such case, it is preferable that the gate insulating layer 26 therebetween should be formed of Si3N4. It has been confirmed according to the experiment that a low frequency below 13.56 MHZ may be similarly used as a frequency of the power supply applied to the substrate if RIE is used, but there can be brought about an effect of improving selective etching of the silicon nitride film at 400 kHz.
The RIE equipment has been employed in the above explanation, but the almost similar effect can be obtained by ECR plasma etching.
Moreover, as the gas to be added to the fluorine gas, other inert gas such as helium or other gas may be employed in addition to argon.
Etching of the silicon nitride film in LOCOS and SAL has been explained in the above example. In addition to this, the above etching process may be applied to the case where the side walls made of Si3N4 are formed or the silicon nitride mask which is used to form recesses in the silicon substrate is formed.
Next, a step of selectively etching the silicon nitride in forming the contact holes by the BLC technique will be explained.
First, steps of forming up to a structure shown in
A groove 52 is formed in the device isolation region of the silicon substrate 51, and then a buried insulating film 53 made of silicon oxide is filled into the groove 52. As a method of filling the buried insulating film 53 into the groove 52, such a method can be employed, for example, that the buried insulating film 53 is formed by CVD in the groove 52 and on the silicon substrate 51 and then the buried insulating film 53 on a surface of the silicon substrate 51 is removed by polishing.
A gate insulating film 54, a gate electrode 55, and a gate covering insulating film 56 are then formed in an active region. Then, low-impurity concentration regions 57s, 57d are formed by ion-implanting the impurity into the silicon substrate 51 on both sides of the gate electrode 55 at a low dosage by use of the gate electrode 55 as a mask. The impurity is phosphorous (P), for example, and has an opposite conductivity to the impurity included in the silicon substrate 51.
Then, an insulating film 58 made of silicon nitride or silicon nitride oxide is formed on the silicon substrate 51, the gate covering insulating film 56, and the low-impurity concentration regions 57s, 57d to have a thickness of 50 nm.
Thereafter, the silicon substrate 51 is loaded in the chamber 2 of the RIE equipment 1 shown in
During reactive ion etching, as mentioned above, the fluorine compound gas consisting of any one of CH2F2, CH3F, and CHF3 and the inert gas such as Ar, He, etc. are introduced into the chamber 2. The flow rate of the fluorine compound gas is set to 5 to 50 sccm, and the flow rate of the inert gas is set more than three times the flow rate of the fluorine compound gas. The pressure in the chamber 2 is set to 10 to 500 mTorr, the substrate heating temperature is set in the range of 20 to 95° C., and the supply power of the radio frequency power supply RF is set in the range of 350 to 700 W.
Under these conditions, the etching selectivity of the silicon nitride to the silicon oxide can be enhanced. Therefore, since the buried insulating film 53 made of silicon oxide is difficult to be etched in the etching step to form the side wall 58s, the silicon substrate 51 is hard to exposed from the side surfaces of the groove 52. In addition, since the surface of the silicon substrate 51 is difficult to be etched, the low-impurity concentration regions 57s, 57d can be suppressed from being thinned.
Then, as shown in
The LDD structure impurity diffusion layers 60s, 60d can be formed on both sides of the gate electrode 55 by the high-impurity concentration regions 59s, 59d and the low-impurity concentration regions 57s, 57d.
Then, as shown in
Then, by heating the metal film 61 and the low-impurity concentration regions 57s, 57d at a temperature of 550° C., silicon and metal as constituent material can be alloyed. As a result, the silicide layers 62s, 62d are formed on surfaces of the low-impurity concentration regions 57s, 57d by the salicide technique. Then, as shown in
After this, as shown in
Then, the silicon substrate 51 is loaded in the chamber 2 of the RIE equipment 1 shown in
The etching of the interlayer insulating film 64 can be etched by the gas including C4F8, CO, Ar, for example. According to such etching gas, the etching selectivity of the interlayer insulating film 64 to the silicon nitride film 63 can be made high so that the silicon nitride film 63 can remain.
As described above, during the etching of the silicon nitride film 63, the fluorine compound gas consisting of any one of CH2F2, CH3F, and CHF3 and the inert gas such as Ar, He, etc. are introduced into the chamber 2. The flow rate of the fluorine compound gas is set to 5 to 50 sccm, and the flow rate of the inert gas is set more than three times the flow rate of the fluorine compound gas. The pressure in the chamber 2 is set to 10 to 500 mTorr, the substrate heating temperature is set in the range of 20 to 95° C., and the supply power of the radio frequency power supply RF is set in the range of 350 to 700 W.
Under these conditions, the etching rate of the silicon nitride film 63 can be enhanced and also etching of the silicon oxide film 53 and the silicon substrate 51 can be suppressed. As a consequence, the silicon substrate 51 can be prevented from being exposed from the groove 52.
Thereafter, as shown in
According to the present invention described above, since the silicon nitride layer is dry-etched while using the fluorine gas composed of any one of CH2F2, CH3, and CHF3 and the inert gas, the etching rate of the silicon nitride layer can be enhanced 10 times or more the etching rate of the silicon oxide layer or the silicon layer beneath the silicon nitride layer and in addition the anisotropic etching thereof can be achieved.
Accordingly, because such etching process is employed in the SAC step for the semiconductor device, the silicon nitride layer can be excessively etched not to remain the silicon nitride on the side surfaces of the side walls of the gate electrodes and furthermore the silicon oxide layer covering the gate electrodes is never removed by etching. As a result, the contact region formed between two side walls can be prevented from being narrowed and also short-circuit between the gate electrodes and conductive layers in the contact holes can be prevented.
Various advantages not referred to herein will occur to one skilled in the art in employing of the invention in practice. Many variations of such embodiments exist and such variations are intended to be within the scope of the present invention and the appended claims.
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
4844773, | Jul 16 1987 | Texas Instruments Incorporated | Process for etching silicon nitride film |
5002632, | Nov 22 1989 | Texas Instruments Incorporated | Method and apparatus for etching semiconductor materials |
5503901, | Jun 30 1993 | Kabushiki Kaisha Toshiba | Surface treatment method and surface treatment apparatus |
5716494, | Jun 22 1993 | Matsushita Electric Industrial Co., Ltd. | Dry etching method, chemical vapor deposition method, and apparatus for processing semiconductor substrate |
5843846, | Dec 31 1996 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Etch process to produce rounded top corners for sub-micron silicon trench applications |
5874013, | Jun 13 1994 | Renesas Electronics Corporation | Semiconductor integrated circuit arrangement fabrication method |
6731008, | Apr 22 1996 | Acacia Research Group LLC | Semiconductor device with conductive contact layer structure |
DE4232475, | |||
JP2240927, | |||
JP59222933, | |||
JP61142744, | |||
JP62102530, | |||
JP62163328, | |||
JP62696622, | |||
JP677175, | |||
JP7335612, | |||
JP774145, | |||
JP8111405, |
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