Decoding apparatus for low-density parity-check codes using sequential decoding, and method thereof

Abstract

Disclosed is a decoding apparatus for ldpc (low-density parity-check) codes when receiving data encoded with ldpc codes on a channel having consecutive output values, and a method thereof. The decoding method for ldpc codes uses sequential decoding and includes the following steps: (a) the nodes are divided according to a parity-check matrix into check nodes for a parity-check message and variable nodes for a bit message; (b) the check nodes are divided into a predetermined number of subsets; (c) the ldpc codeword of each subset for all the check nodes is sequentially decoded; (d) an output message is generated for verifying validity of the decoding result; and (e) the steps (b), (c), and (d) are iteratively performed by a predetermined number of iterations.

Description

CROSS REFERENCE TO RELATED

In the Equation 1, L(q_ij) is the output message of the variable node 410, and L(x_j) is the input message of the variable node 410 transmitted from the channel. Namely, the output message of the variable node 410 is the same as the input message of the variable node 410 transmitted from the channel during the initialization.

The output message 450 of the check node 420 is calculated according to the following Equation 2.

$\begin{array}{cc}L\left(r_{\mathrm{ij}}\right)=(\left(\prod _{j^{*}\in R\left(i\right)/j}\mathrm{sgn}\left(L\left(q_{{\mathrm{ij}}^{*}}\right)\right)·\varphi \left(\sum _{j^{*}\in R\left(i\right)/j}\varphi \left(L\left(q_{{\mathrm{ij}}^{*}}\right)\right)\right)\right)& \left[\mathrm{Equation}2\right]\end{array}$

Here, L(r_ij) 450 is the output message of the i-th check node 420 fed into the j-th variable node 410; R(i) is an index set of the variable nodes connected to the check nodes i 420; and R(i)/j is an index set of the variable nodes connected to the check nodes i 420 other than j.

The output message of each variable node 410 after the initialization is given by the following Equation 3.

$\begin{array}{cc}L\left(q_{\mathrm{ij}}\right)=L\left(x_j\right)+\left(\sum _{i^{*}\in C\left(j\right)/i}L\left(r_{i^{*}j}\right)\right)& \left[\mathrm{Equation}3\right]\end{array}$

Here, C(j) is an index set of check nodes 420 connected to the variable nodes j 410; and C(j)/i is an index set of the check nodes 420 connected to the variable nodes j 410 other than i. The message passed to the information-restoring section 333 after processing each variable node 410 and each check node 420 is calculated according to the following Equation 4.

$\begin{array}{cc}L\left(Q_i\right)=L\left(x_j\right)+\left(\sum _{i^{*}\in C\left(j\right)}L\left(r_{i^{*}j}\right)\right)& \left[\mathrm{Equation}4\right]\end{array}$

Here, L(Q_i) is an updated vector of LLR for each bit of the i-th partial codeword. The respective components in the vector are operated with one another, for the function and the calculation of the vectors according to the Equation 4. The information-restoring section 333 that is a data decoder arranges the output vector messages L(Q_i) of the decoding section 332 in sequence to generate a message. Then, the codeword is decided from the generated message according to the following Equation 5.

$\begin{array}{cc}{\hat{x}}_i=\{\begin{array}{c}1\mathrm{if}L\left(Q_i\right)<0,\\ 0\mathrm{otherwise}\end{array}& \left[\mathrm{Equation}5\right]\end{array}$

FIGS. 5a, 5b, and 5c show a one-cycle iteration decoding process of a (2,4) regular LDPC code having a length of 4 according to an embodiment of the present invention. The message-passing decoder 400 of FIG. 4 iterates the operations of the Equations 1 to 4 to exchange messages between variable nodes 510 and check nodes 520 for decoding.

Hereinafter, an apparatus and method for decoding LDPC codes according to an embodiment of the present invention will be described.

FIG. 6 shows a graph in which check nodes are divided by a size l into p subsets. The check nodes 620 are divided into subsets 630.

Referring to FIG. 6, a regular LDPC code has a code length of n, and the number of check nodes 620 is m. There may be various methods of dividing the check nodes 620 into several subsets 630. Here, a description will be given as to a simplest method that constructs subsets having a constant number of elements.

The check nodes 620 are divided into subsets 630 having l elements by a defined method. So, the number p of the subsets of the check nodes 620 is p=m/l.

The subset construction method that the number of elements of the subsets 630 is not constant shows a similar decoding performance to the subset construction method in which the number of elements is constant. But, the method that the subsets 630 have a different number of elements can have higher performance according to the connection state of the edges connecting the nodes 610 and 620 in the LDPC codes. For example, the performance is all the same in many cases when the number of the subsets 630 optionally determined is constant for irregular LDPC codes constructed to have an irregular number of variable nodes 610 connected to the check nodes 620. Namely, the decoding performance is almost the same when the total number p of the subsets 630 is constant even though each subset 630 has a different number of elements.

The number of the subsets 630 is determined by the characteristic of the codes generated. Generally, it is advantageous in the aspect of coding that the number p of the subsets 630 is equal to or greater than the maximum order in the variable nodes 610. When the number of the subsets 630 is less than the maximum order, it becomes problematic in the aspect of decoding order or decoding independence because there is a case in which one variable check 610 is connected to two check nodes 620 in the subset 630.

The addition of a condition that all the edges connected to a specific variable node 610 are included in different subsets 630 may enhance the decoding performance.

FIGS. 7a to 7d show a one-cycle iteration decoding process of LDPC codes using sequential decoding when check nodes are divided into subsets according to an embodiment of the present invention, for a (2,4) regular LDPC code having a length of 4 when the number p of the subsets is 2. Namely, FIGS. 7a to 7d shows a decoding method of the decoding section 332 when the check nodes are divided into p subsets. Expediently, a (2,4) regular LDPC code having a length of 4 is used herein as in the embodiment of FIGS. 5a, 5b, and 5c.

For p=2, the number of subsets 730 and 740 is 2, and the groups 730 and 740 of l (=4) variable nodes 710 are the subsets 730 for one check node 720.

Hence, there are p(=2) subsets in this embodiment of the present invention, and each of the subsets 730 and 740 is considered as one sub-code, which functions as a unit decoder. This is similar to the structure of a decoder for Turbo codes that comprises at least two unit decoders each transmitting independent extrinsic information to another decoder using an interleaver.

The decoding operations of the Equations 1 to 4 are performed in the respective subsets 730 and 740. In the operation of the Equation 2 according to the embodiment of the present invention, the inputs for the check nodes 720 are divided into a variable node message updated by the subsets 730 of the previous check nodes and a non-updated variable node message.

The operation of the check nodes 720 can be expressed as the following Equation 6.

$\begin{array}{cc}L\left(r_{\mathrm{ij}}\right)=\left(\prod _{j^{*}\in R_0\left(i\right)/j}\mathrm{sgn}\left(L\left(q_{{\mathrm{ij}}^{*}}\right)\right)·\prod _{j^{*}\in R_1\left(i\right)/j}\mathrm{sgn}\left(L\left(q_{{\mathrm{ij}}^{*}}\right)\right)\right)·\varphi \left(\sum _{j^{*}\in R_0\left(i\right)/j}\varphi \left(L\left(q_{{\mathrm{ij}}^{*}}\right)\right)+\sum _{j^{*}\in R_1\left(i\right)/j}\varphi \left(L\left(q_{{\mathrm{ij}}^{*}}\right)\right)\right)& \left[\mathrm{Equation}6\right]\end{array}$

Here, R₀(i) and R₁(i) are an index set of the variable nodes 710 connected to the check nodes i 720; R₀(i)/j is an index set of non-updated variable nodes 710 connected to the check nodes i 720 other than j; and R₁(i)/j is an index set of variable nodes 710 connected to the check nodes i 720 other than j and already updated by the previous subsets 730.

The operation for the variable nodes 710 and the subsequent operations are the same as described in the Equations 3, 4, and 5.

FIG. 8 is a schematic of a decoder 800 for LDPC codes using sequential decoding according to an embodiment of the present invention.

Referring to FIG. 8, the decoder 800 according to an embodiment of the present invention comprises an input buffer memory 810, a variable node message updater 820, a variable node output memory 830, a check node processor 840, a check node output memory 850, an output buffer memory 860, a decoding operation controller 870, and a parity-check matrix memory 880.

First, the input buffer memory 810 stores an input message of the decoder 800. The variable node message updater 820 receives an input from the input buffer memory 810 and the check node output memory 850 and performs the operation of the Equation 1 or 3, i.e., processes the output message of the variable nodes after the initialization according to the Equation 1 or 3.

The variable node output memory 830 stores the processing result. The check node processor 840 receives the stored data and performs the operation of the Equation 2, i.e., processes the output message of the check nodes according to the Equation 2.

Subsequently, the check node output memory 850 stores the processing result of the output message of the check nodes. The stored data are updated by the variable check message updater 820 and then stored in the variable node output memory 830 again.

The data of the variable node output memory 830 are message-updated as often as the number of the subsets. After the completion of the decoding operation on one subset, the connection state of nodes and edges in the variable node memory updater 820 and the check node processor 840 is loaded from the decoding operation controller 870 to reset nodes and edges for the next subset.

After the completion of the iterative operation for all the subsets, the decoding result is transmitted to the information-restoring section 333 through the output buffer memory 860 to verify its validity.

This process is iterated a predetermined number of iteration times. The decoding operation controller 870 determines all kinds of operations related to the decoding operation.

In the decoding method for LDPC codes according to an embodiment of the present invention, the check nodes are divided into several subsets during the decoding process, and the subsets are decoded according to their priority with several decoders. Here, the convergence rate for a bit error rate is variable according to the determination method of the subsets. The higher convergence rate means higher enhancement of the code performance with a smaller number of decoding iterations. Compared with the general LDPC decoding method, this decoding method only changes the order of operations of the decoder without increasing the complexity.

The embodiment of the present invention can decode a codeword with a smaller number of decoding iterations in most of the cases of iterative decoding of LDPC codes. Relative to the conventional method, the method of the present invention has much enhanced performance in the situation that the number of decoding iterations is small. In addition, the method of determining the codeword upon interruption of the decoding in the middle of the decoding process while the parity-check equation of the Equation 6 is satisfied may reduce the time taken for the decoding and show a higher performance for the same complexity as compared with the conventional method.

FIGS. 9 and 10 show the results of a simulation for performance evaluation of the decoding method. Here, the channel environment is assumed as an additive white Gaussian noise (AWGN) channel. The message determined at each node, which is exchanged through the edge, carries a log likelihood ratio (LLR).

FIG. 9 shows a performance graph according to the number of decoding iterations and the number of subsets of irregular LDPC codes having a codeword length of 1000 and a code rate of 1/2. FIG. 10 shows a performance graph according to the number of decoding iterations and the number of subsets of (3, 6) regular LDPC codes having a codeword length of 4092 and a code rate of 1/2.

In the embodiment of the present invention, the number of the subsets is a divisor of the total number of check nodes, and the respective subsets are all the same in the number of elements. The value p is 1, 3, or 4, where the decoding method for p=1 is the same as the conventional message-passing algorithm. In the figure, I means the number of decoding iterations.

Referring to FIG. 9, the decoding performance for irregular IDPC codes having a codeword length of 1000 and a code rate of 1/2 is shown over a bit error ratio (BER) for a signal-to-noise ratio

$\frac{E_b}{N_0}.$
When p is greater than 2, the decoding performance is higher even with a small number of decoding iterations (in curves 910 and 920). But, the decoding performance approaching the maximum performance of the codes is not so enhanced with a large number of decoding iterations.

Referring to FIG. 10, the decoding performance for regular IDPC codes having a codeword length of 4092 and a code rate of 1/2 is shown. In FIG. 10, the decoding performance with a small number of decoding iterations (in curves 1010 and 1020) is much more enhanced than in FIG. 9. The reason for this is that the number of elements in the subsets increases for a small number of decoding iterations with a four-fold increase in the codeword length of the LDPC codes, i.e., from 1000 to 4092, to enhance the message updating effect of the unit codes. Also, in the case of the irregular LDPC codes of FIG. 9, the enhancement of the decoding performance increases with an increased length of the codeword.

While this invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

As described above, the present invention assigns a priority to each subset of the check nodes for decoding in the conventional decoding method of LDPC codes to provide a higher decoding performance with a small number of decoding iterations and almost the same complexity. In addition, the present invention hastens the decision of the decoding success/failure in the decoder and hence guarantees high speed decoding by the reduction of the decoding time.

Claims

1. A method for a decoding apparatus to decode, the method comprising:

(a) dividing, by a message-passing decoder of the decoding apparatus, nodes into check nodes for a parity-check message and variable nodes for a bit message according to a parity-check matrix;

(b) dividing, by the message-passing decoder of the decoding apparatus, the check nodes into a predetermined number of subsets;

(c) sequentially decoding, by the message-passing decoder of the decoding apparatus, a ldpc (low density parity check) codeword of each subset for all the check nodes;

(d) generating, by the message-passing decoder of the decoding apparatus, an output message for verifying validity of the decoding result; and

(e) iteratively performing, by the message-passing decoder of the decoding apparatus, the steps (b), (c), and (d) by a predetermined number of iterations, wherein the number of decoding iterations is reduced according to an increase in the convergence rate when the validity of the ldpc codeword is determined from the output message of the step (d).

2. The method as claimed in claim 1, further comprising: interrupting the decoding operation when the output message of the step (d) satisfies a defined decoding check equation.

3. The method as claimed in claim 1, wherein the number of decoding iterations is fixed at a value smaller than the maximum number of decoding iterations during the iterative decoding process.

4. The method as claimed in claim 1, wherein each of the subsets of the check nodes is decoded with a different priority.

5. The method as claimed in claim 4, wherein the subset for highest-order variable nodes connected to the check nodes is decoded with a highest priority.

6. The method as claimed in claim 1, wherein the step (b) comprises: dividing the check nodes into subsets each having a different number of elements.

7. The method as claimed in claim 6, wherein the number of the subsets is an integer other than a divisor of the number of the check nodes.

8. A method for a decoding apparatus to decode, the method comprising:

(a) dividing, by a message-passing decoder of the decoding apparatus, nodes into check nodes for a parity-check message and variable nodes for a bit message according to a parity-check matrix;

(b) dividing, by the message-passing decoder of the decoding apparatus, the check nodes into a predetermined number of subsets;

(c) sequentially decoding, by the message-passing decoder of the decoding apparatus, a ldpc (low density parity check) codeword of each subset for all the check nodes;

(d) generating, by the message-passing decoder of the decoding apparatus, an output message for verifying validity of the decoding result; and

(e) iteratively performing, by the message-passing decoder of the decoding apparatus, the steps (b), (c), and (d) by a predetermined number of iterations, wherein the step (e) comprises: changing the decoding order of the subsets used in a previous decoding operation when the number of decoding iterations is increased.

9. The method as claimed in claim 8, comprising: reversing the decoding order used in the previous decoding operation, or determining a new decoding priority to the subsets.

10. The method as claimed in claim 8, comprising: differentiating the decoding priority to the subsets of the check nodes according to the number of decoding iterations.

11. An apparatus comprising:

a codeword regenerator for regenerating ldpc codes received through a channel into a codeword for decoding;

a message-passing decoder for sequentially decoding the ldpc codeword of each subset for all check nodes, the check nodes being divided into predetermined subsets, wherein the message-passing decoder comprises:

a parity-check matrix memory for storing a parity-check matrix,

an input buffer memory for storing an input message, and

a variable node message updater for receiving an input from the input buffer memory and a check node output memory and processing an output message of the variable nodes according to the stored parity-check matrix; and

an information-restoring section for determining whether there is an error in the decoded codeword, and extracting and transmitting information when there is no error in the codeword.

12. The apparatus as claimed in claim 11, wherein the message-passing decoder exchanges messages through defined edges between check nodes for a parity-check message and variable nodes for a bit message according to a parity-check matrix to update a node message.

13. The apparatus as claimed in claim 12, wherein the number of subsets is equal to or greater than a maximum order of the variable nodes.

14. The apparatus as claimed in claim 12, wherein each of all the edges connected to a specific one of the variable nodes is included in a different subset.

15. The apparatus as claimed in claim 11, wherein the message-passing decoder comprises:

a variable node output memory for storing a result of the variable node message updater;

a check node processor for receiving data stored in the variable node output memory to process the output message of the check nodes, and transmitting the processed output message to the variable node message updater;

a check node output memory for storing a processing result of the output message of the check nodes;

an output buffer memory for transmitting the decoding result to the information-restoring section so as to verify validity of the decoding result, after completion of the decoding operation for all the subsets; and

a decoding operation controller for determining all kinds of operations related to the decoding operation.

16. The apparatus as claimed in claim 15, wherein the data of the variable node output memory are message-updated as often as the number of the subsets.

17. The apparatus as claimed in claim 15, wherein after the completion of the decoding operation on one subset, the connection state of nodes and edges in the variable node message updater and the check node processor is loaded from the decoding operation controller to reset nodes and edges for a next subset.

18. The apparatus as claimed in claim 11, wherein the decoding operation of the message-passing decoder is iteratively performedwith a predetermined number of decoding iterations.

19. A method for a decoding apparatus to decode, the method comprising:

(a) dividing, by a message-passing decoder of the decoding apparatus, nodes into check nodes for a parity-check message and variable nodes for a bit message according to a parity-check matrix;

(b) dividing, by the message-passing decoder of the decoding apparatus, the check nodes into a predetermined number of subsets;

(c) sequentially decoding, by the message-passing decoder of the decoding apparatus, a low density parity check codeword of each subset for all the check nodes;

(d) generating, by the message-passing decoder of the decoding apparatus, an output message; and

(e) iteratively performing, by the message-passing decoder of the decoding apparatus, the steps (b), (c), and (d) by a predetermined number of iterations, wherein the number of decoding iterations is reduced according to an increase in the convergence rate when a validity of the low density parity check codeword is determined from the output message of the step (d).

20. A method for a decoding apparatus to decode, the method comprising:

(a) dividing, by a message-passing decoder of the decoding apparatus, nodes into check nodes for a parity-check message and variable nodes for a bit message according to a parity-check matrix;

(b) dividing, by the message-passing decoder of the decoding apparatus, the check nodes into a predetermined number of subsets;

(c) sequentially decoding, by the message-passing decoder of the decoding apparatus, a low density parity check codeword of each subset for all the check nodes;

(d) generating, by the message-passing decoder of the decoding apparatus, an output message; and

(e) iteratively performing, by the message-passing decoder of the decoding apparatus, the steps (b), (c), and (d) by a predetermined number of iterations, wherein the step (e) comprises: changing the decoding order of the subsets used in a previous decoding operation when the number of decoding iterations is increased.

21. An apparatus comprising:

a codeword regenerator that regenerates low density parity check codes received through a channel into a codeword for decoding;

a message-passing decoder that sequentially decodes the low density parity check codeword of each subset for all check nodes, the check nodes being divided into predetermined subsets, wherein the message-passing decoder comprises:

a parity-check matrix memory that stores a parity-check matrix,

an input buffer memory that stores an input message, and

a variable node message updater that receives an input from the input buffer memory and a check node output memory and processes an output message of the variable nodes according to the stored parity-check matrix; and

an information-restoring section that determines whether there is an error in the decoded codeword and extracts information when there is no error in the codeword.