DC/DC converter with adaptive drive voltage supply

Abstract

A circuit comprises a first input for receiving a supply voltage and a second input for receiving a sensed current signal from an output of a dc to dc converter. The circuit also includes an output voltage for providing an adjustable drive voltage to a drive circuit. The circuit additionally includes circuitry for adjusting the drive voltage responsive to supply voltage and the sensed current signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a
P_out=V₀×I_out
P₁=VCC×ICC
P₁=V_in×I_n
P₃=Vdr×Idr

Thus, the value of Vdr provided to the driver circuit 106 may be altered such that the value of P₃ will change in the above equation. The value of P₃ may then be set based upon the determined load current through node 504 such that the efficiency of the DC to DC converter is provided at a maximum value over a range of load currents.

Referring now to FIGS. 6-8, there are illustrated various embodiments of the adaptive drive voltage supply 302 according to the present disclosure. While the present examples provided in FIGS. 6-8 describe manners for generating a variable output voltage to maximize the load efficiency responses to a detected load current based upon measurements from a current sensor 118, the present invention envisions the use of the switching frequency in addition to the load current or the switching frequency alone also being used as an input variable to establish a variable output voltage to maximize load efficiencies within a switched power circuit.

In a first embodiment illustrated in FIG. 6, a series pass liner regulation configuration is used. The adaptive drive voltage supply 302 is connected to receive an input voltage V_in from the driver supply voltage 110 as described herein above. The adaptive voltage supply 302 additionally receives a sensed current I_sen from the current sensor 118. An OpAmp 602 has its positive input connected to receive the I_sen signal at node 604. Also connected to node 604 is a resistor 606 which is also connected to ground. The negative input of OpAmp 602 is connected to a feedback network consisting of resistor 608 and 610. The negative input of OpAmp 602 is connected to node 607, and resistor 608 is connected between node 607 and ground. Resistor 610 is connected between node 607 and node 612. A transistor 614 has its drain/source path connected between the V_in input to the adaptive drive voltage supply 302 and node 612. The gate of transistor 614 is connected to the output of comparator circuit 602. Node 612 provides the adjustable output voltage V_out which is applied to the driver circuit 106. The output voltage of V_out is provided to the drain of a first transistor 620 of a transistor pair which are the UGate driver transistors of the power stage 108. The adjustable voltage V_out is also provided to the drain of a first transistor 622 of a pair of transistors driving the lower gate driver transistors of the power stage 108. The gates of these transistors 620 and 622 receive control signals from the controller 104.

This configuration represents, but is not limited to, a series pass linear regulator implementation. Any linear application that achieves the result of a current controlled voltage source for the purpose of varying gate drive voltage as a function of load current in switching power supply applications for overall improved system efficiency is implied by this implementation. The above described implementation provides an output voltage V_out=R₃×(1+R₁/R₂)×I_sen. Efficiency=V_out/V_in. Thus, the variable output drive voltage is controlled to vary linearly over an established ramp by selecting the appropriate values of R₁, R₂ and R₃.

Referring now to FIG. 7, there is illustrated a second embodiment of the adaptive drive voltage supply 302 providing a higher efficiency switching regulator implementation. This configuration is for use with a buck regulator implementation. However, any switching application that achieves the result of a current controlled voltage source with higher efficiency for the purpose of varying gate drive voltage as a function of low current switching power applications, or overall improved system efficiency may use a similar configuration. As described previously, the adaptive drive supply voltage 302 receives an input voltage V_in from the driver supply voltage 110 and a current sense signal I_Sen from the current sense circuitry 118. Additionally, the circuitry receives an input PWM ramp signal. The input current sense signal I_sen is applied to an input node 702. A resistor 704 is connected between node 702 and ground. A OpAmp 706 has its positive input connected to the I_sen node 702. The negative input of OpAmp 706 is connected to a feedback network at node 708. A first impedance 710 is connected between the output of the comparator 706 at node 712 and node 708. A second impedance 714 is connected between node 708 and 716. The output of the OpAmp 706 at node 712 is connected to a positive input of a second OpAmp 718. The negative input of OpAmp 718 is connected to receive the PWM ramp signal. The output of OpAmp 718 is connected at node 720 to the gates of transistors 722 and 724. The drain/source path of n-type transistor 722 is connected between the input node receiving the adjustable input voltage V_in and node 726. The second p-type transistor 724 has its drain/source path connected between node 726 and ground. An inductor 728 is connected between node 726 and node 716. A capacitor 732 is connected between node 716 and ground. Node 716 provides the adjustable output voltage of V_out to a drain of a first transistor 620a. The output voltage of V_out is provided to the drain of a first transistor 620 of a transistor pair which are the UGate driver transistors of the power stage 108. The adjustable voltage V_out is also provided to the drain of a first transistor 622 of a pair of transistors driving the lower gates of the power stage 108. The gates of these transistors 620 and 622 receive control signals from the controller 104. The variable output voltage of the device is controlled by setting resistor R₁ and impedances Z₁ and Z₂ to appropriate values.

Referring now to FIG. 8a, there is illustrated a further embodiment for an adaptive drive voltage supply 302 which provides multiple gate drive voltages to the driver circuit 106. This configuration includes a first adaptive drive voltage supply 302a and a second adaptive voltage supply 302b. Each of the adaptive voltage supplies 302 are supplied a voltage from the driver supply voltage 110 and receive a sensed current signal I_sen from the current sense circuit 118. The adaptive drive voltage supply blocks 302 may comprise either of the two embodiments illustrated in FIGS. 6 and 7, respectively, or even may use other configurations. Each adaptive drive voltage supply blocks 302 can be programmed independently to provide two different variable output voltages to further improve the efficiency of the DC to DC power converter. The adaptive drive voltage supply block 302a supplies an adjustable voltage to the drain of a first transistor 622a of a lower transistor pair driving the lower gates of the power stage circuitry 108. The adjustable voltage provided from adaptor drive voltage supply 302b is provided to the drain of an upper transistor 620a of a pair of transistors driving the upper gate transistors of the switched power supply 108. As before, the gates of the transistors in the driver circuit 106 receive switching control signals from the controller 104.

In addition to using an analog implementation that uses the resistor and impedance network to program the variable voltage output, digital control signals may be generated to control the variable output voltage using any number of digital circuit configurations as illustrated in FIG. 8b.

Using the input voltage V_IN to output load current I_OUT/I_L and the switching frequency F_SW, the drive voltage may be controlled. This analysis attempts to derive an efficiency optimized Vgs as a function of output load, to minimize the sum of driver switching loss and FET losses related to Rdson.

Using the datasheet for the Infineon BSC022N03S Power MOS, the Rdson vs. Vgs data is linearized for 5V<Vgs<10V, whereby the factor Kr defines the linearized rate of change. Similarly, Kg is defined as the rate of change of Qg for a given change in Vgs.

The power loss for the driver and the FET is given by the equation:
Ptotal=(Qg×Vgs×fsw)+(Rdson×Iout²)

Finding dPtotal(Vgs)/dVgs and setting it to ZERO will yield the minimum Ptotal(Vgs).

Using the linearized substitutions:
Rdson=−Kr×ΔVgs
Qg=Kg×ΔVgs
Ptotal(Vgs) and dPtotal(Vgs)/dVgs are derived, yielding:
2KgVgsfs−KrIout²=0
By isolating Vgs:
Vgs=(Kr×Iout^2)/(2×Kg×fs)

Plotting Vgs(Iout) within a realistic range of Iout, and for various frequencies (20K, 75K, 150K, 300K, 500K, 750K, and 1M), the results illustrated in FIG. 9 are provided. Intuitively, for the non linear portion of Rdson that falls in the range 3V<Vgs<5V, all curves will converge to the FET threshold voltage.

$\mathrm{dVgx}:=5$ $\mathrm{dRs}:=1.1·{10}^{-3}$ $\mathrm{Kr}:=\frac{d\mathrm{Rds}}{d\mathrm{Vgs}}$ $\mathrm{dQg}:=40·{10}^{-9}$ $\mathrm{Kg}:=\frac{d\mathrm{Qg}}{d\mathrm{Vgs}}$ $\mathrm{fs}:=20000$ $\mathrm{fs}1:=75000$ $\mathrm{fs}2:=150000$ $\mathrm{fs}3:=300000$ $\mathrm{fs}4:=500000$ $\mathrm{fs}5:=750000$ $\mathrm{fs}6:=1000000$ $\mathrm{Vg}1\left(\mathrm{Io}\right):=\frac{\mathrm{Kr}}{2·\mathrm{Kg}·\mathrm{fs}}{\mathrm{Io}}^2$ $\mathrm{Vg}2\left(\mathrm{Io}\right):=\frac{\mathrm{Kr}}{2·\mathrm{Kg}·\mathrm{fs}2}{\mathrm{Io}}^2$ $\mathrm{Vg}3\left(\mathrm{Io}\right):=\frac{\mathrm{Kr}}{2·\mathrm{Kg}·\mathrm{fs}3}{\mathrm{Io}}^2$ $\mathrm{Vg}4\left(\mathrm{Io}\right):=\frac{\mathrm{Kr}}{2·\mathrm{Kg}·\mathrm{fs}4}{\mathrm{Io}}^2$ $\mathrm{Vg}5\left(\mathrm{Io}\right):=\frac{\mathrm{Kr}}{2·\mathrm{Kg}·\mathrm{fs}5}{\mathrm{Io}}^2$ $\mathrm{Vg}6\left(\mathrm{Io}\right):=\frac{\mathrm{Kr}}{2·\mathrm{Kg}·\mathrm{fs}6}{\mathrm{Io}}^2$

A more accurate plot can be derived by curve fitting a set of data from a matrix to a polynomial function to derive Rds (Vgs) that would hold true from Vth to the upper limit of Vgs.

Additionally, thermal compensation will ensure that the Vgs applied will continue to yield minimum power loss, as Rds changes with T.

Additional detailed analysis may be required to quantify the merits, such as the efficiency gains, as well as the added complexity of creating a variable voltage rail, in the near future.

It will be appreciated by those skilled in the art having the benefit of this disclosure that this invention provides a gate driver topology providing improved load efficiency. It should be understood that the drawings and detailed description herein are to be regarded in an illustrative rather than a restrictive manner, and are not intended to limit the invention to the particular forms and examples disclosed. On the contrary, the invention includes any further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments apparent to those of ordinary skill in the art, without departing from the spirit and scope of this invention, as defined by the following claims. Thus, it is intended that the following claims be interpreted to embrace all such further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments.

Claims

1. A dc to dc converter circuit, comprising:

a power stage for generating a regulated dc output voltage responsive to drive signals;

a driver circuit for generating the drive signals for power transistors in the power stage responsive to an adjustable supply voltage and drive control signals;

a controller for generating the drive control signals to the driver circuit responsive to a sensed current signal at least the regulated dc output voltage;

a current sensor for generating the a sensed current signal responsive to a sensed current in the power stage;

an adaptive drive voltage supply responsive to a supply voltage, the sensed current signal and a switching frequency of the power transistors in the power stage for generating the adjustable supply voltage.

2. The dc to dc converter circuit of claim 1, wherein the current sensor senses a load current of the power stage.

3. The dc to dc converter circuit of claim 2, wherein the adaptive drive voltage supply varies the adjustable supply voltage responsive to the sensed load current to improve an efficiency of the dc to dc converter circuit over a wide range of load currents.

4. The dc to dc converter circuit of claim 1, wherein the adaptive drive voltage supply adjusts the adjustable supply voltage responsive to a digital control signal.

5. The dc to dc converter circuit of the claim 1, wherein the adaptive drive voltage supply comprises a linear voltage regulator responsive to the supply voltage and the sensed current signal to linearly adjust the adjustable supply voltage between a first voltage responsive to a first sensed current signal and a second voltage responsive to a second sensed current signal.

6. The dc to dc converter circuit of claim 1, wherein the adaptive drive voltage supply comprises a switching voltage regulator responsive to the supply voltage and the sensed current signal to adjust the adjustable supply voltage.

7. The dc to dc converter circuit of claim 1, wherein the adaptive drive voltage supply comprises a plurality of adaptive drive voltage supplies, each of the plurality of adaptive drive voltage supplies providing a different adjustable supply voltage for a portion of the power transistors of the power stage.

8. A dc to dc converter circuit, comprising:

a power stage for generating a regulated dc output voltage responsive to drive signals;

a driver circuit for generating the drive signals for power transistors in the power stage responsive to an adjustable supply voltage and drive control signals;

a controller for generating the drive control signals to the driver circuit responsive to a sensed current signal at least the regulated dc output voltage;

a current sensor for generating the a sensed current signal responsive to a sensed current in the power stage;

an adaptive drive voltage supply responsive to a supply voltage and the sensed current signal for generating the adjustable supply voltage, wherein the adaptive drive voltage supply comprises a plurality of adaptive drive voltage supplies, each of the plurality of adaptive drive voltage supplies providing a different adjustable supply voltage for a portion of the power transistors of the power stage.

9. The dc to dc converter circuit of claim 8, wherein the adaptive drive voltage supply adjusts the adjustable supply voltage responsive to a digital control signal.

10. The dc to dc converter circuit of claim 8, wherein the current sensor senses a load current of the power stage.

11. The dc to dc converter circuit of claim 10, wherein the adaptive drive voltage supply varies the adjustable supply voltage responsive to the sensed load current to improve an efficiency of the dc to dc converter circuit over a wide range of load currents.

12. The dc to dc converter circuit of claim 8, wherein the adaptive drive voltage supply is further responsive to a switching frequency of the power transistors in the power stage.

13. The dc to dc converter circuit of the claim 8, wherein the adaptive drive voltage supply comprises a linear voltage regulator responsive to the supply voltage and the sensed current signal to linearly adjust the adjustable supply voltage between a first voltage responsive to a first sensed current signal and a second voltage responsive to a second sensed current signal.

14. The dc to dc converter circuit of claim 8, wherein the adaptive drive voltage supply comprises a switching voltage regulator responsive to the supply voltage and the sensed current signal to adjust the adjustable supply voltage.

15. A dc to dc converter circuit, comprising:

a power stage for generating a regulated dc output voltage responsive to drive signals;

a driver circuit for generating the drive signals for power transistors in the power stage responsive to an adjustable supply voltage and drive control signals;

a controller for generating the drive control signals to the driver circuit responsive to a sensed current signal at least the regulated dc output voltage;

a current sensor for generating the a sensed current signal responsive to a sensed current in the power stage;

an adaptive drive voltage supply responsive to a supply voltage and the sensed current signal for generating the adjustable supply voltage, wherein the adaptive drive voltage supply adjusts the adjustable supply voltage responsive to a digital control signal.

16. The dc to dc converter circuit of claim 15, wherein the current sensor senses a load current of the power stage.

17. The dc to dc converter circuit of the claim 16, wherein the adaptive drive voltage supply comprises a linear voltage regulator responsive to the supply voltage and the sensed current signal to linearly adjust the adjustable supply voltage between a first voltage responsive to a first sensed current signal and a second voltage responsive to a second sensed current signal.

18. The dc to dc converter circuit of claim 16, wherein the adaptive drive voltage supply varies the adjustable supply voltage responsive to the sensed load current to improve an efficiency of the dc to dc converter circuit over a wide range of load currents.

19. The dc to dc converter circuit of claim 16, wherein the adaptive drive voltage supply is further responsive to a switching frequency of the power transistors in the power stage.