Symmetric pilot processing for robust timing offset and frequency offset estimation in receivers

Abstract

timing and frequency offset processing in sub-carriers is performed in an Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) a receiver system. sub-carriers are divided into two sub-sets, where the sub-sets contain an equal number of sub-carriers. Subsequently bad sub-carriers are removed, if present, from first sub-set of the sub-sets, and corresponding sub-carriers from a second sub-set of the sub-sets are also removed. Further, a phase difference on each sub-carrier from each sub-set is computed, and mean phase differences of each of the sub-sets are computed. Furthermore, frequency offset is computed by averaging the mean phase differences of the sets.

Description

where T_u is the OFDM symbol time, Δf is the frequency offset, ξ=ΔT/T and is the timing offset in percentage, and k is the sub-carrier index, as described in Speth, M. et. al, “Optimum receiver design for wireless broad-band systems using OFDM—Part I,” IEEE Trans. on Communications, vol. 47, no. 11, pp. 1668-1677, November 1999, the complete disclosure of which, in its entirety, is herein incorporated by reference. As illustrated in FIG. 1, the mean of phase rotation is equal to ΔfT_u and the slope of the phase rotation curve is the timing offset ξ.

FIG. 2, with reference to FIG. 1, is a flow diagram of a method according to a first embodiment herein. Sub-carriers are divided (201) into two equal sets and the phase difference on each sub-carrier is computed (202). Further, the mean phase difference of each set is computed (203) by:

$\begin{array}{cc}\Delta {\Gamma }_L=\sum _{i=1}^M\Delta {\phi }_{L_i}/M& \left(2\right)\\ \Delta {\Gamma }_R=\sum _{i=1}^M\Delta {\phi }_{R_i}/M& \left(3\right)\end{array}$

Furthermore, the frequency offset is enumerated (204) by (ΔΓ_L+ΔΓ_R)/2. Lastly, the timing offset is computed (205) by (ΔΓ_L−ΔΓ_R)/N, wherein N is the mean distance of bin indices between the right sub-set and the left sub-set.

In a traditional way, if a bin is a bad bin and all other bins are good, then the bad bin could simply be removed from the computation of the mean phase difference in equations (2) and (3). In this context, a bin is “bad” when the received signal magnitude on that bin is too small. For example, if the signal magnitude is below half of the average signal magnitude, one may assume this to be a bad bin. This can cause some serious problems especially if the number of sub-carriers is very small. For example, consider a case where M=2, and S_L={−1, −2} and S_R={1, 2}. The phase differences caused by frequency and timing offset of two-adjacent symbols is described as:
Δφ₋₁≈T_uΔf−ξ  (4)
Δφ₋₂≈T_uΔf−2ξ  (5)
Δφ₁≈T_uΔf+ξ  (6)
Δφ₂≈T_uΔf+2ξ  (7)
The mean set differences are obtained as:
ΔΓ_L≈(Δφ₋₁+Δφ₋₂)/2=(2T_uΔf−3ξ)/2   (8)
ΔΓ_R≈(Δφ₁+Δφ₂)/2=(2T_uΔf+3ξ)/2   (9)
The frequency offset and timing offset is calculated as:
ΔΓ_L+ΔT_R=2T_uΔf   (10)
ΔΓ_R−ΔT_L≈3ξ  (11)

In case one of the bins is a bad bin, for example, bin −2 is a bad bin, the mean set phase differences are:
ΔΓ_L≈Δφ₋₁/2=(T_uΔf−ξ)/2   (12)
ΔΓ_R≈(Δφ₁+Δφ₂)/2=(2T_uΔf+3ξ)/2   (13)
The sum and difference of the set differences are:
ΔΓ_L+ΔT_R≈(3T_uΔf+2ξ)/2   (14)
ΔΓ_R−ΔT_L≈(T_uΔf+4ξ)/2   (15)
ΔΓ_L+ΔT_R is a function of both frequency offset and timing offset, and ΔΓ_R−ΔT_L is also a function of both of two offsets. If the frequency offset and timing offset are calculated, then very noisy estimates may be derived. Therefore, to alleviate this, in case there are bad sub-carriers, the embodiments herein perform symmetric processing for the bad pilots.

In the computation of the mean set difference, the embodiments herein not only remove the bad sub-carriers in one of the sub-set, but also remove their corresponding sub-carriers in the other sub-set. The corresponding bad sub-carriers are different for the estimation of the timing and frequency offsets, so for each sub-set, two mean differences are computed, one for the timing offset, and one for the frequency offset. Consider the above example, if it is assumed only bin −2 is a bad bin, then the mean set difference of the left sub-set is calculated as:
ΔΓ_L≈Δφ₋₁/2=(T_uΔf−ξ)/2   (16)

This mean difference can be used for both the frequency and timing offset estimations. For the right sub-set, two means are computed; one will be used for the timing offset estimation and the other will be used for the frequency offset. These are denoted as ΔΓ_Rf and ΔΓ_Rt, respectively. In the calculation of ΔΓ_Rf, the embodiments herein remove bin 2 even if bin 2 is a good bin and for ΔΓ_Rt, the embodiments herein remove bin 1 even if bin 1 is a good bin. In this context, a good sub-carrier occurs when a magnitude of a received signal in the sub-carrier is equal to or larger than a predetermined threshold level.
ΔΓ_Rf≈(Δφ₁)/2=(T_uΔf+ξ)/2   (17)
ΔΓ_Rt≈(Δφ₂)/2=(T_uΔf+2ξ)/2   (18)

For the left set, the mean differences for the timing and frequency offsets ΔΓ_Lt and ΔΓ_Lf would be same in this case and are equal to:
ΔΓ_Lt=ΔΓ_Lf=(T_uΔf−ξ)/2   (19)
The summation of the mean phase differences of the two sub-sets for frequency offset would be:
ΔΓ_Lf+ΔT_Rf≈T_uΔf   (20)
From the above equation (20), it can be seen that ΔΓ_Lf+ΔT_Rf is no longer a function of both frequency offset and timing offset. It is a linear function of the frequency offset. The difference of the mean phase differences of the two sub-sets for frequency offset would be:
ΔΓ_Rt−ΔT_Lt≈1.5ξ  (21)
From the above equation (21), it can be seen that ΔΓ_Rt−ΔT_Lt is no longer a function of both frequency offset and timing offset; rather it is a linear function of the timing offset.

In order to conduct the symmetric processing process to estimate the frequency and timing offsets, according to the embodiments herein, if one bin in one of the sub-sets is a bad bin, this bin is removed and also the corresponding bin in the other set in the calculation of the set phase differences is removed. Furthermore, for each set, two mean phase differences are computed: one for timing offset, and the other for frequency offset.

For frequency offset calculation, bins L_i and R_M−i+1 form a pair of correlated sets. In one of bins in the correlated set is bad, it is removed from the calculation of the set phase difference. Furthermore, the other bin in the set for calculation of the set phase difference is removed even though that bin is a good bin. For performing timing offset calculation, bins L_i and R_i form a pair of correlated sets. If one of bins in the correlated is bad, it is removed from the calculation of the set phase difference, and the other bin in the set for calculation of the set phase difference is also removed even though that bin is a good bin.

For example, if it is assumed bin L_n in the left bin sub-set S_L={L₁, L₂, L₃, . . . , L_M} is a bad bin. The left set phase differences for timing offset and frequency offsets would be:

$\begin{array}{cc}\Delta {\Gamma }_{\mathrm{Lf}}=\Delta {\Gamma }_{\mathrm{Lt}}=\left(\sum _{i=1,i\ne n}^M\Delta {\phi }_{L_i}\right)/M& \left(22\right)\end{array}$
To calculate the mean phase difference of the right sub-set for frequency offset, bin R_M−n+1 is removed; i.e.,

$\begin{array}{cc}\Delta {\Gamma }_{\mathrm{Rf}}=\left(\sum _{i=1,i\ne M-n+1}^M\Delta {\phi }_{L_i}\right)/M& \left(23\right)\end{array}$
To calculate the mean phase difference of the right sub-set for timing offset, bin R_n is removed; i.e.,

$\begin{array}{cc}\Delta {\Gamma }_{\mathrm{Rt}}=\left(\sum _{i=1,i\ne n}^M\Delta {\phi }_{L_i}\right)/M& \left(24\right)\end{array}$
The summation of ΔΓ_Lf and ΔT_Rf indicates the frequency offset and the difference between ΔΓ_Rt and ΔT_Lt indicates the timing offset.

FIG. 3 is a flow diagram according to a second embodiment herein, where division of sub-carriers into two equal sets (first and second) is performed (301). The presence of any bad sub-carrier is detected (302). If there are no bad sub-carriers detected, then the phase difference of each sub-carrier of each set is calculated (303). Further, the mean phase difference of each set is calculated (304). Thereafter, the frequency offset is computed (305) and the timing offset is computed (306). If a bad sub-carrier is detected, then the process of performing symmetric processing for bad sub-carriers is enacted. In symmetric processing for the bad sub-carriers, if any of the bad sub-carrier is detected, then that particular sub-carrier is removed (307) from the respective sub-set (first set). According to symmetric processing for the bad sub-carriers, the corresponding sub-carriers in other sub-set (second set) is also removed (308). After removal of the bad sub-carrier, the phase difference on each of the sub-carriers of each sub-set is computed (309). In the next step, the mean phase difference of the first set is calculated (310). Furthermore, the mean phase difference for the frequency offset is then calculated (311). Lastly the frequency offset is calculated (312).

FIG. 4 is a flow diagram of a third embodiment according to the embodiments herein, where division of sub-carriers into two equal sets (first and second) is performed (401). In the next step, the presence of any bad sub-carrier is detected (402). If there are no bad sub-carriers detected, then the phase difference on each sub-carrier of each set is computed (403). In the next step, the mean phase difference of each set is calculated (404). Moreover, the frequency offset is computed (405) and the timing offset is computed (406). If bad sub-carriers are detected, then the process of symmetric processing for bad sub-carriers is enacted. In symmetric processing, for the bad sub-carriers if any bad sub-carrier is detected, then that particular sub-carrier is removed (407) from the respective sub-set; i.e. the bad sub-carrier is removed from the first set. According to symmetric processing for bad sub-carriers, the corresponding sub-carriers in the other sub-set (second set) are removed (408). After removal of the corresponding bad sub-carrier, the phase difference on each of the sub-carrier of each the sub-set is computed (409). Next, the mean phase difference of the first set is calculated (410). Furthermore, the mean phase difference for the timing offset is calculated (411). Finally, the timing offset is calculated (412).

FIG. 5 is a block diagram illustrating an apparatus for performing timing and frequency offset estimation according to an embodiment herein. As shown, it is first determined whether a bin is good bin or bad bin. If the bin is bad bin, it is marked as a bad bin. This bad bin classification will be used subsequently when these bad bins are excluded in the accumulation processes. Since the bad bins will be used later, they are stored in storage devices. For example, in an integrated circuit chip, registers or memory may be used to store this information. Bad bins are marked as “bad bins” in register 501 for the left sub-set, and bad bins are marked as “bad bins” in register 502 for the right sub-set. OR logic 503-505 is embodied as a digital logic device adapted to perform a Boolean operation ‘OR’. The bad bins are processed in reverse order 506, 507 prior to being entered into the OR logic devices 504, 505. Thereafter, bad bins are marked as “bad bins” in registers 508-510 for, respectively, both the left and right sub-sets for the timing offset (register 508), the left sub-set for the frequency offset (register 509), and the right sub-set for the frequency offset (register 510).

From register 508, the phase difference for the “good bins” in the left sub-set are accumulated in accumulator 511 and then are scaled (515) by M (where M is the number of bins in the left-right sub-set). Also, from register 508, the phase difference for the “good bins” in the right sub-set are accumulated in accumulator 512 and then are scaled (516) by M. From register 509, the phase difference for the “good bins” in the left sub-set are accumulated in accumulator 513 and then are scaled (517) by M. From register 510, the phase difference for the “good bins” in the right sub-set are accumulated in accumulator 514 and then are scaled (518) by M. After scaling (516) by M, the offset is multiplied (519) by −1 and then is added (520) with the offset from the scaling process (515) to generate the overall timing offset estimation. The scaling 517-518 are combined (521) together to generate the overall frequency offset estimation.

The techniques provided by the embodiments herein may be implemented on an integrated circuit chip (not shown). The chip design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.

The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

The embodiments herein can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment including both hardware and software elements. The embodiments that are implemented in software include but are not limited to, firmware, resident software, microcode, etc.

Furthermore, the embodiments herein can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can comprise, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.

The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W) and DVD.

A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.

Input/output (I/O) devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters.

A representative hardware environment for practicing the embodiments herein is depicted in FIG. 6. This schematic drawing illustrates a hardware configuration of an information handling/computer system 600 in accordance with the embodiments herein. The system 600 comprises at least one processor or central processing unit (CPU) 610. The CPUs 610 are interconnected via system bus 612 to various devices such as a random access memory (RAM) 614, read-only memory (ROM) 616, and an input/output (I/O) adapter 618. The I/O adapter 618 can connect to peripheral devices, such as disk units 611 and tape drives 613, or other program storage devices that are readable by the system 600. The system 600 can read the inventive instructions on the program storage devices and follow these instructions to execute the methodology of the embodiments herein. The system 600 further includes a user interface adapter 619 that connects a keyboard 615, mouse 617, speaker 624, microphone 622, and/or other user interface devices such as a touch screen device (not shown) to the bus 612 to gather user input. Additionally, a communication adapter 620 connects the bus 612 to a data processing network 625, and a display adapter 621 connects the bus 612 to a display device 623 which may be embodied as an output device such as a monitor, printer, or transmitter, for example.

Generally, the embodiments provide a symmetric processing approach to estimate the time offset is to remove the bad sub-carrier and the corresponding sub-carrier in other set while calculating the set phase differences. For the timing offset calculation, sub-carriers L_i and R_i form a pair of correlated sets. If one of the sub-carriers in the sub-set is bad, the bad sub-carrier has to be removed from calculation of set phase difference. The other sub-carrier in the set is removed for calculation of the set phase difference even if that sub-carrier is a good sub-carrier.

The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.

Claims

1. A method of computing timing and frequency offset in sub-carriers in an Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) a receiver system, said method comprising:

storing said sub-carriers in a storage device;

using a processor for dividing said sub-carriers into two sub-sets, using a processor, wherein said the sub-sets comprise an equal number of sub-carriers;

removing bad sub-carriers from a first sub-set of said sub-sets;

removing sub-carriers from a second sub-set of said sub-sets that correspond to said bad sub-carriers from said first sub-set of said subsets sub-sets;

computing a phase difference on each sub-carrier from each sub-set responsive to the removing steps;

computing mean phase differences of each of said sub-sets responsive to the computing step; and

computing a timing offset and a frequency offset in said sub-carriers using the computed mean differences.

2. The method of claim 1, wherein said frequency offset in said sub-carriers is computed by summing said mean phase differences of said sub-sets.

3. The method of claim 1, wherein said timing offset in said sub-carriers is computed by calculating the a difference of said mean phase differences of said sub-sets.

4. The method of claim 1, wherein a bad sub-carrier occurs when a magnitude of a received signal in said sub-carrier is smaller than a predetermined threshold level.

5. The method of claim 1, wherein said sub-carriers from said second sub-set of said sub-sets that correspond to said bad sub-carriers from said first sub-set of said subsets sub-sets are bad sub-carriers.

6. The method of claim 1, wherein said sub-carriers from said second sub-set of said sub-sets that correspond to said bad sub-carriers from said first sub-set of said subsets sub-sets are good sub-carriers.

7. The method of claim 6, wherein a good sub-carrier occurs when a magnitude of a received signal in said sub-carrier is equal to or larger than a predetermined threshold level.

8. A non-transitory program storage device readable by computer, tangibly embodying a program of instructions executable by said computer to perform a method of computing timing and frequency offset in sub-carriers in an Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) a receiver system, said method comprising:

using a processor for dividing said sub-carriers into two sub-sets, using a processor, wherein said the sub-sets comprise an equal number of sub-carriers;

removing bad sub-carriers from a first sub-set of said sub-sets;

removing sub-carriers from a second sub-set of said sub-sets that correspond to said bad sub-carriers from said first sub-set of said subsets sub-sets;

computing a phase difference on each sub-carrier from each sub-set responsive to the removing steps;

computing mean phase differences of each of said sub-sets responsive to the computing step; and

computing a timing offset and a frequency offset in said sub-carriers using the computed mean differences.

9. The program storage device of claim 1, wherein said frequency offset in said sub-carriers is computed by summing said mean phase differences of said sub-sets.

10. The program storage device of claim 1, wherein said timing offset in said sub-carriers is computed by calculating the a difference of said mean phase differences of said sub-sets.

11. The program storage device of claim 1, wherein a bad sub-carrier occurs when a magnitude of a received signal in said sub-carrier is smaller than a predetermined threshold level.

12. The program storage device of claim 1, wherein said sub-carriers from said second sub-set of said sub-sets that correspond to said bad sub-carriers from said first sub-set of said subsets sub-sets are bad sub-carriers.

13. The program storage device of claim 1, wherein said sub-carriers from said second sub-set of said sub-sets that correspond to said bad sub-carriers from said first sub-set of said subsets sub-sets are good sub-carriers.

14. The program storage device of claim 13, wherein a good sub-carrier occurs when a magnitude of a received signal in said sub-carrier is equal to or larger than a predetermined threshold level.

15. An apparatus for computing timing and frequency offset in sub-carriers in an Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) a receiver system, said apparatus comprising:

a storage device for storing said sub-carriers;

a processor for dividing said sub-carriers into two sub-sets, wherein said the sub-sets comprise an equal number of sub-carriers;

digital logic means for removing bad sub-carriers from a first sub-set of said sub-sets;

digital logic means for removing sub-carriers from a second sub-set of said sub-sets that correspond to said bad sub-carriers from said first sub-set of said subsets sub-sets;

means for computing a phase difference on each sub-carrier from each sub-set;

means for computing mean phase differences of each of said sub-sets; and

means for computing a timing offset and a frequency offset in said sub-carriers using the computed mean differences.

16. The apparatus of claim 15, wherein said frequency offset in said sub-carriers is computed by summing said mean phase differences of said sub-sets.

17. The apparatus of claim 15, wherein said timing offset in said sub-carriers is computed by calculating the a difference of said mean phase differences of said sub-sets.

18. The apparatus of claim 15, wherein a bad sub-carrier occurs when a magnitude of a received signal in said sub-carrier is smaller than a predetermined threshold level.

19. The apparatus of claim 15, wherein said sub-carriers from said second sub-set of said sub-sets that correspond to said bad sub-carriers from said first sub-set of said subsets sub-sets are bad sub-carriers.

20. The apparatus of claim 15, wherein said sub-carriers from said second sub-set of said sub-sets that correspond to said bad sub-carriers from said first sub-set of said subsets sub-sets are good sub-carriers, wherein a good sub-carrier occurs when a magnitude of a received signal in said sub-carrier is equal to or larger than a predetermined threshold level.

21. The method of claim 1, wherein said receiver comprises a mobile television receiver.

22. The program storage device of claim 8, wherein said receiver comprises a mobile television receiver.

23. The apparatus of claim 15, wherein said receiver comprises a mobile television receiver.