A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.

Patent
   RE44761
Priority
Nov 10 2003
Filed
Feb 01 2013
Issued
Feb 11 2014
Expiry
Nov 10 2024
Assg.orig
Entity
Large
0
155
all paid
20. A method for forming flip chip interconnection, comprising:
providing a substrate having an interconnect site;
providing a semiconductor die having an interconnect pad;
depositing bump material between the interconnect pad and interconnect site; and
reflowing the bump material to form a composite bump between the interconnect pad and interconnect site, wherein a width of the composite bump across the interconnect site is less than a length of the composite bump along the interconnect site and the composite bump includes a non-collapsible portion and collapsible portion.
17. A method for forming flip chip interconnection, comprising:
providing a substrate having an interconnect site;
providing a semiconductor die having an interconnect pad;
depositing bump material between the interconnect pad and interconnect site; and
reflowing the bump material to form a bump between the interconnect pad and interconnect site, wherein a width of the bump across the interconnect site is less than a length of the bump along the interconnect site and the width of the bump across the interconnect pad is about 1.5 to 4 times the width of the bump across the interconnect site.
33. A method for forming flip chip interconnection, comprising: providing a substrate having an interconnect site; providing a semiconductor die having an interconnect pad; and forming a bump between the interconnect pad and interconnect site, wherein a contact area of the bump across the interconnect site in a first direction is less than a contact area of the bump along the interconnect site in a second direction perpendicular to the first direction, wherein the bump includes a composite bump between the interconnect pad and interconnect site, and wherein the composite bump includes a non-collapsible portion and collapsible portion.
27. A method for forming flip chip interconnection, comprising:
providing a substrate having an interconnect site;
forming a first insulating layer over the substrate with an opening over the interconnect site;
providing a semiconductor die having an interconnect pad;
forming a bump between the interconnect pad and interconnect site, wherein a contact area of the bump across the interconnect site in a first direction is less than a contact area of the bump along the interconnect site in a second direction perpendicular to the first direction and the contact area of the bump in the second direction contacts the first insulating layer while leaving a void along the contact area of the bump in the second direction between the first insulating layer and interconnect site.
12. A method for forming flip chip interconnection, comprising:
providing a substrate having an interconnect site;
forming a first insulating layer over the substrate with an opening over the interconnect site;
providing a semiconductor die having an interconnect pad;
depositing bump material between the interconnect pad and interconnect site; and
reflowing the bump material to form a bump between the interconnect pad and interconnect site, wherein a width of the bump across the interconnect pad is about 1.5 to 4 times the width of the bump across the interconnect site and the width of the bump across the interconnect site is less than a length of the bump along the interconnect site and the bump contacts the first insulating layer while leaving a void between the first insulating layer and interconnect site.
1. A method for forming flip chip interconnection, comprising:
providing a substrate having an interconnect site on a conductive trace formed on a die attach surface;
providing a semiconductor die having an interconnect pad formed on an active surface;
depositing fusible conductive material on the interconnect pad or on the interconnect site;
positioning the semiconductor die with the active side of the die oriented toward the die attach surface of the substrate, the fusible conductive material contacting the interconnect pad and interconnect site; and
melting and then re-solidifying the fusible conductive material to form a metallurgical interconnection between the interconnect pad and interconnect site, wherein a width of the metallurgical interconnect across the interconnect site is less than a length of the metallurgical interconnect along the interconnect site and a width of the metallurgical interconnect across the interconnect pad is about 1.5 to 4 times the width of the metallurgical interconnect across the interconnect site.
8. A method for forming flip chip interconnection, comprising:
providing a substrate having an interconnect site formed on a die attach surface;
forming a first insulating layer over the substrate with an opening over the interconnect site;
providing a semiconductor die having an interconnect pad formed on an active surface;
depositing bump material on the interconnect pad or on the interconnect site;
positioning the semiconductor die with the active side of the die oriented toward the die attach surface of the substrate, the bump material contacting the interconnect pad and interconnect site; and
reflowing the bump material to form a composite bump between the interconnect pad and interconnect site, the composite bump including a non-collapsible portion and collapsible portion, wherein a width of the composite bump across the interconnect site is less than a length of the composite bump along the interconnect site and the composite bump contacts the first insulating layer while leaving a void between the first insulating layer and interconnect site.
21. A method for forming flip chip interconnection, comprising:
providing a substrate having an interconnect site formed on a die attach surface;
forming a first insulating layer over the substrate with an opening over the interconnect site;
providing a semiconductor die having an interconnect pad formed on an active surface;
depositing bump material on the interconnect pad or on the interconnect site;
positioning the semiconductor die with the active side of the die oriented toward the die attach surface of the substrate, the bump material contacting the interconnect pad and interconnect site; and
reflowing the bump material to form a bump between the interconnect pad and interconnect site, wherein a contact area of the bump across the interconnect site in a first direction is less than a contact area of the bump along the interconnect site in a second direction perpendicular to the first direction and the contact area of the bump in the second direction contacts the first insulating layer while leaving a void along the contact area of the bump in the second direction between the first insulating layer and interconnect site.
2. The method of claim 1, further including forming a first insulating layer over the substrate with an opening over the interconnect site.
3. The method of claim 2, wherein the metallurgical interconnect contacts the first insulating layer while leaving a void between the first insulating layer and interconnect site.
4. The method of claim 1, further including forming a composite interconnect structure between the interconnect pad and interconnect site.
5. The method of claim 4, wherein the composite interconnect structure includes a non-collapsible portion and collapsible portion.
6. The method of claim 5, wherein the non-collapsible portion includes lead-tin alloy, copper, gold, or nickel.
7. The method of claim 5, wherein the collapsible portion includes eutectic solder.
9. The method of claim 8, wherein a width of the composite bump across the interconnect pad is about 1.5 to 4 times the width of the composite bump across the interconnect site.
10. The method of claim 8, wherein the non-collapsible portion includes lead-tin alloy, copper, gold, or nickel.
11. The method of claim 8, wherein the collapsible portion includes eutectic solder.
13. The method of claim 12, wherein the bump includes a composite bump between the interconnect pad and interconnect site.
14. The method of claim 13, wherein the composite bump includes a non-collapsible portion and collapsible portion.
15. The method of claim 14, wherein the non-collapsible portion includes lead-tin alloy, copper, gold, or nickel.
16. The method of claim 14, wherein the collapsible portion includes eutectic solder.
18. The method of claim 17, further including forming a first insulating layer over the substrate with an opening over the interconnect site.
19. The method of claim 18, wherein the bump contacts the first insulating layer while leaving a void between the first insulating layer and interconnect site.
22. The method of claim 21, wherein a width of the bump across the interconnect pad is about 1.5 to 4 times the width of the bump across the interconnect site.
23. The method of claim 21, wherein the bump includes a composite bump between the interconnect pad and interconnect site.
24. The method of claim 23, wherein the composite bump includes a non-collapsible portion and collapsible portion.
25. The method of claim 24, wherein the non-collapsible portion includes lead-tin alloy, copper, gold, or nickel.
26. The method of claim 24, wherein the collapsible portion includes eutectic solder.
28. The method of claim 27, wherein a width of the bump across the interconnect pad is about 1.5 to 4 times the width of the bump across the interconnect site.
29. The method of claim 27, wherein the bump includes a composite bump between the interconnect pad and interconnect site.
30. The method of claim 29, wherein the composite bump includes a non-collapsible portion and collapsible portion.
31. The method of claim 30, wherein the non-collapsible portion includes lead-tin alloy, copper, gold, or nickel.
32. The method of claim 30, wherein the collapsible portion includes eutectic solder.
34. The method of claim 33, further including forming a first insulating layer over the substrate with an opening over the interconnect site.
35. The method of claim 34, wherein the bump contacts the first insulating layer while leaving a void between the first insulating layer and interconnect site.
36. The method of claim 33, wherein a width of the bump across the interconnect pad is about 1.5 to 4 times the width of the bump across the interconnect site.

The present application is a reissue application of U.S. Pat. No. 8,216,930, which is a division of U.S. patent application Ser. No. 11/640,534, now U.S. Pat. No. 7,659,633, filed Dec. 14, 2006, and claims priority to the foregoing parent application pursuant to 35 U.S.C. §120 which claims the benefit of U.S. Provisional Application No. 60/597,648, filed Dec. 14, 2005, and further is a continuation-in-part of U.S. patent application Ser. No. 11/388,755, now abandoned, filed Mar. 24, 2006, which claims the benefit of U.S. Provisional Application No. 60/665,208, filed Mar. 25, 2005, and further is a continuation-in-part of U.S. patent application Ser. No. 10/985,654, now U.S. Pat. No. 7,368,817, filed Nov. 10, 2004, which claims the benefit of U.S. Provisional Application No. 60/518,864, filed Nov. 10, 2003 and U.S. Provisional Application No. 60/533,918, filed Dec. 31, 2003.

This invention relates to semiconductor packaging and, particularly, to flip chip interconnection.

Flip chip packages include a semiconductor die mounted onto a package substrate with the active side of the die facing the substrate. The substrate is made up of a dielectric layer and at least one metal layer, patterned to provide substrate circuitry, which includes among other features traces (“leads”) leading to interconnect pads. The metal layer may be patterned by, for example, a mask and etch process. Conventionally, interconnection of the circuitry in the die with circuitry in the substrate is made by way of bumps which are attached to an array of interconnect pads on the die, and bonded to a corresponding (complementary) array of interconnect pads (often referred to as “capture pads”) on the substrate. The capture pads are typically much wider than the leads, and can be as wide as, for example, about 2 to 4 times the nominal or design width of the leads. Conventionally, the interconnect area on the capture pad is approximately equal to the interconnect area on the die pad.

The areal density of electronic features on integrated circuits has increased enormously, and chips having a greater density of circuit features also may have a greater density of sites (“die pads”) for interconnection with the circuitry on a package substrate.

The package is connected to underlying circuitry, such as a printed circuit board (e.g., a “motherboard”), in the device in which the package is employed, by way of second level interconnects (e.g., pins, secondary interconnect solder balls) between the package and the underlying circuit. The second level interconnects have a greater pitch than the flip chip interconnects, and so the routing on the substrate conventionally “fans out”. Significant technological advances in patterning the metal layer on the substrate have enabled construction of fine lines and spaces; but in the conventional arrangement space between adjacent pads limits the number of traces than can escape from the more inward capture pads in the array, and the fan out routing between the capture pads beneath the die and the external pins of the package is conventionally formed on multiple metal layers within the package substrate. For a complex interconnect array, substrates having multiple layers may be required to achieve routing between the die pads and the second level interconnects on the package.

Multiple layer substrates are expensive, and in conventional flip chip constructs the substrate alone typically accounts for more than half the package cost (about 60% in some typical instances). The high cost of multilayer substrates has been a factor in limiting proliferation of flip chip technology in mainstream products.

In conventional flip chip constructs the escape routing pattern typically introduces additional electrical parasitics, because the routing includes short runs of unshielded wiring and vias between wiring layers in the signal transmission path. Electrical parasitics can significantly limit package performance.

Flip chip interconnection is commonly used in a wide variety of integrated circuit designs, including for example ASIC, GPU, Chipset, DSP, FPGA.

The aforementioned challenges presented by conventional flip chip interconnect can be addressed by connecting the interconnect bump directly onto a lead (“Bump-on-Lead” interconnect, or “BoL”); or by connecting the interconnect bump directly onto a narrow interconnection pad, or narrow pad (“Bump-on-Narrow Pad”, or “BoNP”) rather than onto a conventional capture pad. Such approaches are described in, for example, related U.S. application Ser. No. 10/985,654 (BoL) and U.S. application Ser. No. 11/388,755 (BoNP).

BoNP or BoL approaches can provide more efficient routing of traces on the substrate. Particularly, the signal routing can be formed entirely in a single metal layer of the substrate. This can reduce the number of layers in the substrate, and forming the signal traces in a single layer also permits relaxation of some of the via, line and space design rules that the substrate must meet. This simplification of the substrate greatly reduces the overall cost of the flip chip package. The bump-on-lead architecture also helps eliminate such features as vias and “stubs” from the substrate design, and enables a microstrip controlled impedance electrical environment for signal transmission, thereby greatly improving performance.

We have discovered that, within selected design parameters, a BoL or BoNP flip chip interconnection can be at least as reliable as a conventional bond on capture pad interconnect. Generally, within a range, interconnect structures formed on narrower leads—that is, more sharply tapered interconnect structures—can be more reliable than interconnect structures formed on less narrow leads.

Particularly, where the CTE of the die differs significantly from the CTE of the substrate, improved reliability can result from configuring the interconnect so that the interconnect structure is tapered, and the area of contact of the solder with the site on the lead is significantly less than the area of contact of the solder with the die pad. The contact at the site on the lead can be narrower as a result of a narrow dimension of the lead at the site (BoL) or of a narrow pad at the site (BoNP); or the contact at the site on the lead can be narrow as a consequence of masking a larger pad or otherwise limiting the solder-wettable area of a larger pad.

In some embodiments the CTE of the substrate is significantly greater than the CTE of the die; and the material of the interconnect structure is selected to be close to that of the substrate. For example, the CTE of a laminate (organic) substrate is typically in a range about 16-18 ppm/degree C.; the CTE of silicon is about 2-3 ppm/degree C.; the CTE of “glass ceramic” (in earlier use for substrates) is about 3-4 ppm/degree C.; the CTE of a co-fired ceramic (in use in multilayer substrates—as many as 16-18 layers, for example) is about 8-8.5 ppm/degree C. The CTE of a laminate (organic) substrate, on the other hand, is typically in a range about 16-18 ppm/degree C., and so a significant CTE mismatch exists between silicon die and organic laminate or build-up substrates. In some embodiments, the die is silicon-based, the substrate is an organic laminate or build-up substrate, and the tapered interconnect structure has a CTE in the range about 18-28 ppm/degree C.

In one general aspect the invention features a flip chip interconnection having tapered interconnect structures, in which a width of the connection of the interconnect structure with a die pad is greater than a width of the connection of the interconnect structure with a site on a lead. In some embodiments the connection at the die pad is about 1.5 times as wide as the connection at the lead, or is about 2 times as wide as the connection at the lead, or is about 3 times as wide as the connection at the lead, or is about 4 times as wide as the connection at the lead. The width of the connection at the die pad can be in a range about 50 um to about 150 um; die pads in common use have widths about 110 (or 120) urn and about 90 um. The width of the connection at the site at the lead can be in a range about 20 um to about 100 um; some standard leads have widths at the site about 50 um, or about 40 um, or about 30 um. Where the CTE mismatch between the die and the substrate is greater, a more sharply tapering interconnect structure may prove more reliable; where the CTE mismatch is less, a less sharply tapered interconnect structure may prove suitable.

In some embodiments the interconnect structure is a composite structure, including a higher-melting bump connected to the die pad, and a lower-melting solder connecting the bump to the site on the lead. The lower-melting component of the composite structure can be provided as a cap on the bump; or, the lower-melting component can be provided on the interconnect site (for example as a solder paste, or a plated spot); or a lower-melting material could be provided on each the bump and the site. The higher-melting bump can be of a material that is substantially non-collapsible at the reflow temperatures employed in making the interconnect. In such embodiments the higher-melting bump can be, for example, a high-lead solder (such as a lead-tin alloy having high lead content), or copper, or gold, or nickel, or a combination of these. The lower-melting solder can be, for example, a eutectic solder, which may be tin-based, including tin and alloys of tin such as silver, copper, or lead, or a combination of these. Or, the bump could be entirely of a material that melts at the reflow temperature.

The bump can be affixed to the die pad; or, it can be formed on the die pad in situ, by printing or plating the bump material at the die pads and then heating to form the bumps.

In another general aspect the invention features a flip chip package including a die having interconnect pads in an active surface, and a substrate having interconnect sites on electrically conductive traces in a die attach surface, in which tapered interconnect structures connect the die pads to the sites. In some embodiments the sites include locations in the leads (BoL); in some embodiments the sites include narrow pads in the leads (BoNP); in some embodiments the sites include small-area portions of capture pads.

The bump-on-lead interconnection is formed according to methods of the invention with use of a solder mask to confine the molten solder during a re-melt stage in the process. According to the invention the solder mask and openings in the solder mask are configured so that the solder mask contacts—or is very close to—the interconnect structure at the margin of the solder mask opening, so that it interferes with the flow of underfill material to the region adjacent the connection of the interconnect structure with the metallization on the substrate. As a result, voids remain following completion of the underfill process. According to the invention, these voids can provide some relief from thermal stress. The voids may contain whatever atmosphere was present during the underfill process.

Accordingly, in some embodiments the substrate is further provided with a solder mask having openings over the interconnect sites on the leads, and the solder mask contacts the interconnect structures at the margin of the solder mask openings; the assembly includes an underfill between the die and the substrate, but voids remain adjacent the interconnection with the sites on the substrate, defined in part by the locus of the contact of the solder mask with the interconnect structures.

Accordingly in one general aspect the invention features a flip chip interconnection having tapered interconnect structures, in which a width of the connection of the interconnect structure with a die pad is greater than a width of the connection of the interconnect structure with a site on a lead, and further including a solder mask having openings, in which the solder mask contacts the interconnect structure at the margin of the openings, and further comprising an underfill between the die and the substrate, wherein voids are present adjacent the sites on the substrate.

We have also found by computer modeling that thermally-induced maximum stress in BoL interconnections is less on leads that are oriented at the interconnect site toward a thermally neutral point on the die (that is, in a “radial” direction) than on leads that are oriented at the interconnect site perpendicularly to a radial direction.

In another general aspect the invention features a substrate for BoL or BoNP flip chip interconnection, in which the lengthwise dimension of the interconnect site (the mating portion of the lead or narrow pad) is oriented in a direction approximately aligned toward the thermally neutral point of the die, or deviating less than about 45° (more usually, less than about 20°; still more usually, less than about 10°) from such an alignment.

In another general aspect the invention features a method for forming flip chip interconnection, by providing a substrate having interconnect sites in conductive traces formed in a die attach surface, providing a die having bumps attached to interconnect pads in an active surface; providing a fusible conductive material on the bumps or on the interconnect sites (or on each the bumps and the interconnect sites); supporting the substrate and the die; positioning the die with the active side of the die toward the die attach surface of the substrate, and aligning the die and substrate and moving one toward the other so that the bumps contact the corresponding sites; and melting and then re-solidifying the fusible material, forming a metallurgical interconnection between the bump and the trace. In some embodiments the method further includes forming an underfill between the die and the substrate.

In another general aspect the invention features a method for forming flip chip interconnection, by providing a substrate having traces formed in a die attach surface and having a solder mask having openings over interconnect sites on the leads, and a die having bumps attached to interconnect pads in an active surface; supporting the substrate and the die; positioning the die with the active side of the die toward the die attach surface of the substrate, and aligning the die and substrate and moving one toward the other so that the bumps contact the corresponding traces (leads) on the substrate; melting and then re-solidifying to form the interconnection between the bump and the interconnect site on the trace.

In some embodiments the solder bump includes a collapsible solder portion, and the melt and solidifying step melts the bump to form the interconnection on the interconnect site. In some embodiments the substrate is further provided with a solder paste on the interconnect site, and the step of moving the die and the substrate toward one another effects a contact between the bump and the solder on the site, and the melt and solidifying step melts the solder on the site to form the interconnection.

In another general aspect the invention features a method for forming flip chip interconnection, by providing a substrate having traces formed in a die attach surface and having a solder mask having openings over interconnect sites on the leads and having solder paste on the leads at the interconnect sites, and a die having bumps attached to interconnect pads in an active surface; supporting the substrate and the die; positioning the die with the active side of the die toward the die attach surface of the substrate, and aligning the die and substrate and moving one toward the other so that the bumps contact the solder paste on the corresponding traces (leads) on the substrate; and melting and then re-solidifying the solder paste, forming a metallurgical interconnection between the bump and the trace.

In another general aspect the invention features a flip chip package, including interconnections formed as described above, and additionally including forming an underfill between the die and the substrate.

FIG. 1A is a diagrammatic sketch of a portion of a conventional bump-on-capture pad (“BoC”) flip chip interconnection, in a sectional view parallel to the plane of the package substrate surface.

FIG. 1B is a diagrammatic sketch in a plan view showing a die mounted on a substrate in a flip chip manner, in which the die and the substrate have significantly different thermal expansion coefficients, and showing dimensional change of the die in relation to the substrate as a result of change in temperature.

FIG. 2A is a diagrammatic sketch showing a portion of a flip chip interconnection according to the invention, in a sectional view perpendicular to the plane of the package substrate surface and generally transverse to the long axes of the leads.

FIG. 2B is a diagrammatic sketch showing a portion of a flip chip interconnection according to the invention, in a sectional view perpendicular to the plane of the package substrate surface and generally parallel long axes of the lead.

FIGS. 3A and 3B are diagrammatic sketches as in FIGS. 2B and 2B, respectively indicating dimensional references for various of the features.

The invention will now be described in further detail by reference to the drawings, which illustrate alternative embodiments of the invention. The drawings are diagrammatic, showing features of the invention and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the FIGS. illustrating embodiments of the invention, elements corresponding to elements shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the FIGS.

The conventional flip chip interconnection is made by using a melting process to join the bumps (conventionally, solder bumps) onto the mating surfaces of the corresponding capture pads and, accordingly, this is known as a “bump-on-capture pad” (“BoC”) interconnect. Two features are evident in the BOC design: first, a comparatively large capture pad is required to mate with the bump on the die; second, an insulating material, typically known as a “solder mask” is required to confine the flow of solder during the interconnection process. The solder mask opening may define the contour of the melted solder at the capture pad (“solder mask defined”), or the solder contour may not be defined by the mask opening (“non-solder mask defined”).

The techniques for defining solder mask openings have wide tolerance ranges. Consequently, for a solder mask defined bump configuration, the capture pad must be large (typically considerably larger than the design size for the mask opening), to ensure that the mask opening will be located on the mating surface of the pad; and for a non-solder mask defined bump configuration, the solder mask opening must be larger than the capture pad. The width of capture pads (or diameter, for circular pads) is typically about the same as the ball (or bump) diameter, and can be as much as two to four times wider than the trace width. This results in considerable loss of routing space on the top substrate layer. In particular, for example, the “escape routing pitch” is much bigger than the finest trace pitch that the substrate technology can offer. This means that a significant number of pads must be routed on lower substrate layers by means of short stubs and vias, often beneath the footprint of the die, emanating from the pads in question.

FIG. 1A shows a portion of a conventional flip chip package, in diagrammatic sectional view; the partial sectional view in FIG. 1A is taken in a plane perpendicular to the package substrate surface. Referring now to FIG. 1A, a die attach surface of the package substrate includes a patterned electrically conductive layer formed on a dielectric layer 10. The metal layer is patterned to form leads and capture pads 16. An insulating layer 11, typically termed a “solder mask”, covers the die attach surface of the substrate; the solder mask is usually constructed of a photodefinable material, and is patterned by conventional photoresist patterning techniques to have openings, indicated at 12, leaving the mating surfaces of the capture pads 16 exposed. Interconnect bumps 17 attached to pads (so-called “under bump metallization”) 18 on the active side of the die 14 are joined to the mating surfaces of corresponding capture pads 16 on the substrate to form appropriate electrical interconnection between the circuitry on the die and the leads on the substrate. The active side of the die 14 is covered, except at the contact surfaces of the die pads 16, with a die passivation layer 15, which may be, for example, a polyimide layer. After the reflowed solder is cooled to establish the electrical connection, an underfill material (not shown in these FIGS.) is introduced into the space between the die and the substrate, mechanically stabilizing the interconnects and protecting the features between the die and the substrate.

In such a conventional flip chip interconnect arrangement, signal escape traces in the upper metal layer of the substrate lead from their respective capture pads across the die edge location, and away from the die footprint. The capture pads are typically three times greater than the trace width. In one example of a conventional arrangement, the capture pads are arranged in a 210 um two-row area array pitch in a solder mask defined configuration, with one signal trace between capture pads in the marginal row, resulting in an effective escape pitch about 105 um, for example. In one example of a BoL interconnect, the interconnect sites can be arranged in a 210 um three-row area array pitch, with two signal traces between sites in the outer row, resulting in an effective escape pitch about 70 um. This escape pitch is adequate to route a significant proportion of integrated circuit designs that commonly employ flip chip interconnection on a single metallization layer, based on the inherent I/O density of the IC device architectures. BoL interconnection also further opens the prospect of routing a considerable proportion of flip chip designs in conventional through-hole laminate substrates, inasmuch as laminate substrates have line/space capacities of about 40 um/40 um (or better). This could provide for substantial cost reduction.

FIG. 1A shows a solder mask defined solder contour. As the fusible material of the bumps on the die melts, the molten solder tends to “wet” the metal of the capture pads, and the solder tends to “run out” over any contiguous metal surfaces that are not masked. The solder tends to flow along the underlying pad (and exposed contiguous lead), and in the solder mask defined contour the solder flow is limited by the solder mask, for example by the width of the opening 12 in the solder mask 11.

A non-solder mask defined solder contour may alternatively be employed, in which the flow of solder along the lead is limited at least in port by a patterned deposition of non-solder-wettable material on the lead surface.

Thermal movement (in the x-y plane) of die pads on the die attach surface of the die in relation to the corresponding points on the substrate (as indicated for example by arrow 13 in FIG. 1A), can result in stresses to the interconnections between the die pad and the site on the substrate. Dimensional change, resulting from temperature changes, of a flip chip mounted die in relation to a substrate, is shown diagrammatically (and with dimensions exaggerated) in plan view in FIG. 1B. In this example, there is a significant mismatch between the CTE of the die and the CE of the substrate. A portion of the substrate is shown at 11. Dimensional change of the die in the x-y plane (parallel to the plane of the substrate) in relation to the substrate as the temperature changes (for example, during thermal cycling in assembly or test or die burnout routines) is shown by the arrows 113. A footprint of the die at a higher temperature (the substrate is more “thermally expanded” than the die) is shown at 14B; a footprint of the die at a lower temperature is shown at 14B. As will be appreciated, registration of any point on the active surface of the die 14 with respect to a corresponding underlying point on the die attach surface of the substrate 11 will change as the dimensions of the die and substrate change differentially as a result of thermal stress. At some point on the active surface of the die there is no net movement with relation to the corresponding point on the underlying substrate, as a result of expansion or contraction of the die in relation to the substrate; that point may be referred to herein as the “thermally neutral point”. Generally, as may be appreciated, the thermally neutral point may approximately coincide with the geometric center of the die surface. The extent of movement of any point on the die in an x-y plane (parallel to the plane of the substrate) in relation to the substrate as a result of thermal expansion or contraction (the “thermal movement”) depends at least in part upon the distance of that point from the thermally neutral point on the die; accordingly, there is greater relative thermal movement at points nearer the edges of the die (and, particularly, near the corners of the die) than at points nearer the thermally neutral point.

Movement (in the x-y plane) of a die pad in relation to an underlying contact pad can result in stresses to the interconnection between the pad and the contact pad. Where the movement passes a limit, something has to give: failure of the interconnect can result. In conventional flip chip interconnects, where there is a thermal mismatch between the die and the substrate, failure typically occurs at the joint between the solder bump and the die pad. And, in convention flip chip interconnects, where there is a thermal mismatch between the die and the substrate, even if there is no failure, thermal stress at the die pad can cause damage to the die.

Conventionally it is thought that, in an ideal solder joint structure, the area (diameter) of the interconnect pad on the substrate is approximately equal to the area (diameter) of the interconnect pad on the die, as shown by way of example in FIG. 1A.

By analysis of interconnect configurations using computer simulations, we have determined that the primary locus of stress is as referenced at 19 in FIG. 1A. Particularly, where the thermal movement of the die in relation to the substrate is as shown at arrow 13 in FIG. 1A, the greatest (“Maximum”) plastic strain on the interconnect is predicted by the computer model to be at the “leading edge” 19 of the connection (interface) between the solder 17 and the die pad (UBM) 18. (As will be appreciated, the arrow might be positioned at the substrate, but reversed, showing relative movement of the substrate in the opposite direction; the relative movement is pointed out here in relation to the die, because the thermally neutral point is established in relation to the die footprint. The appearance of actual failures during accelerated fatigue testing is consistent with the model, that is, failure in conventional bond-on-capture pad interconnects usually appears at the interface of the solder with the die pad, rather than at the interface of the solder with the capture pad on the substrate.

A BoL interconnection according to an embodiment of the invention is shown by way of example in sectional views perpendicular to the surface of the substrate in FIGS. 2A and 2B. In FIG. 2A, two solder joints are shown in a sectional view transverse to the lead, and in FIG. 2B, one solder joint is shown in a sectional view parallel to the lead. Referring to FIG. 2A, a die attach surface of the package substrate includes a patterned electrically conductive layer formed on a dielectric layer 20. The metal layer is patterned to form leads having interconnect sites 26. An insulating layer 21, typically termed a “solder mask”, covers the die attach surface of the substrate; the solder mask is usually constructed of a photodefinable material, and is patterned by conventional photoresist patterning techniques to have openings, indicated at 22, leaving the top surface and the sides of the lead (the “mating surfaces”) exposed at the interconnect site 26. Interconnect structures 27 are attached to pads (so-called “under bump metallization”) 28 on the active side of the die 24 and are joined to the mating surfaces of the leads at the interconnect sites 26 on the substrate to form appropriate electrical interconnection between the circuitry on the die and the leads on the substrate. The active side of the die 24 is covered, except at the contact surfaces of the die pads 26, with a die passivation layer (such as a polyimide layer) 25. After the reflowed solder is cooled to establish the electrical connection, an underfill material (not shown in these FIGS.) is introduced into the space between the die and the substrate, mechanically stabilizing the interconnects and protecting the features between the die and the substrate.

Referring now to FIG. 2B, an interconnect is shown in a sectional view taken along the line 2B-2B in FIG. 2A. (In this view, the solder mask 21 is not shown.) This view shows the solder of interconnect structure 27 covering the sides of the lead 26.

The interconnect structures according to some embodiments can be made using entirely fusible materials, or using composite bumps, or using a solder-on-lead method, as described above.

Particularly, for example, so-called composite interconnect structures may be used. Composite structures have at least two bump portions, made of different materials, including one which is collapsible under reflow conditions, and one which is substantially non-collapsible under reflow conditions. The non-collapsible portion is attached to the interconnect pad on the die; typical conventional materials for the non-collapsible portion include various solders having a high lead (Pd) content, for example, (such as a lead-tin alloy having high lead content), or copper, or gold, or nickel, or a combination of these. The collapsible portion is joined to the non-collapsible portion, and it is the collapsible portion that makes the connection with the interconnect site on the lead. Typical conventional materials for the collapsible portion of the composite bump include eutectic solders, for example, which may be tin-based, including tin and alloys of tin such as silver, copper, or lead, or a combination of these.

This structure can be formed in the following way, for example. Solder bumps (or balls) are attached to or formed on the die pads (under bump metallization or UBM). Solder is applied to the interconnect sites on the traces, for example in the form of a solder paste. The die is oriented, active side facing the mounting surface of the substrate, so that the bumps on the die are aligned with the respective interconnect sites on the leads, and the die is moved toward the substrate to bring the bumps into contact with the solder on the leads. The assembly is then heated, to reflow the solder and form the connection at the interconnect site. As the solder on the lead reflows, it wicks to the solder-wettable surface of the solder bump, and to the solder-wettable mating surfaces of the lead. The surface of the substrate dielectric 20 is not solder-wettable, and the solder tends to make little or no contact with the substrate dielectric. The tapered form of the connection structure (as viewed in section across the lead, as in FIG. 2A) results from the narrow dimension of the lead at the interconnect site, and the wicking of the solder during reflow.

For example, the bumps may be formed of a high-lead (high-Pb) solder (e.g., 97% lead, 2% tin), and the solder on the interconnect site can be a eutectic solder. Reflow in some such examples can be carried out at a peak temperature of 235° C., employing flux in a jet flux method.

In a BoL construct such as is shown here, although the width of the leads may vary over their length, no particular widening of the leads is formed at the interconnect sites; in a BoNP construct, the leads may be widened to a limited extent at the interconnect sites. In either BoL or BONP construct, the sides of the lead—as well as the top—(the mating surfaces) are exposed to the solder at the interconnect site, and during reflow solder wicks to the solder-wettable surfaces.

As noted with reference to FIG. 2B, a solder mask is employed in these embodiments to limit the flow of solder along the length of the leads. In other embodiments the leads may be treated to be non-solder-wettable along portions of the leads adjacent the mating surfaces at the interconnect sites, so that flow of solder away from the interconnect sites along the leads is limited without use of a solder mask.

Any of a variety of substrate types can be employed according to the invention, including for example build-up film substrates and laminate substrates. For example, a 1-2-1 high-density build-up substrate can be used (such as an Ajinomoto Build-Up Film, or other high density substrate build-up film), or a 4-layer laminate substrate can be used.

Testing of samples constructed generally as shown in FIGS. 2A and 2B and employing a high-lead solder ball and a eutectic solder on the interconnect site shows that eventual failure can occur at or near the lead, rather than at the die pad, as in the conventional interconnect. Moreover, in embodiments according to the invention, where the difference between the areas of contact at the die pad and at the lead is sufficiently great, a greater number of thermal cycles to failure can be obtained.

FIGS. 3A and 3B are similar to FIGS. 2A and 2B, marked up for reference to dimensions of certain of the features. The features are referenced as follows: H, interconnect height as measured from the die surface to the solder mask surface; D, bump diameter at half the interconnect height (H/2); UD, under bump metallization diameter; OPx, mask opening width in the x-direction (across the lead); OPy, mask opening width in the y-direction (along the lead); CW, width of the (Copper) lead at the interconnect site; CH, thickness (height) of the lead at the interconnect site; T, solder mask thickness.

With further reference to FIG. 2A, a flip chip package according to the invention includes an underfill 47, which contributes to the mechanical stability of the structure and serves to protect the interconnection and the die and substrate surfaces. As inspection of FIG. 2A shows, the solder mask makes contact with (or is in close proximity to) the interconnect structure 27 at the margin of the opening 22. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site. This results in the creation of voids 48 left unfilled by the underfill material, adjacent the contact of the interconnect structure with the site on the substrate metallization. Conventionally, it is generally believed that any voids in a flip chip construct are undesirable, for a variety of reasons. However, we have discovered that these voids adjacent the interconnect cite on the substrate can help provide relief from strain induced by changes in temperature of the system; and the generally perceived complications imposed by voids can be mitigated.

A BoL construct according to the invention may have the following dimensions, for example: UD, 90 um; D, 110 um; H, 75 um; T, 40 um; CW, 30 um, CT, 20 um. A BoL construct having these dimensions formed on an Ajinomoto Build-Up Film (ABF) 1-2-1 substrate has performed well in fatigue failure tests. This result is surprising, because it is conventionally believed that preferred interconnects should have a shape and support area for the joint at the die side approximately equal to that on the substrate side (bond-on-capture pad, or BoC). (A similar BoL construct, having a wider CW (40 um) and formed on a 4-layer BT laminate, performed less satisfactorily.) Without intending to be bound thereto, the applicants suggest that the following hypothesis might explain this surprising result. Although in the conventional BoC the average strain on the interconnect system is determined by the magnitude of the CTE mismatch between the die and the substrate, a high strain concentration occurs at the bump/die interface, because at this location there is an abrupt difference in CTE. Accordingly, applicants suggest that fatigue failure is driven by a concentration of plastic strain at this location, and not by the average strain. In the BoL construct, because the interconnect structure is tapered, the portion of it nearer the substrate has a greater compliancy; particularly, applicants suggest that there is a high compliancy region (or “relief structure”) at or near the narrow interface at the interconnect site on the trace. Applicants suggest that this relief structure has an effect of diffusing the strain away from the die pad, resulting in improved fatigue life of the system. A computer analysis (Finite Element Modeling, FET) can lend support to this view.

A conventional (BoC) construct having the following dimensions was used for the FET analysis: UD, 90 um; D, 110 um; H, 75 um; OPx, 95 um; T, 40 um; CW, 115 um, CT, 20 um. The analysis showed a considerable concentration of maximum strain at the interface with the die pad in the BoC model, and a maximum plastic strain in a zone on the “leading edge” of the structure at the die pad (see, FIG. 1A). In the BoL model, the maximum plastic strain is reduced, and it is shifted away from the die pad interface.

Other embodiments are within the following claims.

Pendse, Rajendra D., Kim, KyungOe, Kang, TaeWoo

Patent Priority Assignee Title
Patent Priority Assignee Title
5186383, Oct 02 1991 Freescale Semiconductor, Inc Method for forming solder bump interconnections to a solder-plated circuit trace
5378859, Mar 02 1992 Casio Computer Co., Ltd. Film wiring board
5386624, Jul 06 1993 NXP, B V F K A FREESCALE SEMICONDUCTOR, INC Method for underencapsulating components on circuit supporting substrates
5434410, May 29 1992 L-3 Communications Corporation Fine-grain pyroelectric detector material and method
5508561, Nov 15 1993 NEC Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
5519580, Sep 09 1994 Intel Corporation Method of controlling solder ball size of BGA IC components
5587337, May 28 1993 Kabushiki Kaisha Toshiba Semiconductor process for forming bump electrodes with tapered sidewalls
5650595, May 25 1995 International Business Machines Corporation Electronic module with multiple solder dams in soldermask window
5710071, Dec 04 1995 SHENZHEN XINGUODU TECHNOLOGY CO , LTD Process for underfilling a flip-chip semiconductor device
5795818, Dec 06 1996 AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD Integrated circuit chip to substrate interconnection and method
5844782, Mar 29 1996 Sony Corporation Printed wiring board and electronic device using same
5854514, Aug 05 1996 INTERNATIONAL BUISNESS MACHINES CORPORATION; IBM Corporation Lead-free interconnection for electronic devices
5869886, Mar 22 1996 NEC Corporation Flip chip semiconductor mounting structure with electrically conductive resin
5872399, Apr 01 1996 AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD Solder ball land metal structure of ball grid semiconductor package
5889326, Feb 27 1996 Godo Kaisha IP Bridge 1 Structure for bonding semiconductor device to substrate
5915169, Dec 22 1995 AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD Semiconductor chip scale package and method of producing such
5985456, Jul 21 1997 CREATIVE ELECTRON, INC Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits
6002172, Mar 12 1997 International Business Machines Corporation Substrate structure and method for improving attachment reliability of semiconductor chips and modules
6109507, Nov 11 1997 Fujitsu Limited Method of forming solder bumps and method of forming preformed solder bumps
6201305, Jun 09 2000 AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD Making solder ball mounting pads on substrates
6218630, Jun 30 1997 FUJIFILM Corporation Printed circuit board having arrays of lands arranged inside and outside of each other having a reduced terminal-pitch
6228466, Apr 11 1997 Ibiden Co. Ltd. Printed wiring board and method for manufacturing the same
6229209, Feb 16 1996 Matsushita Electric Industrial Co., Ltd. Chip carrier
6229220, Jun 27 1995 International Business Machines Corporation Bump structure, bump forming method and package connecting body
6259163, Dec 25 1997 LAPIS SEMICONDUCTOR CO , LTD Bond pad for stress releif between a substrate and an external substrate
6281450, Jun 26 1997 Hitachi Chemical Company, Ltd. Substrate for mounting semiconductor chips
6281581, Mar 12 1997 Invensas Corporation Substrate structure for improving attachment reliability of semiconductor chips and modules
6297560, Oct 31 1996 Invensas Corporation Semiconductor flip-chip assembly with pre-applied encapsulating layers
6324754, Mar 25 1998 Tessera, Inc Method for fabricating microelectronic assemblies
6329605, Mar 26 1998 TESSERA, INC , A CORPORATION OF DELAWARE Components with conductive solder mask layers
6333206, Dec 24 1996 Nitto Denko Corporation Process for the production of semiconductor device
6335568, Oct 28 1998 Seiko Epson Corporation Semiconductor device and method of fabrication thereof, circuit board, and electronic equipment
6335571, Jul 21 1997 Invensas Corporation Semiconductor flip-chip package and method for the fabrication thereof
6383916, Dec 21 1998 Qualcomm Incorporated Top layers of metal for high performance IC's
6396707, Dec 03 1999 Siliconware Precision Industries Co., Ltd. Ball grid array package
6409073, Jul 15 1998 Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V. Method for transfering solder to a device and/or testing the device
6441316, Aug 27 1999 Mitsubishi Denki Kabushiki Kaisha Printed-circuit board and a semiconductor module, and a manufacturing process of the semiconductor module
6448665, Oct 15 1997 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
6458622, Jul 06 1999 SHENZHEN XINGUODU TECHNOLOGY CO , LTD Stress compensation composition and semiconductor component formed using the stress compensation composition
6462425, Apr 19 1999 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
6472608, Feb 18 2000 NEC Electronics Corporation Semiconductor device
6518674, Sep 23 1999 Invensas Corporation Temporary attach article and method for temporary attach of devices to a substrate
6573610, Jun 02 2000 Siliconware Precision Industries Co., Ltd. Substrate of semiconductor package for flip chip package
6600234, Feb 03 1999 AOI ELECTRONICS CO , LTD Mounting structure having columnar electrodes and a sealing film
6608388, Nov 01 2001 Siliconware Precision Industries Co., Ltd. Delamination-preventing substrate and semiconductor package with the same
6660560, Sep 10 2001 DELPHI TECHNOLOGIES IP LIMITED No-flow underfill material and underfill method for flip chip devices
6664483, May 15 2001 Intel Corporation Electronic package with high density interconnect and associated methods
6678948, Sep 01 1998 Robert Bosch GmbH Method for connecting electronic components to a substrate, and a method for checking such a connection
6710458, Oct 13 2000 SHENZHEN TOREY MICROELECTRONIC TECHNOLOGY CO LTD Tape for chip on film and semiconductor therewith
6734557, Mar 12 2002 Sharp Kabushiki Kaisha Semiconductor device
6768190, Jan 25 2002 Advanced Semiconductor Engineering, Inc. Stack type flip-chip package
6774497, Mar 28 2003 SHENZHEN XINGUODU TECHNOLOGY CO , LTD Flip-chip assembly with thin underfill and thick solder mask
6780673, Jun 12 2002 Texas Instruments Incorporated Method of forming a semiconductor device package using a plate layer surrounding contact pads
6780682, Feb 27 2001 STATS CHIPPAC, INC Process for precise encapsulation of flip chip interconnects
6787918, Jun 02 2000 Siliconware Precision Industries Co., Ltd. Substrate structure of flip chip package
6809262, Jun 03 2003 VIA Technologies, Inc. Flip chip package carrier
6818545, Mar 05 2001 Qualcomm Incorporated Low fabrication cost, fine pitch and high reliability solder bump
6821878, Feb 27 2003 SHENZHEN XINGUODU TECHNOLOGY CO , LTD Area-array device assembly with pre-applied underfill layers on printed wiring board
6849944, May 30 2003 Texas Instruments Incorporated Using a supporting structure to control collapse of a die towards a die pad during a reflow process for coupling the die to the die pad
6870276, Dec 26 2001 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Apparatus for supporting microelectronic substrates
6888255, May 30 2003 Texas Instruments Incorporated Built-up bump pad structure and method for same
6913948, Nov 10 1999 International Business Machines Corporation Partially captured oriented interconnections for BGA packages and a method of forming the interconnections
7005585, Sep 02 2002 Murata Manufacturing Co., Ltd. Mounting board and electronic device using same
7005743, Apr 28 2000 Sony Corporation Semiconductor device using bumps, method for fabricating same, and method for forming bumps
7005750, Aug 01 2003 ASE SHANGHAI INC Substrate with reinforced contact pad structure
7049705, Jul 15 2003 Advanced Semiconductor Engineering, Inc. Chip structure
7057284, Aug 12 2004 Texas Instruments Incorporated Fine pitch low-cost flip chip substrate
7064435, Jul 29 2003 Samsung Electronics Co., Ltd. Semiconductor package with improved ball land structure
7098407, Aug 23 2003 Samsung Electronics Co., Ltd. Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate
7102222, Oct 02 2003 Siliconware Precision Industries Co., Ltd. Conductive trace structure and semiconductor package having the conductive trace structure
7102239, Aug 18 2003 Siliconware Precision Industries Co., Ltd. Chip carrier for semiconductor chip
7112524, Sep 29 2003 Phoenix Precision Technology Corporation Substrate for pre-soldering material and fabrication method thereof
7164208, Jan 20 2004 Mosaid Technologies Incorporated Semiconductor device and method for manufacturing the same
7173828, Jul 28 2003 Siliconware Precision Industries Co., Ltd. Ground pad structure for preventing solder extrusion and semiconductor package having the ground pad structure
7224073, May 18 2004 UTAC HEADQUARTERS PTE LTD Substrate for solder joint
7242099, Oct 25 2002 Qualcomm Incorporated Chip package with multiple chips connected by bumps
7271484, Sep 25 2003 Polaris Innovations Limited Substrate for producing a soldering connection
7294451, Nov 18 2003 Texas Instruments Incorporated Raised solder-mask-defined (SMD) solder ball pads for a laminate electronic circuit board
7294929, Dec 30 2003 Texas Instruments Incorporated Solder ball pad structure
7317245, Apr 07 2006 AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD Method for manufacturing a semiconductor device substrate
7405484, Sep 30 2003 Sanyo Electric Co., Ltd. Semiconductor device containing stacked semiconductor chips and manufacturing method thereof
7436063, Oct 04 2004 ROHM CO , LTD Packaging substrate and semiconductor device
7521284, Mar 05 2007 Texas Instruments Incorporated System and method for increased stand-off height in stud bumping process
7642660, Dec 17 2002 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Method and apparatus for reducing electrical interconnection fatigue
7663250, Jun 17 2008 Samsung Electro-Mechanics Co., Ltd. Wafer level package and manufacturing method thereof
7670939, May 12 2008 ATI Technologies ULC Semiconductor chip bump connection apparatus and method
7671454, May 12 2006 SHENZHEN TOREY MICROELECTRONIC TECHNOLOGY CO LTD Tape carrier, semiconductor apparatus, and semiconductor module apparatus
7692314, Sep 07 2006 Samsung Electronics Co., Ltd. Wafer level chip scale package and method for manufacturing the same
7700407, Nov 10 2003 STATS CHIPPAC PTE LTE Method of forming a bump-on-lead flip chip interconnection having higher escape routing density
7732913, Feb 03 2006 Siliconware Precision Industries Co., Ltd. Semiconductor package substrate
7750457, Mar 30 2004 SHENZHEN TOREY MICROELECTRONIC TECHNOLOGY CO LTD Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus
7790509, Jun 27 2008 Texas Instruments Incorporated Method for fine-pitch, low stress flip-chip interconnect
7791211, Oct 19 2007 Advanced Semiconductor Engineering, Inc. Flip chip package structure and carrier thereof
7847399, Dec 07 2007 Texas Instruments Incorporated Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles
7847417, Dec 22 2005 Shinko Electric Industries Co., Ltd. Flip-chip mounting substrate and flip-chip mounting method
7851928, Jun 10 2008 Texas Instruments Incorporated Semiconductor device having substrate with differentially plated copper and selective solder
7898083, Dec 17 2008 Texas Instruments Incorporated Method for low stress flip-chip assembly of fine-pitch semiconductor devices
7902660, May 24 2006 AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD Substrate for semiconductor device and manufacturing method thereof
7902678, Mar 29 2004 Godo Kaisha IP Bridge 1 Semiconductor device and manufacturing method thereof
7902679, Mar 05 2001 Qualcomm Incorporated Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
7932170, Jun 23 2008 AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD Flip chip bump structure and fabrication method
7947602, Feb 21 2007 Texas Instruments Incorporated Conductive pattern formation method
7973406, Apr 03 2008 STATS CHIPPAC PTE LTE ; STATS CHIPPAC PTE LTD Bump-on-lead flip chip interconnection
20010013423,
20020041036,
20020121706,
20020192865,
20030049411,
20030067084,
20030116866,
20030127734,
20030168748,
20040035909,
20040056341,
20040105223,
20040108135,
20040232560,
20040232562,
20050046041,
20050082654,
20050103516,
20050248037,
20060131758,
20060202331,
20070200234,
20070259514,
20080093749,
20080179740,
20080277802,
20090108445,
20090114436,
20090152716,
20090191329,
20090288866,
20090308647,
20100139965,
20110049703,
20130214409,
20130277830,
JP10256307,
JP11145176,
JP11233571,
JP2000031204,
JP2000349194,
JP2001156203,
JP2002270732,
JP2004165283,
JP2004221205,
JP2005109187,
JP200528037,
JP4355933,
JP6503687,
JP9097791,
WO371842,
WO9306964,
//////
Executed onAssignorAssigneeConveyanceFrameReelDoc
Feb 01 2013STATS ChipPAC, Ltd.(assignment on the face of the patent)
Aug 06 2015STATS CHIPPAC, INC CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENTSECURITY INTEREST SEE DOCUMENT FOR DETAILS 0362880748 pdf
Mar 29 2016STATS ChipPAC LtdSTATS CHIPPAC PTE LTE CHANGE OF NAME SEE DOCUMENT FOR DETAILS 0383780227 pdf
Mar 29 2016STATS ChipPAC LtdSTATS CHIPPAC PTE LTD CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE S NAME FROM STATS CHIPPAC PTE LTE TO STATS CHIPPAC PTE LTD PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0227 ASSIGNOR S HEREBY CONFIRMS THE ASSIGNMENT 0648030368 pdf
May 03 2019CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENTSTATS CHIPPAC, INC RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS 0528440491 pdf
May 03 2019CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENTSTATS CHIPPAC PTE LTD FORMERLY KNOWN AS STATS CHIPPAC LTD RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS 0528440491 pdf
Date Maintenance Fee Events
Jan 11 2016M1551: Payment of Maintenance Fee, 4th Year, Large Entity.
Jan 10 2020M1552: Payment of Maintenance Fee, 8th Year, Large Entity.
Jan 10 2024M1553: Payment of Maintenance Fee, 12th Year, Large Entity.


Date Maintenance Schedule
Feb 11 20174 years fee payment window open
Aug 11 20176 months grace period start (w surcharge)
Feb 11 2018patent expiry (for year 4)
Feb 11 20202 years to revive unintentionally abandoned end. (for year 4)
Feb 11 20218 years fee payment window open
Aug 11 20216 months grace period start (w surcharge)
Feb 11 2022patent expiry (for year 8)
Feb 11 20242 years to revive unintentionally abandoned end. (for year 8)
Feb 11 202512 years fee payment window open
Aug 11 20256 months grace period start (w surcharge)
Feb 11 2026patent expiry (for year 12)
Feb 11 20282 years to revive unintentionally abandoned end. (for year 12)