Dynamic performance adjustment of computation means

Abstract

A dynamic performance circuit adjustment system and method that flexibly adjusts the performance of a logic circuit. The dynamic performance circuit adjustment system and method facilitates flexible power conservation. In one exemplary implementation, a dynamic performance adjustment control circuit controls performance adjustments to a logic circuit (e.g., a processor) and adjusts support functions for the logic circuit. The logic circuit performs operational functions (e.g., processing) or tasks that have different performance requirements. For example, some tasks performed by the logic circuit are required to be performed in a relatively short duration of time and other tasks performed by logic circuit have relatively longer time limitations. The dynamic performance adjustment control circuit adjusts the clock frequency and voltage at which the logic circuit operates to a relatively greater frequency and voltage for tasks required to be performed in a shorter duration of time and adjusts the frequency and voltage at which the logic circuit operates to a relatively lower frequency and voltage for tasks with longer timing tolerances. The dynamic performance adjustment system and method includes provisions to manage a transition in performance and support functions in a manner that reduces the risk of spurious signals or “glitches.”

Description

110 411. Address/data bus 410 is coupled to central processor 401, volatile memory 402 (e.g., random access memory RAM), non-volatile memory 403 (e.g., read only memory ROM), optional removable data storage device 404 (e.g., memory stick), display device 405, optional alphanumeric input device 406, optional cursor control or directing device 407, and signal communication port 408, modem 409 and main dynamic control adjustment circuit 110 411. In one embodiment of the present invention, central processor 401 includes main dynamic control adjustment circuit 110 411.

The components of computer system 400 cooperatively function to provide a variety of functions, including PIM, communications, etc. Address/data bus 410 communicates information, central processor 401 processes information and instructions, volatile memory 402 (e.g., random access memory RAM) stores information and instructions for the central processor 401 and non-volatile memory 403 (e.g., read only memory ROM) stores static information and instructions. Optional removable data storage device 404 (e.g., memory stick) also stores information and instructions. Display device 405 displays information to the computer user and an optional alphanumeric input device 406 is an input device, which in one implementation is a handwriting recognition pad (“digitizer”) having regions 306a and 306b (see FIG. 3A). Optional directing device 407 also communicates user input information and command selections to the central processor 401 via a touch screen capable of registering a position on the screen 405 where the stylus makes contact. Signal Communication port 408 is a communication interface (e.g., serial communications port 308) for communicating signals to and from a coupled peripheral device (not shown). Modem 409 facilitates communications with other devices. Main dynamic control adjustment circuit 110 411 controls adjustments to the performance of other components (e.g., processor 410, modem 409, etc.) and comprises a variety of configurations in different implementations. In one embodiment of the present invention, main dynamic control adjustment circuit 110 411 controls adjustments to the support functions (e.g., power supplies) to other components.

FIG. 5 is block diagram of dynamic performance circuit adjustment system 500 in accordance with one embodiment of the present invention. In one embodiment of the present invention, dynamic performance circuit adjustment system 500 is implemented in palm computer system 300. Dynamic performance circuit adjustment system 500 comprises main dynamic adjustment control circuit 550, clock circuit 520, voltage supply circuit 530, and logic circuit 570. Clock circuit 520 comprises a high frequency output 521 and a low frequency output 522. Voltage supply circuit 530 comprises high voltage output 531 and low voltage output 532. Main dynamic adjustment control circuit 550 is coupled to clock circuit 520, voltage supply circuit 530, and logic circuit 570. Logic circuit 570 is coupled to clock circuit 520, voltage supply circuit 530.

The components of dynamic performance circuit adjustment system 500 cooperatively operate to provide flexible dynamic performance adjustment of logic circuit 570. Logic circuit 570 performs operational functions (e.g., processing) or tasks. Clock circuit 520 supplies a clock signal 581 to logic circuit 570. Clock signal 581 is a first relatively high frequency or second relatively low frequency depending upon whether high frequency output 521 or low frequency output 522 is enabled. Voltage supply circuit 530 supplies a power signal 582 to logic circuit 570. Power signal 582 is a first relatively high voltage or a second relatively low voltage depending upon whether high voltage output 521 or low voltage output 532 are enabled. Main dynamic adjustment control circuit 550 controls adjustments to the performance of logic circuit 570. For example, main dynamic adjustment control circuit 550 enables either high frequency output 521 via high frequency enable signal 591 or low frequency output 522 via low frequency enable signal 592. Similarly main dynamic adjustment control circuit 550 enables either high voltage output 531 via high voltage enable signal 593 or low voltage output 532 via low voltage enable signal 594. At lower voltage settings, dynamic performance circuit adjustment system 500 facilitates power conservation.

A dynamic performance adjustment power control system of the present invention provides a significant degree of flexibility in adjusting performance (e.g., computation performance or speed of a processor). A dynamic performance adjustment power control system of the present invention is easily expanded to provide greater granularity of control. For example, in one embodiment of the present invention a clock circuit has numerous different frequency outputs that are controlled by a main dynamic performance adjustment control circuit. Similarly, in one embodiment of the present invention a power supply has numerous different voltage outputs (e.g., 5 volts, 3.3 volts, 2 volts, 0 volts, etc.) that are controlled by a main dynamic performance adjustment control circuit. Dynamic performance circuit adjustment system 500 “throttles” between the different voltage outputs depending upon performance requirements to conserve power when less than maximum performance is required.

In one embodiment of the present invention, a main dynamic performance adjustment control circuit disables a clock signal and/or a power signal to logic circuit 570. Main dynamic adjustment control circuit 550 (FIG. 5) disables both high frequency output 521 and low frequency output 522 turning off the clock signal to logic circuit 570. Similarly, main dynamic adjustment control circuit 550 also disables both high voltage output 531 and low voltage output 532 reducing power supplied to logic circuit 570.

A dynamic performance adjustment control circuit (e.g., main dynamic adjustment control circuit 550 shown in FIG. 5) comprises a variety of configurations or embodiments. For example, a dynamic performance adjustment control circuit comprises a processor in one embodiment of the present invention. In another exemplary implementation, the dynamic performance adjustment control circuit comprises a state machine. The dynamic performance adjustment control circuit dynamically adjusts the performance of a logic circuit (e.g., a processor) based upon the requirements of a particular task. In one exemplary implementation of the present invention, the dynamic performance adjustment control circuit determines an optimized clock rate and power supply voltage based upon the particular task to be performed by the logic circuit. In one embodiment, a processor included in a dynamic performance adjustment control circuit utilizes a hash table to determine appropriate performance controls and support functions.

FIG. 6 is an illustration of performance determination table 600 that can be used in one embodiment of the present invention. Performance determination table 600 tracks seven different tasks performed by a logic circuit and provides a correlation to their associated performance and support requirements. A first task requires maximum frequency and voltage and a processor in dynamic performance adjustment control circuit signals a frequency supply and voltage supply to provide a maximum frequency and voltage to the logic circuit. A second and sixth task require a relatively high frequency and voltage and a processor in dynamic performance adjustment control circuit signals a frequency supply and voltage supply to provide a relatively high frequency and voltage to the logic circuit. A third and seventh task require a relatively low frequency and voltage and a processor in dynamic performance adjustment control circuit signals a frequency supply and voltage supply to provide a relatively low frequency and voltage to the logic circuit. A forth task does not require maximum capacity of the logic circuit, however the performance is optimized by providing a maximum frequency and voltage for a period of time and turning off a frequency and voltage supply after the task is performed. The dynamic performance adjustment control circuit turns the frequency supply and power supply on when another task is required. A fifth task does not require the logic circuit to perform any functions and the dynamic performance adjustment control circuit turns off a frequency supply and voltage supply until the logic circuit is required to perform another task.

The present invention is very flexible in managing power consumption and facilitates the weighing of a number of factors in controlling the performance of a logic circuit such as a processor. One exemplary embodiment of the present includes a hash table in which multiple factors weighed in determining a task number. For example, a particular functional task may have a higher priority at times and a lower priority at others. The functional task is assigned different task numbers in the hash table according to the priority requirements, a higher priority task is assigned a task number associated with performing the functional task quickly (e.g., task number 4) and a lower priority task is assigned another task number associated with performing the functional task slower (e.g. task number 3).

In one embodiment of the present invention, the dynamic performance adjustment control circuit adjusts the performance of a processor in a modem in accordance with an appropriate communication rate. In this exemplary implementation, a modem initiates a communication session by engaging in a handshaking protocol in which a communication rate is negotiated based upon a number of parameters (e.g., the maximum baud rates of the modems on each end, line conditions, etc.). The negotiated communication rate is supplied to the dynamic performance adjustment control circuit. Based upon the negotiated communication rate the dynamic performance adjustment control circuit determines the optimal modem processor rate. The optimal processor rate is the lowest rate at which the modem processor adequately services a negotiated communication rate.

In one exemplary implementation of the present invention, the dynamic performance adjustment control circuit adjusts the performance of a processor in a modem that normally operates at a maximum 56K bits per second (bps). The modem processor requires a clock signal at a relatively high frequency to service the 56 Kbps rate. The dynamic performance adjustment control circuit enables a relatively high frequency output of a clock circuit and a relatively high voltage output of a power supply. However, if the negotiated communication rate is 28.8 Kpbs, the modem processor is capable servicing the 28.8 Kbps rate based upon a clock signal at a relatively low frequency and a dynamic performance adjustment control circuit enables a relatively low frequency output of a clock circuit and a relatively low voltage output of a power supply. In one embodiment of the present invention, a dynamic performance adjustment control circuit disables all clock outputs and power supply outputs when the modem is not actively engaged in transmitting or receiving data.

One embodiment of the present invention utilizes a processor included in the logic circuit to perform a dynamic performance adjustment control circuit. FIG. 7 is an illustration of dynamic performance circuit adjustment system 700. Dynamic performance circuit adjustment system 700 comprises logic circuit 705, clock control switch 740 and power supply switch 750. Logic circuit 705 is coupled to clock control switch 740 and power supply switch 750. Logic circuit 705 comprises processor 710 which performs operational functions or tasks as well as providing and dynamic adjustment control processing. The dynamic adjustment control processing issues a clock control signal 722 to clock control switch 740 and a voltage control signal 732 to power supply switch 750. Clock control signal 722 controls whether clock control switch selects to transmit X1 Mhx or X2 Mhz signal as clock signal 721. Voltage control signal 732 controls whether power supply switch selects to transmit V1 voltage signal or V2 voltage signal as power supply signal Vcc 731.

In one embodiment, 700, logic circuit 705 comprises a power control state machine (not shown) adjacent to processor 710. The power control state machine (not shown) is included in the same integrated circuit (IC). The power control state machine resists errors caused by changing support functions (e.g., voltage of a power supply signal) and/or performance (e.g., a clock rate). Processor 710 signals the power control state machine to change operating condition(s) and then the processor 710 ceases active operation. The power control state machine waits a predetermined time period (e.g., number of clock cycles) and then initiate and control the changes. In one embodiment of the present invention, after a second predetermined time sufficient to permit the clock generator and/or voltage generator to stabilize, the power control state machine signals processor 710 to resume active operation.

FIG. 8 is a block diagram of dynamic performance circuit adjustment method 800, in accordance with one embodiment of the present invention. Dynamic performance circuit adjustment method 800 provides flexible control of a functional circuit by facilitating adjustments to the performance of a functional circuit (e.g., a digital processor, analog amplifier, etc.) and support functions (e.g., power signals). Dynamic performance circuit adjustment method 800 is capable of adjusting performance in a manner that provides power conservation when a functional circuit is required to actively execute tasks at a rate lower than its maximum capability.

In step 810, an appropriate performance level (e.g., processing frequency, communication rate, etc.) is determined. In one embodiment of the present invention, the minimum level (e.g., frequency, voltage, etc.) at which a functional circuit adequately performs a task, (e.g., processing, modem communication, etc.) is considered an appropriate performance level. In exemplary implementation, an appropriate performance level is to operate at maximum capacity for a period of time and then throttle back for a period of time.

In step 820, an appropriate support level (e.g., voltage of a power supply signal) is determined. In one embodiment of the present invention, an appropriate voltage level of a power supply signals is determined based upon the frequency of a clock signal. For example, the higher the frequency of a clock signal the higher the appropriate voltage level of a power supply signal.

In step 830, a performance indication signal (e.g., performance indication signal 130) is received. The performance indication signal indicates the performance requirements of a functional circuit (e.g., functional circuit 120) for a particular task. In one embodiment of the present invention, a performance indication signal indicates a negotiated communication rate (e.g., a modem communication rate) or the speed at which a processor operates to adequately accommodate a negotiated communication rate.

In Step 840, a functional circuit ceases operations during a stabilization period. In one embodiment of dynamic performance circuit adjustment method 800, a functional circuit is directed to cease operations for a period of time sufficient to permit a dynamic performance adjustment control circuit to make changes to a performance input signal (e.g., a clock signal) and a support signal (e.g., a power signal) and permit the system to stabilize. Dynamic performance circuit adjustment method 800 makes changes to clock rates and or operating voltages while a functional circuit is not actively operating. A function circuit ceases operations for a predetermined period of time.

In step 850, a performance signal is adjusted. For example, the clock signal frequency can be adjusted by performance circuit adjustment method 800. In one embodiment of the present invention, the clock signal frequency is adjusted by enabling a first relatively high frequency clock output (e.g., turning on a relatively high frequency clock or making adjustments in clock multiplier or divider). The clock signal frequency can be adjusted by enabling a second relatively low frequency clock output (e.g., turning on a relatively low frequency clock or making adjustments in clock multiplier or divider). In one embodiment of the present invention, a performance signal is adjusted by switching between a low frequency source and a high frequency source.

In step 860, a support signal is adjusted. In one exemplary implementation of the present invention, a power signal voltage is adjusted by performance circuit adjustment method 800. The power signal voltage is adjusted by enabling a first relatively high voltage signal output (e.g., turning on a relatively high voltage source or making). In one embodiment of the present invention, the power signal voltage is adjusted by enabling a second relatively low voltage signal output (e.g., turning on a relatively low voltage source). A power signal is adjusted by switching between a low voltage source and a high voltage source. In one embodiment of the present invention, enabling a second relatively low voltage signal output or switching to a low voltage source conserves power.

In step 870 the process returns to step 810.

FIG. 9 is a flow chart of dynamic adjustment method 900, a present invention method of dynamically adjusting the performance of a functional circuit. In one embodiment of the present invention, utilizing dynamic adjustment method 900 to adjust performance facilitates power conservation. For example, dynamic adjustment method 900 adjusts the frequency at which a functional circuit performs and changes the voltage level of a power supply signal accordingly to support the frequency change. Thus, dynamic adjustment method facilitates power conservation during tasks requiring a lower voltage power signal.

In Step 910, a performance indication signal is accessed. The performance indication signal provides an indication of an adequate or desired performance level of a functional circuit (e.g., functional circuit 120)

In Step 920 a voltage level and clock frequency are dynamically determined based upon the performance signal accessed in Step 910. For example, a clock frequency and power supply voltage level are set to a maximum value if a performance indication signal indicates the functional circuit

In Step 930 a functional circuit performance level is dynamically adjusted by supplying the voltage level and clock frequency dynamically determined in Step 920. In one embodiment of the present invention, different voltage level power signals and clock frequency signals are selectively enabled. In one implementation, dynamic adjustment method 900 switches between different voltage level power signals and clock frequency signals. A functional circuit to cease operations for a period of time sufficient to permit a functional circuit to stabilize before a performance level adjustment.

In Step 940, a functional circuit performs a task at the performance level indicated by the performance indication signal accessed in Step 910. In one exemplary implementation a processor performs computations at a frequency slower than its maximum permitting it to operate at a voltage level less than its maximum and thus conserves power.

In Step 950 the process returns to Step 910.

Thus, the present invention system and method dynamically adjusts the performance of a functional circuit (e.g., processor) and is flexibly adaptable to various performance capabilities between a maximum performance level and a minimum performance level. The dynamic performance adjustment system and method of the present invention provides relative power conservation while permitting processing to be performed. The present invention is adaptable to a variety of implementations, for example a handheld palm computer. In one exemplary implementation, the present invention is utilized to control performance and functional support adjustments to a functional circuit comprising analog components. In one embodiment of the present invention, a dynamic performance adjustment control circuit controls adjustments to operating voltages of an amplification circuit of a Walkman portable radio as frequency and/or loudness requirements change.

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.

Claims

1. A dynamic performance circuit adjustment system comprising:

a functional circuit for performing operational tasks that have differing minimum performance and support function requirements; and

a dynamic performance adjustment control circuit for controlling performance adjustments to said functional circuit and adjustments to support functions for said functional circuit, said dynamic performance adjustment control circuit coupled to said functional circuit, wherein said dynamic performance adjustment control circuit:

a) adjusts the frequency and voltage at which said functional circuit operates to a relatively greater frequency and voltage for tasks required to be performed in a shorter duration of time,

b) adjusts the frequency and voltage at which said functional circuit operates to a relatively lower frequency and voltage for tasks with longer timing tolerance, and

c) transmits an operation control signal to said functional circuit directing said functional circuit to cease operations for a period of time sufficient to permit said dynamic performance adjustment control circuit to make changes to said performance input signal and said support signal and permit the system to stabilize.

2. The dynamic performance circuit adjustment system of claim 1 wherein said dynamic performance adjustment control circuit receives a performance indication signal indicating said minimal performance requirements of said functional circuit for a particular one of said tasks.

3. The dynamic performance circuit adjustment system of claim 2 wherein said dynamic performance adjustment control circuit makes an adjustment to a performance signal and a support signal for said functional circuit in accordance with said performance indication signal indicating.

4. The dynamic performance circuit adjustment system of claim 1 wherein said dynamic performance adjustment control circuit stops a clock signal to said functional circuit and sets a power supply signal to said functional circuit at zero volts when said functional circuit is not actively performing operation.

5. The dynamic performance circuit adjustment system of claim 1 wherein said functional circuit signals said dynamic performance adjustment control circuit to adjust performance and support functions for said functional circuit and said functional circuit ceases active operation for a period of time sufficient to permit said dynamic performance adjustment control circuit to make changes to said performance input signal and said support signal and permit the system to stabilize.

6. A dynamic performance circuit adjustment system implemented in a palm computer system comprising;

a logic circuit for performing operational functions or tasks;

a clock circuit for supplying a clock signal to said logic circuit, said clock circuit coupled to said logic circuit;

a voltage supply circuit for supplying a power signal to said logic circuit, said voltage supply circuit coupled to said logic circuit; and

a main dynamic adjustment control circuit for controlling the performance of said logic circuit by varying a frequency of said clock signal and by varying the voltage of said power signal, wherein said main dynamic adjustment control circuit signals said logic circuit to cease active operations for a period of time sufficient to permit said dynamic performance adjustment control circuit to make changes to said frequency and said voltage and and permit the system to stabilize, said main dynamic adjustment control circuit coupled to said logic circuit.

7. The dynamic performance circuit adjustment system of claim 6 wherein said clock circuit further comprises:

a high frequency output for supplying a first relatively high frequency signal; and

a low frequency output for supplying a second relatively low frequency signal.

8. The dynamic performance circuit adjustment system of claim 6 wherein said voltage supply circuit further comprises:

a high voltage output for supplying a first relatively high voltage signal; and

a low voltage output for supplying a first relatively low voltage signal.

9. The dynamic performance circuit adjustment system of claim 6 wherein said main dynamic adjustment control circuit selectively enables a high frequency output via a high frequency enable signal and a low frequency output via a low frequency enable signal.

10. The dynamic performance circuit adjustment system of claim 6 wherein said main dynamic adjustment control circuit selectively enables a high voltage output via a high voltage enable signal and a low voltage output via a low voltage enable signal.

11. The dynamic performance circuit adjustment system of claim 6 wherein said performance adjustment control circuit disables a clock signal and a power signal to logic circuit.

12. A dynamic performance circuit adjustment method comprising the steps of:

a) accessing a performance indication signal;

b) based upon said performance indication signal, dynamically determining a voltage level and a clock frequency;

c) supplying said voltage level and said clock frequency to said functional circuit to dynamically adjust its performance level and directing functional operations to cease for a period of time sufficient to permit stabilize before adjusting said performance level;

d) performing a task using said factional circuit; and

e) repeating steps a) through d).

13. A method of claim 12 further comprising the step of ceasing functional circuit active operation during stabilization period.

14. A method of claim 12 further comprising the steps of:

c1) selecting a first relatively high frequency clock output; and

c2) selecting a second relatively low frequency clock output.

15. A dynamic performance circuit adjustment method of claim 12 wherein step c) further comprises the step of switching between a low frequency source and a high frequency source.

16. A method of claim 12 wherein step c) further comprises the steps of:

enabling a first relatively high voltage signal output; and

enabling a second relatively low voltage signal output.

17. A method of claim 12 wherein step c) further comprises the step of switching between a low voltage source and a high voltage source.

18. A dynamic performance adjustment system comprising:

a display operable to display information thereon;

a memory device;

a functional circuit for performing operational tasks that have differing minimum frequency and voltage requirements; and

a dynamic performance adjustment control circuit for controlling at least one of frequency adjustment and voltage adjustment to said functional circuit, said dynamic performance adjustment control circuit coupled to said functional circuit, wherein said dynamic performance adjustment control circuit:

a) adjusts at least one of frequency and voltage at which said functional circuit operates to at least one of a relatively greater frequency and a relatively greater voltage for tasks required to be performed in a shorter duration of time,

b) adjusts at least one of frequency and voltage at which said functional circuit operates to at least one of a relatively lower frequency and a relatively lower voltage for tasks with longer timing tolerance, and

c) transmits an operation control signal to said functional circuit directing said functional circuit to cease operations for a period of time sufficient to implement a change to said frequency and said voltage supplied to said functional circuit, said period of time permitting said dynamic performance adjustment control circuit to control at least one of frequency adjustment and voltage adjustment to said functional circuit and permitting said dynamic performance adjustment system to stabilize.

19. The dynamic performance adjustment system of claim 18, wherein said period of time is sufficient to permit said dynamic performance adjustment control circuit to control both frequency adjustment and voltage adjustment to said functional circuit.

20. The dynamic performance adjustment system of claim 18, wherein said dynamic performance adjustment control circuit receives a performance indication signal indicating a minimal performance requirement of said functional circuit for a particular one of said operational tasks.

21. The dynamic performance adjustment system of claim 20, wherein said dynamic performance adjustment control circuit controls at least one of frequency adjustment and voltage adjustment to said functional circuit in accordance with said performance indication signal.

22. The dynamic performance adjustment system of claim 18, wherein said dynamic performance adjustment control circuit stops a clock signal to said functional circuit and sets a power supply signal to said functional circuit at substantially zero volts when said functional circuit is not actively performing an operation.

23. The dynamic performance adjustment system of claim 18, wherein said functional circuit signals said dynamic performance adjustment control circuit to control at least one of frequency adjustment and voltage adjustment for said functional circuit, and wherein said functional circuit ceases operation for a period of time sufficient to permit said dynamic performance adjustment control circuit to control at least one of frequency adjustment and voltage adjustment to said functional circuit and permit the dynamic performance adjustment system to stabilize.

24. The dynamic performance adjustment system of claim 18, further comprising a bus.

25. The dynamic performance adjustment system of claim 24, wherein said memory device is coupled to said bus.

26. The dynamic performance adjustment system of claim 25, wherein said dynamic performance adjustment control circuit is coupled to said bus.

27. The dynamic performance adjustment system of claim 18, further comprising an input device.

28. The dynamic performance adjustment system of claim 18, further comprising a communication device for communicating signals.

29. The dynamic performance adjustment system of claim 18, further comprising a power source.

30. A mobile computer system comprising:

a display for displaying information;

a memory unit;

a logic circuit for performing operational functions or tasks;

a clock circuit for supplying a clock signal to said logic circuit, said clock circuit coupled to said logic circuit;

a voltage supply circuit for supplying a power signal to said logic circuit, said voltage supply circuit coupled to said logic circuit; and

a dynamic adjustment control circuit for controlling the performance of said logic circuit by varying at least one of a frequency of said clock signal and a voltage of said power signal to said logic circuit, wherein said dynamic adjustment control circuit signals said logic circuit to cease active operations for a period of time sufficient to implement a change to said frequency and said voltage supplied to said logic circuit, said period of time permitting said dynamic adjustment control circuit to vary at least one of said frequency of said clock signal and said voltage of said power signal and permitting the mobile computer system to stabilize, said dynamic adjustment control circuit being coupled to said logic circuit.

31. The mobile computer system of claim 30, wherein said clock circuit further comprises: a high frequency output for supplying a high frequency signal; and a low frequency output for supplying a low frequency signal.

32. The mobile computer system of claim 31, wherein said voltage supply circuit further comprises: a high voltage output for supplying a high voltage signal; and a low voltage output for supplying a low voltage signal.

33. The mobile computer system of claim 32, wherein said dynamic adjustment control circuit selectively enables said high frequency output via a high frequency enable signal and said low frequency output via a low frequency enable signal.

34. The mobile computer system of claim 33, wherein said dynamic adjustment control circuit selectively enables said high voltage output via a high voltage enable signal and said low voltage output via a low voltage enable signal.

35. The mobile computer system of claim 30, wherein said dynamic adjustment control circuit disables said clock signal and said power signal to said logic circuit.

36. The mobile computer system of claim 30, further comprising an input device for receiving user input.

37. The mobile computer system of claim 30, further comprising a communication device for communicating signals.

38. The mobile computer system of claim 30, further comprising a power source.

39. A method comprising:

a) accessing a performance indication signal within a computer system including a display, a memory unit, and a functional circuit;

b) based upon said performance indication signal, dynamically determining at least one of a voltage level and a clock frequency for said functional circuit;

c) supplying at least one of said voltage level and said clock frequency to said functional circuit to dynamically adjust a performance level for said functional circuit and directing said functional circuit to cease functional operations for a period of time sufficient to implement a change to said voltage level and said clock frequency supplied to said functional circuit, said period of time permitting stabilization before adjustment of said performance level;

d) performing a task using said functional circuit; and

e) repeating said a) through d).

40. The method of claim 39, wherein said c) comprises:

enabling one of a high frequency clock output and a low frequency clock output.

41. The method of claim 39, wherein said c) comprises:

switching between a low frequency source and a high frequency source.

42. The method of claim 39, wherein said c) comprises:

enabling one of a high voltage signal output and a low voltage signal output.

43. The method of claim 39, wherein said c) comprises:

switching between a low voltage source and a high voltage source.

44. The method of claim 39, wherein said computer system further includes a user input device.

45. The method of claim 39, wherein said computer system further includes a user input device.

46. The method of claim 39, wherein said computer system further includes a power source.

47. A dynamic performance adjustment system comprising:

a display operable to display information thereon;

a memory device;

a functional circuit for performing operational tasks that have differing minimum frequency and voltage requirements; and

a dynamic performance adjustment control circuit for controlling frequency adjustment and voltage adjustment to said functional circuit, said dynamic performance adjustment control circuit coupled to said functional circuit, wherein said dynamic performance adjustment control circuit:

a) adjusts frequency and voltage at which said functional circuit operates to a relatively greater frequency and a relatively greater voltage for tasks required to be performed in a shorter duration of time,

b) adjusts frequency and voltage at which said functional circuit operates to a relatively lower frequency and a relatively lower voltage for tasks with longer timing tolerance, and

c) transmits an operation control signal to said functional circuit directing said functional circuit to cease operations for a period of time sufficient to implement a change to said frequency and said voltage supplied to said functional circuit, said period of time permitting said dynamic performance adjustment control circuit to control frequency adjustment and voltage adjustment to said functional circuit and permitting said dynamic performance adjustment system to stabilize.

48. The dynamic performance adjustment system of claim 47, wherein said dynamic performance adjustment control circuit receives a performance indication signal indicating a minimal performance requirement of said functional circuit for a particular one of said operational tasks.

49. The dynamic performance adjustment system of claim 48, wherein said dynamic performance adjustment control circuit controls frequency adjustment and voltage adjustment to said functional circuit in accordance with said performance indication signal.

50. The dynamic performance adjustment system of claim 47, wherein said dynamic performance adjustment control circuit stops a clock signal to said functional circuit and sets a power supply signal to said functional circuit at substantially zero volts when said functional circuit is not actively performing an operation.

51. The dynamic performance adjustment system of claim 47, wherein said functional circuit signals said dynamic performance adjustment control circuit to control frequency adjustment and voltage adjustment for said functional circuit, and wherein said functional circuit ceases operation for a period of time sufficient to permit said dynamic performance adjustment control circuit to control frequency adjustment and voltage adjustment to said functional circuit and permit the dynamic performance adjustment system to stabilize.

52. The dynamic performance adjustment system of claim 47, further comprising a bus.

53. The dynamic performance adjustment system of claim 52, wherein said memory device is coupled to said bus.

54. The dynamic performance adjustment system of claim 53, wherein said dynamic performance adjustment control circuit is coupled to said bus.

55. The dynamic performance adjustment system of claim 47, further comprising an input device.

56. The dynamic performance adjustment system of claim 47, further comprising a communication device for communicating signals.

57. The dynamic performance adjustment system of claim 47, further comprising a power source.