Method for driving a nonvolatile semiconductor memory device

Abstract

A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device includes a semiconductor layer having a channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and a gate electrode provided on the second insulating film, and changes its data memory state by injection of charges into the floating electrode. The method includes to achieve a state in which charges having a first polarity are injected into the floating electrode: providing a first potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the second insulating film; subsequently providing a second potential difference between the semiconductor layer and the gate electrode to inject charges having a second polarity opposite to the first polarity into the second insulating film; and subsequently providing a third potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the floating electrode.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is
After time TT7, charge retention continues until the next charge injection is performed.

In setting the voltage used for the after erase operation AE, electrical damage to the first insulating film 5A needs to be taken into consideration. Preferably, electric field applied to the first insulating film 5A is 20 MV/cm or less. More preferably, for rapid operation at low voltage, electric field applied to the first insulating film 5A is 15 MV/cm or less, and the application time is 10 seconds or less.

FIG. 21 is a schematic cross-sectional view illustrating charge distribution formed by application of the method for driving the nonvolatile semiconductor memory device according to the third embodiment of the invention.

FIG. 21 shows the charge distribution ρ(x) in the second insulating film 5B of the nonvolatile semiconductor memory device after the after erase operation AE following the data program operation DE. The horizontal axis of this figure represents the distance x in the direction from the gate electrode 4 to the floating electrode 3 and the vertical axis represents the amount of charges.

As shown in FIG. 21, the charge distribution ρ(x) (charge distribution E3) by the method for driving according to this embodiment is such that the nearly whole area of the second insulating film 5B (T₂) is filled with electrons and the region near the floating electrode 3 is filled with holes. That is, the charge distribution is one illustrated in FIG. 19B.

That is, in the charge distribution in the second insulating film 5B just after completion of the after erase operation AE, electrons exist in the whole area of the second insulating film 5B at a density of N_E(cm⁻³), and holes exist in the region with a thickness of t₂ near the interface with the floating electrode 3 at a density of N_H(cm⁻³). At this time, the threshold voltage of the floating electrode 3 becomes:

$\begin{array}{cc}\begin{array}{c}{V}_{t1}=-\frac{T_{2}Q}{{\varepsilon }_2{\varepsilon }_0}-\frac{1}{{\varepsilon }_2{\varepsilon }_0}{\int }_0^{T_2}\rho \left(x\right)xdx\\ =\frac{T_{2}Q}{{\varepsilon }_2{\varepsilon }_0}+\frac{{\mathrm{qN}}_E}{{\varepsilon }_2{\varepsilon }_0}{T}_2^2-\frac{{\mathrm{qN}}_H}{{\varepsilon }_2{\varepsilon }_0}{T}_2^2+\frac{{\mathrm{qN}}_H}{{\varepsilon }_2{\varepsilon }_0}{\left(T_2-t_2\right)}^2\end{array}& \left(4\right)\end{array}$
At this time, in the process of charge retention, if holes near the interface with the floating electrode 3 in the second insulating film 5B diffuse uniformly into the second insulating film 5B, the threshold voltage becomes:

$\begin{array}{cc}\begin{array}{c}{V}_{t2}=-\frac{T_{2}Q}{{\varepsilon }_2{\varepsilon }_0}-\frac{1}{{\varepsilon }_2{\varepsilon }_0}{\int }_0^{T_2}\rho \left(x\right)xdx\\ =\frac{T_{2}Q}{{\varepsilon }_2{\varepsilon }_0}+\frac{{\mathrm{qN}}_E}{{\varepsilon }_2{\varepsilon }_0}{T}_2^2-\frac{{\mathrm{qN}}_H}{{\varepsilon }_2{\varepsilon }_0}{t}_2{T}_2\end{array}& \left(5\right)\end{array}$
From equation (4) and equation (5), the threshold variation becomes:

$\begin{array}{cc}{V}_{t2}-V_{t1}=\frac{{\mathrm{qN}}_H}{{\varepsilon }_2{\varepsilon }_0}{t}_2\left(T_2-t_2\right)& \left(6\right)\end{array}$

In the case where holes in the second insulating film 5B are distributed only in the region near the interface with the floating electrode 3 (T₂>t₂), the threshold voltage increases. That is, if holes existing in the region near the interface with the floating electrode 3 in the second insulating film 5B are re-distributed (hole redistribution) throughout the whole area of the second insulating film 5B in the retention process, the effect of increasing the threshold voltage is produced.

On the other hand, in the process of charge retention in the floating electrode 3, charges in the second insulating film 5B are released to the gate electrode 4. Charges stored in the floating electrode 3 are also released through the first insulating film 5A or the second insulating film 5B to the floating electrode 3 and the gate electrode 4. Release of charges results in decreasing the threshold. In particular, release of electrons is the main cause of the threshold decrease.

FIG. 22 is a graph illustrating the change of threshold voltage by the method for driving the nonvolatile semiconductor memory device according to the third embodiment of the invention.

The horizontal axis of the figure represents the time and the vertical axis represents the threshold voltage. The broken line represents the variation of the threshold voltage resulting from the above hole redistribution, the dashed line represents the variation of the threshold voltage resulting from the above electron release, and the solid line represents the variation of the total threshold voltage resulting from both the hole redistribution and the electron release.

As shown in FIG. 22, holes are distributed only in the region near the interface with the floating electrode 3 in the second insulating film 5B and the holes are redistributed, and thereby the threshold voltage increases with time. On the other hand, release of electrons stored in the floating electrode 3 results in the threshold voltage decrease with time. Since the threshold voltage increase resulting from the hole redistribution and the threshold voltage decrease resulting from the electron release are opposite in their behaviors, they compensate each other. That is, in the method for driving the non-volatile semiconductor memory device according to this embodiment, performing the after erase operation AE following the data program operation DW (electron injection) can accelerate the redistribution of charges in the second insulating film 5B during the charge retention process, and this charge redistribution compensates the threshold voltage decrease resulting from the charge release, and consequently has the effect of suppressing the variation of the threshold voltage.

Second Comparative Example

A method for driving the nonvolatile semiconductor memory device of a second comparative example does not include the step S320 illustrated in FIG. 16. That is, the step S420 illustrated in FIG. 17 is not included. Furthermore, after the data program operation DW, the after erase operation AE illustrated in FIG. 18 is not included. Therefore, the charge distribution after the data program operation DW is such that illustrated in FIG. 19A. That is, a sufficient amount of electrons are injected during time TT5 before time TT6 as the data program operation DW and defects in the second insulating film 5B are filled with electrons. And like the case of this embodiment, holes do not exist in the region near the interface with the floating electrode 3 in the second insulating film 5B. Therefore, no means for compensating the threshold voltage decrease results in the threshold voltage decrease during the retention time.

FIG. 23 is a graph illustrating of the temporal variations of threshold voltage by the method for driving the nonvolatile semiconductor memory device according to the third embodiment of the invention and the method for driving of the second comparative example.

FIG. 23 illustrates the temporal variation of the threshold voltage in the state of charge retention, the horizontal axis represents the time and the vertical axis represents the threshold voltage. In the figure, the retention curve H1 corresponds to the method for driving the nonvolatile semiconductor memory device according to this embodiment and the retention curve H2 corresponds to the method for driving of the second comparative example.

As shown in FIG. 23, in the method for driving the non-volatile semiconductor memory device according to this embodiment, the after erase operation AE performed after the data program operation DW (electron injection) results in the retention characteristics of the threshold voltage as represented by the retention curve H1. On the other hand, in the method for driving of the second comparative example, the after erase operation AE omitted after the data program operation (electron injection) results in the characteristics as represented by the retention curve H2. That is, the method for driving according to this embodiment can delay the variation of the threshold voltage.

As described above, in the method for driving the nonvolatile semiconductor memory device according to this embodiment, the after erase operation AE performed after the data program operation DW (electron injection) enhances the retention characteristics of the threshold voltage.

It is noted that the voltage pulse used for after erase operation AE may be a combination of a plurality of voltage pulses. At this time, at least the combination satisfies: all the applied voltages have the same polarity, and the threshold after application of the pulses reaches an intended threshold.

Fourth Embodiment

Next, a fourth embodiment of the invention will be described.

The method for driving the nonvolatile semiconductor memory device according to the third embodiment described above has enhanced the retention characteristics after injecting charges for the data program operation DW into the floating electrode 3. At this time, the case where electrons are injected as charges has been described, however, the invention is not limited to this and can be applied to the case of injecting holes.

A method for driving the nonvolatile semiconductor memory device according to the fourth embodiment enhances the retention characteristics in the case of injecting holes, namely, in the case of data erase operation. In this case, it is desirable to reverse the polarity described in the third embodiment.

That is, the first polarity is the positive polarity, a fifth potential difference is provided by application of an voltage lower than a voltage applied to the semiconductor layer 1 to the gate electrode 4, and a sixth potential difference is provided by application of a voltage higher than a voltage applied to the semiconductor layer 1 to the gate electrode 4.

FIG. 24 is a schematic cross-sectional view illustrating charge distribution formed by application of the method for driving the nonvolatile semiconductor memory device according to the fourth embodiment of the invention.

FIG. 24 shows the charge distribution ρ(x) in the second insulating film 5B of the nonvolatile semiconductor memory device after an after program operation AW following the data erase operation DE (hole injection into the floating electrode 3) in the case of applying the method for driving of this embodiment. The horizontal axis of this figure represents the distance x in the direction from the gate electrode 4 to the floating electrode 3 and the vertical axis represents the amount of charges.

As shown in FIG. 24, the charge distribution ρ(x) (charge distribution E4) formed by the method for driving according to this embodiment is such that the nearly whole area of the second insulating film 5B (T₂) is filled with holes and the region near the floating electrode 3 is filled with electrons.

This enhances the retention characteristics after the data erase operation by the same effect as that described in the third embodiment.

That is, when electrons existing in the region near the interface with the floating electrode 3 in the second insulating film 5B are redistributed (electron redistribution) throughout the whole area of the second insulating film 5B during the retention process, the threshold voltage decreases. On the other hand, holes in the second insulating film 5B are released from the floating electrode 3 to the gate electrode 4 and the semiconductor layer 1 during the charge retention process in the floating electrode 3, and the threshold voltage increases. Since the variations of the threshold voltages are opposite in their behaviors each other, both compensate each other, and consequently the retention characteristics after the data erase operation is enhanced.

FIG. 25 is a graph illustrating the change of threshold voltage by the method for driving the nonvolatile semiconductor memory device according to the fourth embodiment of the invention.

The horizontal axis of the figure represents the time and the vertical axis represents the threshold voltage. The broken line represents the variation of the threshold voltage resulting from the above electron redistribution, the dashed line represents the variation of the threshold voltage resulting from the above hole release, and the solid line represents the variation of the total threshold voltage resulting from both the electron redistribution and the hole release.

As shown in FIG. 25, electrons are distributed in the region near the interface with the floating electrode 3 in the second insulating film 5B and the electrons are redistributed, and thereby the threshold voltage decreases with time. On the other hand, release of holes stored in the floating electrode 3 results in the threshold voltage increase with time. Since the threshold voltage increase resulting from the electron redistribution and the threshold voltage decrease resulting from the hole release are opposite in their behaviors, they compensate each other.

That is, in the method for driving the nonvolatile semiconductor memory device according to this embodiment, performing the after program operation AW following the data erase operation DE (hole injection) can accelerate the redistribution of charges in the second insulating film 5B during the charge retention process, and this charge redistribution compensates the threshold voltage decrease resulting from the charge release, and consequently has the effect of suppressing the variation of the threshold voltage.

It is noted that the methods for driving the nonvolatile semiconductor memory device according to the first through fourth embodiments described above may be sequentially performed.

That is, the first potential difference is provided between the semiconductor layer 1 and the gate electrode 4 to inject charges having the first polarity into the second insulating film 5B, after that the second potential difference is provided between the semiconductor layer 1 and the gate electrode 4 to inject charges having the second polarity opposite to the first polarity into the second insulating film 5B, after that the third potential difference is provided between the semiconductor layer 1 and the gate electrode 4 to inject charges having the first polarity into the floating electrode 3, after that the fourth potential difference is provided between the semiconductor layer 1 and the gate electrode 4 to inject charges having the second polarity into the second insulating film 5B.

This speeds up the data program operation and the data erase operation, and enhances the retention characteristics after the data program operation and the data erase operation.

Fifth Embodiment

Next, a fifth embodiment of the invention will be described.

FIG. 26 is a block diagram illustrating the configuration of a nonvolatile semiconductor memory device according to the fifth embodiment of the invention.

As shown in FIG. 26, the nonvolatile semiconductor memory device according to the fifth embodiment of the invention includes a memory cell array 11 and a control circuit 10. Each memory cell in the memory cell array 11 is a transistor type memory cell having the floating electrode 3.

More specifically, the memory cell 11 includes the source/drain regions 2 spaced from each other in the surface portion of the semiconductor layer 1, the first insulating film 5A provided on the channel between the source/drain regions 2, the floating electrode 3 provided on the first insulating film 5A, the second insulating film 5B provided on the floating electrode 3 and the gate electrode 4 provided on the second insulating film 5B.

The control circuit 10 performs at least any of the methods for driving according to respective embodiments described above.

The control circuit 10 includes a voltage generation circuit 13 for generating a program voltage, an erase voltage, or a read voltage, a voltage control circuit 12 for coupling the voltage generated in the voltage generation circuit 13 to the memory cell array 11, and a read circuit 14 for reading information programmed in the memory cell array 11.

The voltage required for implementing each operation of the preset P1, the preset P2, the after erase operation AE, the after program operation AW, the data program operation DW and the data erase operation DE described in the first to fourth embodiments is supplied from the voltage generation circuit 13. The application time required for each operation is controlled by the voltage control circuit 12.

It is noted that the method for driving the nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device according to the embodiments described above are applicable to all of the floating gate memory cells. For example, the material of the semiconductor layer 1 is not limited to a silicon substrate, but may be a polysilicon substrate, a SiGe substrate, a Ge substrate, or a SiGeC substrate. The configuration of the semiconductor layer 1 is not limited to a P-type well or a P-type semiconductor layer (SOI), but may be SGOI (silicon germanium on insulator) or GOI (germanium on insulator).

The floating gate flash memory having the high dielectric material applied to the insulating film has charge trapping characteristics being taken on by the high dielectric material. Therefore, the method for driving the nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device according to the embodiments described above are suitably applicable to the floating gate flash memory having the high dielectric material applied to the insulating film.

The floating gate memory cell may be configured as a vertical transistor or a FIN transistor. Alternatively, the memory cell array itself may have a vertically laminated structure.

The invention is applicable to various memory cell arrays having the memory cell including the floating gate electrode. Such memory cell arrays include not only of the NAND type and the NOR type, but also of the AND type (H. Kume, M. Kato, T. Adachi, T. Tanaka, T. Sasaki, T. Okazaki, N. Miyamoto, S. Saeki, Y. Ohji, M. Ushiyama, J. Yagami, T. Morimoto, and T. Nishida, “A 1.28 μm² contactless memory cell technology for a 3V-only 64 Mbit EEPROM”, IEDM Tech. Dig., pp. 991-993, December (1992)), the DINOR type (H. Onoda, Y. Kunori, S. Kobayashi, M. Ohi, A. Fukumoto, N. Ajika, and H. Miyoshi, “A novel cell structure suitable for a 3 volt operation, sector erase flash memory”, IEDM Tech. Dig., pp. 599-602, December (1992)), the split gate type (G. Samachisa, C. Su, Y. Kao, G. Smarandoiu, T. Wong, and C. Hu, “A 128K flash EEPROM using double polysilicon technology”, ISSCC Dig. Tech. Papers, pp. 76-77, February (1987)), the stack type (V. N. Kynett, A. Baker, M. Fandrich, G. Hoekstra, O. Jungroth, J. Kreifels, and S. Wells, “An in-system reprogrammable 256K CMOS flash memory”, ISSCC Dig. Tech. Papers, pp. 132-133, February (1988)), the triple layer polysilicon type (F. Masuoka, M. Asano, H. Iwashita, T. Komuro, and S. Tanaka, “A new flash EEPROM cell using triple polysilicon technology”, IEDM Tech. Dig., pp. 464-467, December (1984)), and the 3Tr-NAND (JP-A 2007-115407(Kokai)).

Furthermore, the method for driving the nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device according to the embodiments described above are described with the charge injection from the semiconductor layer 1 in mind, however, are also applicable to a gate injection memory cell having charges injected from the gate electrode 4.

In the gate injection memory cell, the semiconductor layer 1 and the gate electrode 4 have opposite roles in the charge injection into the floating electrode 3. Therefore, by exchange the voltage applied to the semiconductor layer 1 with the voltage applied to the gate electrode 4, the method for driving the nonvolatile semiconductor memory device and the non-volatile semiconductor memory device according to the first to fifth embodiments are applicable to the gate injection memory cell.

The embodiment of the invention has been described with reference to the examples. However, the invention is not limited to these examples. For example, the specific configuration of respective elements comprising the method for driving the nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device are encompassed within the scope of the invention as long as a person skilled in the art could have worked the invention similarly by selecting properly from the publicly known scope and achieve the same effect.

Combinations of any two or more elements among respective specific examples within the technically possible range are also encompassed within the scope of the invention as long as they include the features of the invention.

In addition, all of the method for driving the nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device which a person skilled in the art could have worked by the proper design variation on the basis of the method for driving the nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device described above as the embodiment of the invention are also encompassed within the scope of the invention as long as they include the features of the invention.

It is perceived that a person skilled in the art could have made various corrections and modifications in the category of the invention and these corrections and modifications are also encompassed within the scope of the invention.

Claims

1. A method for driving a nonvolatile semiconductor memory device having a semiconductor layer having a channel and source/drain regions provided on both sides of the channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and a gate electrode provided on the second insulating film, the nonvolatile semiconductor memory device changing its data memory state by injection of charges into the floating electrode,

the method comprising, to achieve a state in which charges having a first polarity are injected into the floating electrode:

providing a first potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the second insulating film;

subsequently providing a second potential difference between the semiconductor layer and the gate electrode to inject charges having a second polarity opposite to the first polarity into the second insulating film; and

subsequently providing a third potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the floating electrode.

2. The method according to claim 1, wherein

after providing the third potential difference between the semiconductor and the gate electrode,

a fourth potential difference is provided between the semiconductor layer and the gate electrode to inject charges having the second polarity into the second insulating film.

3. The method according to claim 1, wherein before providing the third potential difference between the semiconductor layer and the gate electrode, defects in a region in the second insulating film near the floating electrode are filled with the charges having the second polarity and defects in a remaining region in the second insulating film are filled with the charges having the first polarity.

4. The method according to claim 1, wherein at least any of the first insulating film and the second insulating film includes at least one selected from a group consisting of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnia, hafnium aluminate, hafnia nitride, hafnium nitride aluminate, hafnium silicate, hafnium nitride silicate, lanthanum oxide, and lanthanum aluminate.

5. The method according to claim 1, wherein an electric field applied to the first insulating film by the first potential difference and the second potential difference is 20 MV/cm or less.

6. The method according to claim 1, wherein an electric field applied to the first insulating film by the first potential difference and the second potential difference is 15 MV/cm or less, and application time of the electric field is 10 seconds or less.

7. The method according to claim 1, wherein the providing the first potential difference includes a plurality of providing potential differences to inject the charges having the first polarity into the second insulating film.

8. The method according to claim 1, wherein the providing of the second potential difference includes a plurality of providing potential differences to inject the charges having the second polarity into the second insulating film.

9. The method according to claim 1, wherein

the first polarity is negative,

the first potential difference is a potential difference such that the gate electrode has a higher potential than the semiconductor layer,

the second potential difference is a potential difference such that the gate electrode has a lower potential than the semiconductor layer, and

the third potential difference is a potential difference such that the gate electrode has a higher potential than the semiconductor layer.

10. The method according to claim 9, wherein before providing the third potential difference between the semiconductor layer and the gate electrode, defects in a region in the second insulating film near the floating electrode are filled with holes and defects in a remaining region in the second insulating film are filled with electrons.

11. The method according to claim 9, wherein

after providing the third potential difference between the semiconductor layer and the gate electrode,

a fourth potential difference is provided between the semiconductor layer and the gate electrode to inject the charges having the second polarity being positive into the second insulating film.

12. The method according to claim 1, wherein

the first polarity is positive,

the first potential difference is a potential difference such that the gate electrode has a lower potential than the semiconductor layer,

the second potential difference is a potential difference such that the gate electrode has a higher potential than the semiconductor layer, and

the third potential difference is a potential difference such that the gate electrode has a lower potential than the semiconductor layer.

13. The method according to claim 12, wherein before providing the third potential difference between the semiconductor layer and the gate electrode, defects in a region in the second insulating film near the floating electrode are filled with electrons and defects in a remaining region in the second insulating film are filled with holes.

14. The method according to claim 12, wherein

after providing the third potential difference between the semiconductor layer and the gate electrode,

a fourth potential difference between the semiconductor layer and the gate electrode to inject the charges having the second polarity being negative into the second insulating film.

15. A method for driving a nonvolatile semiconductor memory device having a semiconductor layer having a channel and source/drain regions provided on both sides of the channel, a first insulating film provided on the channel, a floating electrode provided on the first insulating film, a second insulating film provided on the floating electrode, and a gate electrode provided on the second insulating film, the nonvolatile semiconductor memory device changing its data memory state by injection of charges into the floating electrode,

the method comprising, to achieve a state in which charges having a first polarity are injected into the floating electrode:

providing a first potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the floating electrode; and

subsequently providing a second potential difference between the semiconductor layer and the gate electrode to inject charges having a second polarity opposite to the first polarity into the second insulating film.

16. The method according to claim 15, wherein providing the second potential difference between the semiconductor layer and the gate electrode injects the charges having the second polarity into a region of the second insulating film facing the floating electrode.

17. The method according to claim 15, wherein at least any of the first insulating film and the second insulating film includes at least one selected from a group consisting of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnia, hafnium aluminate, hafnia nitride, hafnium nitride aluminate, hafnium silicate, hafnium nitride silicate, lanthanum oxide, and lanthanum aluminate.

18. The method according to claim 15, wherein

the first polarity is negative,

the first potential difference is a potential difference such that the gate electrode has a higher potential than the semiconductor layer,

the second potential difference is a potential difference such that the gate electrode has a lower potential than the semiconductor layer.

19. The method according to claim 15, wherein

the first polarity is positive,

the first potential difference is a potential difference such that the gate electrode has a lower potential than the semiconductor layer,

the second potential difference is a potential difference such that the gate electrode has a higher potential than the semiconductor layer.

20. A nonvolatile semiconductor memory device comprising:

a semiconductor layer having a channel and source/drain regions provided on both sides of the channel;

a first insulating film provided on the channel;

a floating electrode provided on the first insulating film;

a second insulating film provided on the floating electrode;

a gate electrode provided on the second insulating film; and

a control circuit controlling its data memory state by injection of charges into the floating electrode,

the control circuit being configured to perform, to achieve a state in which charges having a first polarity are injected into the floating electrode:

providing a first potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the second insulating film;

subsequently providing a second potential difference between the semiconductor layer and the gate electrode to inject charges having a second polarity opposite to the first polarity into the second insulating film; and

subsequently providing a third potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the floating electrode.

21. A nonvolatile semiconductor memory device comprising:

a semiconductor layer having a channel and source/drain regions provided on both sides of the channel;

a first insulating film provided on the channel;

a floating electrode provided on the first insulating film;

a second insulating film provided on the floating electrode;

a gate electrode provided on the second insulating film; and

a control circuit controlling its data memory state by injection of charges into the floating electrode,

the control circuit being configured to perform, to achieve a state in which charges having a first polarity are injected into the floating electrode:

providing a first potential difference between the semiconductor layer and the gate electrode to inject charges having the first polarity into the floating electrode; and

subsequently providing a second potential difference between the semiconductor layer and the gate electrode to inject charges having a second polarity opposite to the first polarity into the second insulating film.

22. A nonvolatile semiconductor memory device comprising:

a semiconductor layer;

a first insulating film provided on the semiconductor layer;

an electrode provided on the first insulating film;

a second insulating film having a characteristic to trap charge provided on the electrode side;

a gate electrode provided on the second insulating film; and

a control circuit,

the control circuit being configured to perform a first operation to provide a first potential difference between the gate electrode and the semiconductor layer, to perform a second operation to provide a second potential difference between the gate electrode and the semiconductor layer, and to perform a third operation to provide a third potential difference between the first gate electrode and the semiconductor layer,

the first potential difference having a first polarity,

the second potential difference having a second polarity opposite to the first polarity, and

the third potential difference having the first polarity.

23. The device according to claim 22, wherein the control circuit includes a voltage control circuit, a voltage generation circuit and a read circuit.

24. The device according to claim 22, wherein

in the first operation, the control circuit is configured to apply a first voltage to the gate electrode and to apply a second voltage lower than the first voltage to the semiconductor layer, and

in the second operation, the control circuit is configured to apply a third voltage to the gate electrode and to apply a fourth voltage higher than the third voltage to the semiconductor layer.

25. The device according to claim 22, further comprising a select transistor provided together with a memory cell and including a select gate, the memory cell including the electrode, the second insulating film and the gate electrode.

26. The device according to claim 25, wherein

in the first operation, the control circuit is configured to apply a first voltage to the gate electrode and to apply a second voltage lower than the first voltage to the semiconductor layer, and

in the second operation, the control circuit is configured to apply a third voltage to the gate electrode and to apply a fourth voltage higher than the third voltage to the semiconductor layer.

27. The device according to claim 26, wherein in the first operation, the control circuit is configured to apply a fifth voltage to the select gate, and the fifth voltage is lower than the first voltage and higher than the second voltage.

28. The device according to claim 27, wherein in the second operation, the control circuit is configured to turn the select gate off.

29. The device according to claim 22, wherein the electrode includes Si.

30. The device according to claim 29, wherein the second insulating film includes Hf and oxygen.

31. The device according to claim 22, wherein the electrode is based on nanocrystal.

32. The device according to claim 29, wherein the second insulating film includes silicon, nitrogen and oxygen.

33. The device according to claim 29, wherein the electrode has a two- or three-layer structure.

34. The device according to claim 22 wherein the control circuit is configured to perform the second operation after the first operation consecutively.

35. A nonvolatile semiconductor memory device comprising:

a semiconductor layer;

a first insulating film provided on the semiconductor layer;

an electrode provided on the first insulating film;

a second insulating film having a characteristic to trap charge provided on the electrode side;

a gate electrode provided on the second insulating film; and

a control circuit,

the control circuit being configured to perform a first operation to provide a first potential difference between the gate electrode and the semiconductor layer, and to perform a second operation to provide a second potential difference between the gate electrode and the semiconductor layer,

the first potential difference having a first polarity, and

the second potential difference having a second polarity opposite to the first polarity, wherein

in the first operation, the control circuit is configured to apply a first voltage to the gate electrode and to apply a second voltage lower than the first voltage to the semiconductor layer, and

in the second operation, the control circuit is configured to apply a third voltage to the gate electrode and to apply a fourth voltage higher than the third voltage to the semiconductor layer.

36. The device according to claim 35, wherein the control circuit include a voltage control circuit and a voltage generation circuit and a read circuit.

37. The device according to claim 35, further comprising a select transistor provided together with a memory cell and including a select gate, the memory cell including the electrode, the second insulating film and the gate electrode.

38. The device according to claim 35, wherein in the first operation, the control circuit is configured to apply a third voltage to the select gate, and the third voltage is lower than the first voltage and higher than the second voltage.

39. The device according to claim 38, wherein in the second operation, the control circuit is configured to turn the select gate off.

40. The device according to claim 35, wherein the electrode includes Si.

41. The device according to claim 40, wherein the second insulating film includes Hf and oxygen.

42. The device according to claim 35, wherein the electrode is based on nanocrystal.

43. The device according to claim 40, wherein the second insulating film includes silicon, nitride and oxygen.

44. The device according to claim 40, wherein the electrode has a two- or three-layer structure.

45. The device according to claim 35 wherein the control circuit is configured to perform the second operation after the first operation consecutively.

46. A nonvolatile semiconductor memory device comprising:

a semiconductor layer;

a first insulating film provided on the semiconductor layer;

an electrode provided on the first insulating film;

a second insulating film having a characteristic to trap charge provided on the electrode side;

a gate electrode provided on the second insulating film; and

a control circuit,

the control circuit being configured to perform a first operation to provide a first potential difference between the gate electrode and the semiconductor layer, to perform a second operation to provide a second potential difference between the gate electrode and the semiconductor layer, and to perform the second operation after the first operation consecutively,

the first potential difference having a first polarity, and

the second potential difference having a second polarity opposite to the first polarity.

47. The device according to claim 46, wherein the control circuit include a voltage control circuit and a voltage generation circuit and a read circuit.

48. The device according to claim 46, further comprising a select transistor provided together with a memory cell and including a select gate, the memory cell including the electrode, the second insulating film and the gate electrode.

49. The device according to claim 46, wherein in the first operation, the control circuit is configured to apply a third voltage to the select gate, and the third voltage is lower than the first voltage and higher than the second voltage.

50. The device according to claim 49, wherein in the second operation, the control circuit is configured to turn the select gate off.

51. The device according to claim 46, wherein the electrode includes Si.

52. The device according to claim 51, wherein the second insulating film includes Hf and oxygen.

53. The device according to claim 46, wherein the electrode is based on nanocrystal.

54. The device according to claim 51, wherein the second insulating film includes silicon, nitride and oxygen.

55. The device according to claim 51, wherein the electrode has a two- or three-layer structure.