memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes, a log2(N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offsets) to bits of the byte-bank with an address conversion operator, and an adder in operative communication with the address offset bus and the log2(N) bit address bus, the adder operative to add addresses of the byte-bank with the offset generated by the address conversion operator and output a result to the log2(N) bit address. A random access memory array may include a plurality of the byte-banks.
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7. A method comprising:
providing a random access memory array comprising a plurality of said byte-banks, wherein each byte-bank is organized in N rows and 8 columns, each byte-bank having a capacity of log2(N) bytes;
providing a log2(N) bit address bus operative to address said byte-bank;
generating address offsets to bits of said byte-bank with an address conversion operator; and
adding addresses of said byte-bank with the generated address offset and outputting a result to said log2(N) bit address.
1. memory apparatus comprising:
a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes;
a log2(N) bit address bus operative to address said byte-bank;
an address offset bus operative to generate address offsets to bits of said byte-bank with an address conversion operator; and
an adder in operative communication with said address offset bus and said log2(N) bit address bus, said adder operative to add addresses of said byte-bank with the address offset generated by said address conversion operator and output a result to said log2(N) bit address.
0. 14. An apparatus comprising:
a memory array comprising a plurality of byte banks, wherein individual ones of the plurality of byte banks have a capacity of a number of bytes; and
a plurality of row decoders, individual of the plurality of row decoders capable of being selectively coupled with the memory array, wherein individual ones of the row decoders are coupled to respective individual ones of the plurality of byte banks;
wherein when selectively coupled to the memory array the plurality of row decoders may be capable of providing nonaligned access to the memory array;
an address bus coupled to the plurality of byte banks, wherein the address bus has a width of a number of bits equal to the number of bytes, and wherein the address bus is configured to address the respective individual ones of the byte banks using the number of bits; and
a plurality of address offset buses, individual ones of the plurality of address offset buses associated with respective individual ones of the plurality of byte banks.
2. The memory apparatus according to
3. The memory apparatus according to
4. The memory apparatus according to
5. The memory apparatus according to
6. The memory apparatus according to
8. The method according to
9. The method according to
10. The method according to
11. The method according to
12. The method according to
13. The method according to
0. 15. The apparatus of claim 14, wherein the memory array comprises an SRAM memory array.
0. 16. The apparatus of claim 14, wherein individual ones of the plurality of address offset buses are 1-bit buses.
0. 17. The apparatus of claim 14, further comprising:
a plurality of adders, wherein individual ones of the plurality of adders are configured to receive a word address and a respective input from one of the plurality of address offset buses, wherein individual ones of the plurality of adders are configured to add the word address and the input received from one of the plurality of address offset buses, and wherein individual ones of the plurality of adders are configured to output an address to the address bus.
0. 18. The apparatus of claim 14, further comprising:
an address conversion operator coupled to the plurality of address offset buses and configured to generate address offsets.
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More than one reissue application has been filed for the reissue of U.S. Pat. No. 6,975,553 B2. The reissue applications for the reissue of U.S. Pat. No. 6,975,553 B2 are application Ser. No. 13/005,225 (the present application), and Ser. No. 11/956,301. Application Ser. No. 13/005,225 (the present application) is a divisional reissue of application Ser. No. 11/956,301 filed Dec. 13, 2007 (the parent reissue application—now abandoned) which is a reissue application of Ser. No. 10/816,849 filed Apr. 5, 2004, now U.S. Pat. No. 6,975,553 B2. This application is a reissue of U.S. Pat. No. 6,975,553 B2.
The present invention relates generally to methods and apparatus for operating memory devices, and particularly to methods and apparatus for organizing random access memories, e.g., SRAM arrays, with nonaligned access, wherein unambiguous access to the bits of the array may be obtained even if two or more column lines and two or more row lines are activated at the same time.
Random access memories, such as static random access memories (SRAMs) or dynamic random access memories (DRAMs), generally comprise a multiplicity of addresses for writing therein data. Data in the addresses may be accessed, for example, through data latches for performing operations, e.g., programming, on a memory cell array, e.g., a non-volatile memory cell array.
Reference is now made to
Access to the rows may be controlled by a row decoder 12, and access to the columns may be controlled by a column decoder 14. The row and column decoders 12 and 14 may convert 3-bit row addresses and 3-bit column addresses to a single row select and a single column select signal, respectively.
It is noted that the “memory word length” refers to the memory array row length in bits. The memory array capacity is defined by the number of memory rows. Each appropriate bit in every memory array row belongs to a memory array column.
The memory array 10 may be accessed with a byte-aligned access using an 8-bit resolution. For such an access, all column lines may be activated and one of the row lines may be activated, thereby selecting all the bits in that row. Thus, a 3-bit row address is sufficient for accessing the whole byte.
The traditional, prior art organization of an SRAM is fine for such byte-aligned accesses, wherein if all the column lines are activated only one row line is activated. There is no ambiguity of two different rows that are both selected.
However, the prior art memory array structure is not capable of performing a nonaligned memory access. A “nonaligned memory access” is defined as an access wherein at least two column lines and at least two row lines are activated at the same time. An example of a nonaligned memory access is a request to read the four most significant bits of the top byte and the four least significant bits of the byte below, in a single data transaction. Such an access is impossible with the memory array 10, because it requires activating a pair of row lines and all the column lines, which creates an ambiguity in the memory array electric scheme.
The present invention seeks to provide methods and apparatus for organizing random access memories, e.g., SRAM arrays, with nonaligned access (e.g., with a byte resolution), wherein unambiguous access to the bits of the array may be obtained even if two or more column lines and two or more row lines are activated at the same time, as is described more in detail hereinbelow.
There is thus provided in accordance with an embodiment of the present invention memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes, a log2(N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offsets) to bits of the byte-bank with an address conversion operator, and an adder in operative communication with the address offset bus and the log2(N) bit address bus, the adder operative to add addresses of the byte-bank with the offset generated by the address conversion operator and output a result to the log2(N) bit address. A random access memory array may include a plurality of the byte-banks.
In accordance with an embodiment of the present invention, for each byte-bank, the address conversion operator may convert an unaligned address on a byte resolution into a log2(N) address on a data word resolution. The address offset may include shifting the most significant byte from the least significant byte by a distance of 8 bytes.
There is also provided in accordance with an embodiment of the present invention a method including providing a random access memory array including a plurality of the byte-banks, wherein each byte-bank is organized in N rows and 8 columns, each byte-bank having a capacity of log2(N) bytes, providing a log2(N) bit address bus operative to address the byte-bank, generating address offsets to bits of the byte-bank with an address conversion operator, and adding addresses of the byte-bank with the generated address offset and outputting a result to the log2(N) bit address.
The method may include performing an unaligned memory access to the byte-banks. The unaligned memory access may include transforming a data word before a memory write or read operation and compensating for the data word rotation with the offsets.
The present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:
Reference is now made to
In the structure of memory array 20, for example, a whole 8-byte word may be accessed in a single data transaction. Referring to
The structure of
Thus, in general, the random access memory array of the present invention includes byte-banks organized in N rows and 8 columns, wherein each byte bank has capacity of log2(N) bytes and is addressed by a log2(N) bit address bus. In the above example, N=512 and each byte bank has capacity of 9 bytes and is addressed by a 9-bit address bus (log2(512)=9). If the memory partition distribution of
In accordance with an embodiment of the present invention, the memory partition distribution of
For correction of the data word contents rotation (shift), two data conversion operators may be introduced.
Reference is now made to
Reference is now made to
From the foregoing description of the data word rotation, it may be seen that if the least significant byte of the 64-bit data word is located in the byte-bank 1, 2, 3, etc., the most significant byte is then located in the bank 0, 1, 2, etc., respectively. That is, the most significant byte is shifted from the least significant byte by a distance of 8 bytes in the byte address resolution. In a nonaligned data access, this row offset may be manipulated by the structure of the memory array 20, as shown in
Reference is now made to
In general, for addressing 4 KB, 12 address bits are needed (212=4096). Among 12 bits of the non-aligned address, the 9-bit component for the aligned access may be extracted from the most significant bits of this address. This component can be used for simultaneous addressing of all byte-banks.
When an unaligned memory access takes place, the 64-bit data word location can be started anywhere in the byte-banks 1 to 7. The 64-bit data word location is defined by the location of its least significant byte and depends on the contents of the three least significant bits of the original 12-bit address. As mentioned hereinabove, a distance of 8 bytes separates the least significant byte of the 64-bit data word from the most significant byte in the byte address resolution. Thus, for the most significant byte or bytes of the unaligned 64-bit data word, the selected memory row is shifted downwards by one row with respect to the memory rows for the least significant byte or bytes in the byte-banks. Therefore, each byte-bank needs a one-bit row offset depending on the starting location of the unaligned 64-bit data word. Such one-bit row offsets may be generated by the address conversion operator shown in
Reference is now made to
It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. Rather the scope of the present invention includes both combinations and sub-combinations of the features described hereinabove as well as modifications and variations thereof which would occur to a person of skill in the art upon reading the foregoing description and which are not in the prior art.
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
6070003, | Nov 17 1989 | Texas Instruments Incorporated | System and method of memory access in apparatus having plural processors and plural memories |
6507534, | Feb 29 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Column decoder circuit for page reading of a semiconductor memory |
6571327, | Sep 03 1998 | CORAGE, LTD | Non-aligned double word access in word addressable memory |
6975553, | Apr 05 2004 | Intellectual Ventures I LLC | Nonaligned access to random access memory |
20030012066, | |||
20050219933, |
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