A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active. An adjustment unit provides a writing current to the cell, and increases the writing current according to the control signal until the comparing signal indicates that the memory cell is in a reset state.
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0. 18. A method, comprising:
increasing a writing current applied to a first memory cell of a non-volatile memory until a first sensing voltage is larger than or equal to a reference voltage;
identifying a magnitude of the writing current as a reference current magnitude;
determining that a second memory cell of the non-volatile memory is in a non-reset state by comparing a second sensing voltage and the reference voltage; and
providing the writing current with the reference current magnitude to the second memory cell in response to said determining.
0. 24. A circuit, comprising:
a sensing unit configured to identify a sensing voltage associated with a first memory cell of a non-volatile memory;
a writing current generator configured to increase a writing current applied to the first memory cell until the first sensing voltage is larger than or equal to a reference voltage, wherein a magnitude of the writing current is configured to be identified as a reference current magnitude; and
a comparator configured to compare a second sensing voltage and the reference voltage, wherein the writing current with the reference current magnitude is applied to a second memory cell of the non-volatile memory in response to determining that the second memory cell is in a non-reset state.
1. A verification circuit for a phase change memory array, comprising:
a sensing unit, sensing a first sensing voltage from a first memory cell of the phase change memory array according to an enable signal;
a comparator, generating a comparing signal according to the first sensing voltage and a reference voltage to indicate whether the first memory cell is in a reset state;
a control unit, generating a control signal according to the enable signal; an operating unit, generating a first signal according to the control signal to indicate whether the comparator is active; and
an adjusting unit, providing a writing current to the first memory cell and adjusting the writing current according to the control signal until the comparing signal indicates that the first memory cell is in a reset state.
15. A verification method for a phase change memory array, comprising:
providing a writing current to a first memory cell of the phase change memory array and gradually increasing the writing current until a first sensing voltage sensed from the first memory cell is larger than or equal to a reference voltage;
recording the current magnitude of the writing current as a reference current magnitude when the first sensing voltage is larger than or equal to a reference voltage;
reading a second memory cell of the phase change memory array to obtain a second sensing voltage;
determining whether the second memory cell is in a reset state by comparing the second sensing voltage and the reference voltage; and
providing the writing current with the reference current magnitude to the second memory cell to transform the second memory cell into a reset state when the second memory cell is in a non-reset state.
2. The verification circuit as claimed in
3. The verification circuit as claimed in
4. The verification circuit as claimed in
5. The verification circuit as claimed in
a first switch, having a first terminal coupled to the control unit and a second terminal coupled to the adjusting unit, wherein the first switch is controlled to transmit the control signal of the control unit to the adjusting unit according to the comparing signal; and
a second switch coupled between a specific voltage and the second terminal, having a control terminal for receiving the comparing signal.
6. The verification circuit as claimed in
a delay unit, delaying the first signal to generate a second signal;
a flip-flop, having a data input terminal coupled to the second terminal, a clock input terminal for receiving the second signal, and a data output terminal for providing a verification signal; and
a determining unit, providing the enable signal to the control unit.
7. The verification circuit as claimed in
a calculating unit, calculating the pulse number of the control signal to generate an adjusting signal with a plurality of bits; and
a writing current generator, generating the writing current which has a current magnitude corresponding to the adjusting signal, and wherein the current magnitude of the writing current is of reference current magnitude when the comparing signal indicates that the first memory cell is in a reset state.
8. The verification circuit as claimed in
a register, storing the reference current magnitude.
9. The verification circuit as claimed in
10. The verification circuit as claimed in
11. The verification circuit as claimed in
12. The verification circuit as claimed in
13. The verification circuit as claimed in
14. The verification circuit as claimed in
16. The verification method as claimed in
when the second sensing voltage corresponding to the reference current magnitude is smaller than the reference voltage, gradually increasing the writing current until the second sensing voltage corresponding to the writing current is larger than or equal to the reference voltage.
17. The verification method as claimed in
0. 19. The method of claim 18, wherein the non-volatile memory comprises a memory which has different resistances corresponding to at least two switchable states of the non-volatile memory.
0. 20. The method of claim 19, wherein the two switchable states comprise a crystalline state and an amorphous state indicative of stored data in the non-volatile memory.
0. 21. The method of claim 18, wherein the non-volatile memory comprises a phase change memory.
0. 22. The method of claim 18, further comprising determining that the first memory cell is in a reset state if the first sensing voltage is larger than or equal to the reference voltage, wherein said identifying comprises identifying the magnitude of the writing current in response to determining that the first memory cell is in the reset state.
0. 23. The method of claim 18, further comprising transforming the second memory cell into a reset state in response to providing the writing current with the reference current magnitude.
0. 25. The circuit of claim 24, wherein the non-volatile memory comprises a memory device which changes resistance according to a switched state of the non-volatile memory.
0. 26. The circuit of claim 25, wherein the switched state comprises a crystalline state or an amorphous state indicative of stored data in the non-volatile memory.
0. 27. The circuit of claim 24, wherein the non-volatile memory comprises a phase change memory.
0. 28. The circuit of claim 24, wherein the comparator is further configured to determine that the first memory cell is in a reset state if the first sensing voltage is larger than or equal to the reference voltage, and wherein the magnitude of the writing current is configured to be identified in response to determining that the first memory cell is in the reset state.
0. 29. The circuit of claim 24, wherein the second memory cell is configured to be transformed into a reset state in response to applying the writing current with the reference current magnitude.
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This Application is a reissue of U.S. patent application Ser. No. 12/485,720, filed Jun. 16, 2009, now U.S. Pat. No. 7,974,122, issued Jul. 5, 2011, which claims priority of Taiwan Patent Application No. 097151378, filed on Dec. 30, 2008, the entirety of which is are incorporated by reference herein.
1. Technical Field
The present disclosure relates to a verification circuit, and more particularly to a verification circuit for a phase change memory array.
2. Description of the Related Art
A Phase Change Memory (PCM) is a non-volatile memory with high speed, high capacity and low energy consumption, wherein a plurality of PCM cells of the PCM cell is formed by phase change material, such as chalcogenide etc. The phase change material can be switched between two states, a crystalline state and an amorphous state, with the application of heat, wherein the phase change material has different resistances corresponding to the crystalline and amorphous states respectively, and the resistances respectively represent different stored data.
In general, different writing currents are provided to heat a PCM cell to change its resistance, such that data can be stored into the PCM cell. Furthermore, for a PCM cell, it is necessary for a writing current to transform the PCM cell into a reset state. Therefore, a verification circuit for verifying a PCM array is desired, which is used to verify that the memory cells of the PCM array have been transformed from a non-reset state to a reset state.
Verification circuits and verification methods for a phase change memory array are provided. An exemplary embodiment of such a verification circuit for a phase change memory array comprises: a sensing unit, sensing a first sensing voltage from a first memory cell of the phase change memory array according to an enable signal; a comparator, generating a comparing signal according to the first sensing voltage and a reference voltage, so as to indicate whether the first memory cell is in a reset state; a control unit, generating a control signal according to the enable signal; an operating unit, generating a first signal according to the control signal, so as to indicate whether the comparator is active; and an adjusting unit, providing a writing current to the first memory cell and adjusting the writing current according to the control signal until the comparing signal indicates that the first memory cell is in a reset state.
Furthermore, an exemplary embodiment of a verification method for a phase change memory array is provided. A memory cell of the phase change memory array is read to obtain a sensing voltage. The sensing voltage is compared with a reference voltage. When the sensing voltage is smaller than the reference voltage, a writing current is provided to the memory cell and the writing current is gradually increased until the sensing voltage corresponding to the writing current is larger than or equal to the reference voltage.
Moreover, another exemplary embodiment of a verification method for a phase change memory array is provided. A writing current is provided to a first memory cell of the phase change memory array and the writing current is gradually increased until a first sensing voltage sensed from the first memory cell is larger than or equal to a reference voltage. The current magnitude of the writing current is recorded as a reference current magnitude when the first sensing voltage is larger than or equal to a reference voltage. A second memory cell of the phase change memory array is read to obtain a second sensing voltage. It is determined whether the second memory cell is in a reset state by comparing the second sensing voltage and the reference voltage. The writing current with the reference current magnitude is provided to the second memory cell to transform the second memory cell into a reset state when the second memory cell is in a non-reset state. A detailed description is given in the following exemplary embodiments with reference to the accompanying drawings.
The following description is made for the purpose of illustrating the general principles of the disclosure and should not be taken in a limiting sense. The scope of the embodiments is best determined by reference to the appended claims and their equivalents.
When receiving an enable signal SEN provided by the determining unit 128, the sensing unit 112 may read a memory cell of the PCM array 150 to sense a resistance Rcell of the memory cell, so as to obtain a sensing voltage Vcell corresponding to the resistance Rcell. Next, the comparator 114 may compare the sensing voltage Vcell with a reference voltage Vref, so as to generate a comparing signal Sc to indicate the state of the read memory cell. For example, the comparing signal Sc indicates that the read memory cell is in a non-reset state when the sensing voltage Vcell is smaller than the reference voltage Vref, and the comparing signal Sc indicates that the read memory cell has be transformed into a reset state when the sensing voltage Vcell is larger than or equal to the reference voltage Vref.
Furthermore, the determining unit 128 also provides the enable signal SEN to the control unit 116 to generate the control signal Sctrl. Next, the operating unit 118 generates the signal S1 according to the control signal Sctrl, so as to control the comparator 114 to operate or not. Next, the comparing signal Sc may control the switches 120 and 122 to turn on or off. The switch 120 is coupled between the control unit 116 and the adjusting unit 130 and the switch 122 is coupled between a voltage VDD and the switch 120, wherein the switches 120 and 122 are controlled by the comparing signal Sc. Therefore, the comparing signal Sc may control the switches 120 and 122 to change the control signal Sctrl into a signal Sclk and provide the signal Sclk to the adjusting unit 130 and the flip-flop 126. Referring to
Referring to
Referring to
While the disclosure has been described by way of example and in terms of embodiments, it is to be understood that the disclosure is not limited thereto. It will be apparent to those skilled in the art that various modifications and variations can be made in the disclosure. It is intended that the embodiments described be considered as exemplary only, with the true scope of the embodiments being indicated by the following claims and their equivalents.
Lin, Wen-Pin, Sheu, Shyh-Shyuan, Chiang, Pei-Chia
Patent | Priority | Assignee | Title |
8982634, | Jul 11 2012 | eMemory Technology Inc. | Flash memory |
Patent | Priority | Assignee | Title |
4974205, | Oct 24 1988 | Fujitsu Limited | Josephson memory and read/write circuit |
5694363, | Apr 28 1995 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Reading circuit for memory cell devices having a low supply voltage |
5787042, | Mar 18 1997 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for reading out a programmable resistor memory |
5883837, | Sep 30 1996 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Reading circuit for semiconductor memory cells |
6487113, | Jun 29 2001 | OVONYX MEMORY TECHNOLOGY, LLC | Programming a phase-change memory with slow quench time |
7054213, | Dec 28 2000 | STMicroelectronics, Inc. | Method and circuit for determining sense amplifier sensitivity |
7110286, | Feb 04 2004 | Samsung Electronics Co., Ltd. | Phase-change memory device and method of writing a phase-change memory device |
7154774, | Mar 30 2005 | OVONYX MEMORY TECHNOLOGY, LLC | Detecting switching of access elements of phase change memory cells |
7190607, | Jun 19 2004 | Samsung Electronics Co., Ltd. | Phase-change memory element driver circuits using measurement to control current and methods of controlling drive current of phase-change memory elements using measurement |
7259982, | Jan 05 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Reading phase change memories to reduce read disturbs |
7324371, | Dec 27 2001 | OVONYX MEMORY TECHNOLOGY, LLC | Method of writing to a phase change memory device |
7359231, | Jun 30 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Providing current for phase change memories |
7388775, | Mar 30 2005 | OVONYX MEMORY TECHNOLOGY, LLC | Detecting switching of access elements of phase change memory cells |
7423897, | Oct 01 2004 | OVONYX MEMORY TECHNOLOGY, LLC | Method of operating a programmable resistance memory array |
7447092, | Aug 22 2003 | Samsung Electronics Co., Ltd. | Write driver circuit for controlling a write current applied to a phase change memory based on an ambient temperature |
7457151, | Jul 13 2005 | Samsung Electronics Co., Ltd. | Phase change random access memory (PRAM) device having variable drive voltages |
7515460, | Jan 25 2005 | TAHOE RESEARCH, LTD | Multilevel programming of phase change memory cells |
7521372, | Dec 29 2006 | Gula Consulting Limited Liability Company | Method of fabrication of phase-change memory |
7535747, | Sep 04 2006 | Samsung Electronics Co., Ltd. | Phase change random access memory and related methods of operation |
7542356, | Nov 01 2006 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method for reducing cell activation during write operations |
7566895, | Nov 24 2006 | Gula Consulting Limited Liability Company | Phase change memory device and method for fabricating the same |
7609544, | Nov 26 2004 | NEC ELECTRRONICS CORPORATION; Renesas Electronics Corporation | Programmable semiconductor memory device |
7639522, | Nov 29 2006 | Samsung Electronics Co., Ltd. | Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device |
7643373, | Jan 12 2007 | Gula Consulting Limited Liability Company | Driving method and system for a phase change memory |
7646627, | May 18 2006 | Renesas Electronics Corporation | Magnetic random access memory having improved read disturb suppression and thermal disturbance resistance |
7670869, | Feb 16 2007 | Gula Consulting Limited Liability Company | Semiconductor device and fabrications thereof |
7672176, | Jun 13 2007 | HIGGS OPL CAPITAL LLC | Writing circuit for a phase change memory |
7678606, | Sep 04 2007 | HIGGS OPL CAPITAL LLC | Phase change memory device and fabrication method thereof |
7679163, | May 14 2007 | Gula Consulting Limited Liability Company | Phase-change memory element |
7745811, | Aug 16 2006 | HIGGS OPL CAPITAL LLC | Phase change memory devices and methods for fabricating the same |
7773408, | Nov 30 2005 | Renesas Electronics Corporation | Nonvolatile memory device |
7773409, | Mar 08 2007 | Gula Consulting Limited Liability Company | Writing method and system for a phase change memory |
7773410, | Nov 08 2007 | Gula Consulting Limited Liability Company | Writing system and method for phase change memory |
7773411, | Dec 06 2007 | Gula Consulting Limited Liability Company | Phase change memory and control method thereof |
7787281, | Jul 05 2007 | Gula Consulting Limited Liability Company | Writing circuit for a phase change memory |
7796454, | Jun 25 2007 | Gula Consulting Limited Liability Company | Sensing circuit of a phase change memory and sensing method thereof |
7796455, | Sep 21 2007 | Gula Consulting Limited Liability Company | Device controlling phase change storage element and method thereof |
7858961, | Jun 03 2008 | Gula Consulting Limited Liability Company | Phase change memory devices and methods for fabricating the same |
7885109, | Dec 03 2007 | HIGGS OPL CAPITAL LLC | Memory and method for dissipation caused by current leakage |
7889547, | Jun 02 2008 | Gula Consulting Limited Liability Company | Memory and writing method thereof |
7919768, | Jul 11 2008 | Gula Consulting Limited Liability Company | Phase-change memory element |
7923714, | May 31 2007 | Gula Consulting Limited Liability Company | Phase change memory cell structures and methods for manufacturing the same |
7933147, | Jun 25 2007 | Gula Consulting Limited Liability Company | Sensing circuit of a phase change memory and sensing method thereof |
7964862, | Apr 24 2007 | Gula Consulting Limited Liability Company | Phase change memory devices and methods for manufacturing the same |
7974122, | Dec 30 2008 | Gula Consulting Limited Liability Company | Verification circuits and methods for phase change memory array |
8199561, | Dec 31 2008 | Gula Consulting Limited Liability Company | Phase change memory |
20050068804, | |||
20060221678, | |||
20070002654, | |||
20090189142, | |||
20090296458, | |||
20100117050, | |||
20100165723, | |||
20120230099, | |||
CN101136452, | |||
CN101202326, | |||
CN101211959, | |||
CN101266834, | |||
CN101271862, | |||
CN101276643, | |||
CN101308903, | |||
CN101312230, | |||
CN101330126, | |||
CN101335045, | |||
CN101369450, | |||
CN101383397, | |||
CN101414480, | |||
CN101452743, | |||
CN101471130, | |||
CN101504863, | |||
CN101504968, | |||
CN101599301, | |||
CN101626060, | |||
CN101740716, | |||
CN101814323, | |||
CN101819816, | |||
CN1455412, | |||
JP2002246561, | |||
JP2004274055, | |||
JP2005525690, | |||
JP2006108645, | |||
JP2006295168, | |||
JP2006510220, | |||
JP2007103945, | |||
JP2007184591, | |||
JP2008171541, | |||
JP2008193071, | |||
JP2008226427, | |||
JP2008283163, | |||
TW200828506, | |||
TW200845443, | |||
TW200849278, | |||
TW200901196, | |||
TW200908294, | |||
TW200913252, | |||
TW200915318, | |||
TW200921682, | |||
TW200926186, | |||
TW200937693, | |||
TW200951981, | |||
TW200952169, | |||
TW201003851, | |||
TW201019467, | |||
TW201025326, | |||
TW201025573, | |||
TW305042, | |||
TW318470, | |||
TW320180, | |||
TW324823, | |||
TW326917, | |||
TW328816, | |||
TW330846, | |||
TW334604, | |||
TW336925, | |||
TW342022, | |||
TW343642, |
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