MPGA products based on a prototype FPGA

Abstract

A smaller mask programmable gate array (mpga) device derived from a larger field programmable gate array (fpga), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the fpga; and input/output pads matching a subset of the input/output pads of the fpga; wherein, a design that is mapped to said smaller region of the fpga device using said subset of input/output pads by a user programmable means can be identically mapped to the mpga by a hard-wire circuit. Such a gate array further comprises a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the fpga; and a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the fpga.

Description

This application is a continuation-in-part of application Ser. No. 11/645,313 filed Dec. 26, 2006,
The truth table logic states are represented by S0, S1, S2 and S3. The realization is done through six inverters collectively designated 250 and eight pass transistors collectively designated 260. Logic states are stored in 4 programmable registers.

FIG. 12 shows a logic tree constructed with five 2-input truth table logic blocks 320-328 to perform a full four input truth table. A four input truth table has 16 possible logic states S0, S1, . . . , S15. As the number of inputs grows to N, this logic tree construction requires 2^N logic states, and 2^(N−1) branches in the logic tree. For large N values, a full truth table realization is less efficient compared to a partial product term AND-OR array realization.

In another embodiment, the programmable logic block can be a programmable microprocessor block. The microprocessor can be selected from third party IP cores such as: 8051, Z80, 68000, MIPS, ARM, and PowerPC. These microprocessor architectures include superscalar, Fine Grain Multi-Threading (FGMT) and Simultaneous Multi-Threading (SMT) that support Application Specific Packet Processing (ASPP) routines. To handle Programmable Network Interface (PNI) the processor can contain hardware and software configurability. Hardware upgradeability can be greatly enhanced in microprocessors embedded in PLD's by making use of the available logic content of the PLD device. Programmable features can include varying processor speed, cache memory system and processor configuration, enhancing the degree of Instruction Level Parallelism (ILP), enhancing Thread level parallelism (TLP). Such enhancements allow the user to optimize the core processor to their specific application. Cache parameters such as access latency, memory bandwidth, interleaving and partitioning are also programmable to further optimize processor performance and minimize cache hit miss rates. Additionally, the processor block can be a Very Long Instruction Word (VLIW) processor to handle multimedia applications. The processor block can include a cache controller to implement a large capacity cache as compared with an internal cache.

While a PLD can be configured to do DSP functions, the programmable logic block can also contain a digital signal processor (DSP), which is a special purpose processor designed to optimize performance for very high speed digital signal processing encountered in wireless and fiber-optic networks. The DSP applications can include programmable content for cache partitioning, digital filters, image processing and speech recognition blocks. These real-time DSP applications contain high interrupt rates and intensive numeric computations best handled by hardware blocks. In addition, the applications tend to be intensive in memory access operations, which may require the input and output of large quantities of data. The DSP cache memory may be configured to have a “Harvard” architecture with separate, independent program and data memories so that the two memories may be accessed simultaneously. This architecture permits an instruction and an operand to be fetched from memory in a single clock cycle. A modified Harvard architecture utilizes the program memory for storing both instructions and operands to achieve full memory utilization. The program and data memories are often interconnected with the core processor by separate program and data buses. When both instructions and operands (data) are stored in a single program memory, conflicts may arise in fetching data with the next instruction. Such conflicts have been resolved in prior art for DSPs by providing an instruction cache to store conflicting instructions for subsequent program execution.

In yet another embodiment, programmable logic block can contain software programmability. These software functions are executed in DSP, ARM, or MIPS type inserted IP cores, or an external host CPU. Accelerators connected by a configurable SRAM switching matrix enhance the computation power of the processors. The microprocessor has local permanent SRAM memory to swap, read, and write data. The switch matrix is pre-designed to offer both hard-wire and programmable options in the final ASIC. In this situation, the circuit block 104 can be a functional block that performs well-defined, commonly-needed function, such as special D/A or A/D converter, standard bus interface, or such block that implements special algorithms such as MPEG decode. The special algorithms implemented can be hardware versions of software. For example, algorithms relating to digital radio or cellular telephone such as WCDMA signal processing can be implemented by the functional block. Other functional blocks include PCI, mini-PCI, USB, UART blocks that can be configured by specifying the SRAM logic blocks.

In yet another embodiment, the circuit block 104 can be memory such as a register file, cache memory, static memory, or dynamic memory. A register file is an array of latches that operate at high speed. This register length counter may be programmable by the user. A cache memory has a high access throughput, short access latency and a smaller capacity as compared with main memory. The cache memory may be programmable to partition between the different requirements of the system design. One such need is the division between L1 and L2 cache requirements for networking applications. The memory can also be static random access memory or (SRAM) device with an array of single port, or multi-port addressable memory cells. Each cell includes a four transistor flip-flop and access transistors that are coupled to input/output nodes of the flip-flop. Data is written to the memory cell by applying a high or low logic level to one of the input/output nodes of the flip-flop through one of the access transistors. When the logic level is removed from the access transistor, the flip-flop retains this logic level at the input/output node. Data is read out from the flip-flop by turning on the access transistor. The memory can also be dynamic random access memory (DRAM). Generally, a DRAM cell consists of one transistor and a capacitor. A word line turns on/off the transistor at the time of reading/writing data stored in the capacitor, and the bit line is a data input/output path. DRAM data is destroyed during read, and refresh circuitry is used to continually refresh the data. Due to the low component count per bit, a high density memory device is achieved.

In another embodiment, the circuit block 104 can be an intellectual property (“IP”) core which is reusable for licensing from other companies or which is taken from the same/previous design. In core-based design, individual cores may be developed and verified independently as stand-alone modules, particularly when IP core is licensed from external design source. These functions are provided to the user as IP blocks as special hardware blocks or pre-configured programmable logic blocks. The IP blocks connect via a programmable switching matrix to each other and other programmable logic. The hardware logic block insertion to any position in a logic sequence is done through the configurable logic matrix. These hardware logic blocks offer a significant gate count reduction on high gate count frequently used logic functions, and the user does not require generic “logic element” customization. In both cases, the user saves simulation time, minimize logic gate count, improve performance, reduce power consumption and reduce product cost with pre-defined IP blocks. The switch matrix is replaced by hardwires in the final ASIC.

The circuit blocks 104 can also be an array of programmable analog blocks. In one embodiment, the analog blocks include programmable PLL, DLL, ADC and DAC. In another embodiment, each block contains an operational amplifier, multiple programmable capacitors, and switching arrangements for connecting the capacitors in such as a way as to perform the desired function. Switched capacitor filters can also be used to achieve an accurate filter specification through a ratio of capacitors and an accurate control of the frequency of a sampling clock. Multiple PLL's can be programmed to run at different frequencies on the same chip to facilitate SoC applications requiring more than one clock frequency.

The circuit blocks 104 also contain data fetch and data write circuitry required to configure the configuration circuits 108. This operation may be executed by a host CPU residing in the system, or the PLD device itself. During power up, these circuits initialize and read the configuration data from an outside source, either in serial mode or in parallel mode. The data is stored in a predefined word length locally and written to the configurability allocation. The programmed configuration data is verified against the locally stored data and a programming error flag is generated if there is a mismatch. These circuits are redundant in the conversion of the PLD to an ASIC. However, these circuits are used in both FPGA and ASIC for test purposes, and has no cost penalty. A pin-out option has a “disable” feature to disconnect them for the customer use in the FPGA and ASIC.

Configuration circuits 108 provide active circuit control over digital circuits 104. One embodiment of the configuration circuit includes an array of memory elements. The user configuration of this memory amounts to a specific bitmap of the programmable memory in a software representation.

Suitable memory elements include volatile or non volatile memory elements. In non-volatile memory (NVM) based products, configurable data is held in one of metal link fuse, anti-fuse, EPROM, Flash, EEPROM memory element, or ferro-electric elements. The first two are one time programmable (OTP), while the last four can be programmed multiple times. As EPROM's require UV light to erase data, only Flash & EEPROM's lend to in-system programmability (ISP). In volatile products, the configurable data storage can be SRAM cells or DRAM cells. With DRAM cells, the data requires constant refresh to prevent losses from leakages. Additionally, one or more redundant memory cells controlling the same circuit block can be used to enhance device yield.

The components of the memory element array can be a resistor, capacitor, transistor or a diode. In another embodiment of the configuration circuit, a memory element can be formed using thin film deposition. The memory element can be a thin film resistor, thin film capacitor, thin film transistor (TFT) or a thin film diode or a group of thin film devices connected to form an SRAM cell.

This discussion is mostly on SRAM elements and can easily extend to include all other programmable elements. In all cases, the design needs to adhere to rules that allow programmable module elimination, with no changes to the base die, a concept not used in PLD, FPGA, Gate Array and ASIC products today.

An exemplary 6T SRAM cell, shown in FIG. 13, needs no high voltage capability, nor added process complexity. The cell of FIG. 13 has two back-to-back inverters 350-352 whose access is controlled by pass transistors 354-356. In addition, R-load & Thin Film Transistor (TFT) load PMOS based SRAM cells can be used for PLDs and FPGAs. To achieve zero stand-by power by eliminating sensing circuitry, and reduce memory element count for low input functions, these SRAM cells are embedded in truth table logic (also called Look-Up-Table) based architectures.

Pass gate transistor 360 logic controlled by SRAM is shown in FIG. 14. In this embodiment, the memory cell (such as the cell of FIG. 13) drives the pass transistor 360 to e affect an outcome. A 5×6-switch point matrix 370 controlled by 30-SRAM cells coupled to 30-NMOS pass gates is shown in FIG. 15. FIG. 16 shows the NMOS pass gate 360 logic controlled by the SRAM in FIG. 14 converted to hard-wire logic. A contact 362, connected to Vcc (logic 1) or Vss (logic 0) depending on the SRAM logic content, replace the SRAM cell. The SRAM logic mapping to hard wire connections are automatic and done by a software program that is verifiable against the bit-map.

Similarly, FIG. 17 shows the 5×6-switch point matrix 370 hard-wired by replacing the SRAM bits that control NMOS gates with hard-wires to Vcc or Vss. In FIG. 17, the bubble may represent either SRAM or hard-wire Vcc or Vss control on NMOS pass gates. In the case of Fuse or Antifuse arrays, contact or no contact between the two metal lines in FIG. 15 directly replaces the programmable element and there is no NMOS pass-gate needed.

The P-Term logic builds the core of PLD's and complex PLD's (CPLD's) that use AND-OR blocks 202-204 (or equivalent NAND-NOR type logic functions) as shown in the block diagram of FIG. 5 and one expansion is shown in FIG. 6 with and gates 210 and or gates 212. Gate implementation of two inputs (I1, I2) and two P-terms (P1, P2) NAND function can be single poly EEPROM bits as shown in FIG. 10. The dotted circle contains the charge trapping floating gate, the programming select transistor, tunneling diode, a control gate capacitor and programming access nodes. The SRAM cell replaces that entire circle in this invention as detailed next. The SRAM NAND-NOR array (also AND-OR array) replacement has not been realized in prior art as SRAM cells require Nwell & Pwell regions that consume large silicon area to prevent latch-up. The SRAM in TFT do not have well related constraints as NMOS and PMOS bodies are isolated from each other. Keeping the two pass gates in silicon layers and moving SRAM to TFT layers allow P-Term logic implementation with SRAM cells and subsequent replacement with hard-wires. In TFT SRAM conversion to final ASIC, the bubble on NMOS gate becomes a hard-wire connection to Vcc or Vss.

The length of input and output wires, and the drive on NMOS pass gates and logic gate delays determine the overall PLD delay timing, independent of the SRAM cell parameters. By moving SRAM cell to TFT upper layers, the chip X, Y dimensions are reduced over 20% to 50% compared to traditional SRAM FPGA's, providing a faster logic evaluation time. In addition, removal of SRAM cell later does not alter lateral wire length, wire loading and NMOS pass gate characteristic. The vertical dimension change in eliminating the memory module is negligible compared to the lateral dimension of the ASIC, and has no impact on timing. This allows maintaining identical timing between the FPGA and ASIC implementations with and without the SRAM cells. The final ASIC with smaller die size and no SRAM elements have superior reliability, similar to an ASIC, leading to lower board level burn-in and field failures compared to PLD's and FPGA's in use today.

Next, the wiring and/or routing circuit 112 is discussed. The wiring and/or routing circuit connects each logic block to each other logic block. The wiring/routing circuit allows a high degree of routing flexibility per silicon area consumed and uniformly fast propagation of signals, including high-fanout signals, throughout the device. The wiring module may contain one or many levels of metal interconnects.

One embodiment of a switch matrix is a 6×5 programmable switch-matrix with 30 SRAM bits (or 30 Anti-fuses, or 30 fuses), shown in FIG. 15. The box in FIG. 14 contains the SRAM cell shown inside dotted box of FIG. 14, where the pass gate makes the connection between the two wires, and the SRAM bit holds the configuration data. In this configuration, the wire connection in circuit 112 occurs via a pass transistor located in circuit 104 controlled by an SRAM cell in circuit 108. During power-up, a permanent non-volatile memory block located in the system, loads the correct configuration data into SRAM cells. In Fuse or Anti-fuse applications, the box simply represents the programmable element in circuit 108 between the two wires in circuit 112. During the ASIC conversion this link is replaced with an open or short between the wires.

Another embodiment provides short interconnect segments that could be joined to each other and to input and output terminals of the logic blocks at programmable interconnection points. In another embodiment, direct connections to adjacent logic blocks can be used to increase speed. For global signals that traverse long distances, longer lines are used. Segmented interconnect structures with routing lines of varied lengths can be used. In yet other embodiments, a hierarchical interconnect structure provides lines of short lengths connectable at boundaries to lines of longer lengths extending between the boundaries, and larger boundaries with lines of even longer length extending between those boundaries. The routing circuit can connect adjacent logic blocks in two different hierarchical blocks differently than adjacent logic blocks in the same hierarchical block. Alternatively, a tile-based interconnect structure can be used where lines of varying lengths in which each tile in a rectangular array may be identical to each other tile. In yet another implementation, the interconnect lines can be separated from the logic block inputs by way of a routing matrix, which gives each interconnect line more flexible access to the logic block inputs. In another embodiment, the interconnect routing is driven by programmable buffers. Long wire lengths can be sub-divided into smaller length segments with smaller buffers to achieve a net reduction in the overall wire delay, and to obtain predictable timing in the logic routing of the PLD.

FIG. 18A shows a first embodiment of an FPGA constructed as a regular 2D FPGA or a modular 3D FPGA. It may have configuration circuits in the same module layers as the transistors as in conventional FPGAs. It may have configuration circuits in a second module layer positioned above a first module layer that comprises logic circuits as presented in FIG. 1 thru FIG. 4. The FPGA has a core region 1801. The core region comprises programmable logic blocks and programmable interconnects. It further comprises user memory such as single-port or dual-port memory. It further comprises IP blocks such as microprocessor cores, DSP cores, analog cores and other circuits typically found in ICs. It further comprises registers, storage devices, clocks, PLLs, DLLs and control circuits. The core region 1801 interfaces with input/output pad regions 1811. These pad structures may be arranged around the perimeter as shown in FIG. 18A. In that, I/O structures 1811_A1-1811_G1 are left perimeter structures, 1811_A2-1811_G2 are bottom perimeter structures, 1811_A3-1811_G3 are right perimeter structures, and 1811_A4-1811_G4 are top perimeter structures. These pad structures may be arranged in any other method that is found in ICs, such as two sides of the core or distributed in an array through the core. Configuration circuits provide access for a user to program the functionality and routing of the FPGA to achieve a desirable functionality and performance. Configuration circuits further provide programmable interface of I/O pads to inputs of logic blocks and outputs of logic blocks in the FPGA core.

The FPGA in FIG. 18A further comprises smaller regions within the core such as 1802 and 1803. Region 1802 comprises the entire area inside the shaded region including region 1803. Therefore the resource content of region 1803 is the least, 1802 is greater than in 1803, and 1801 has the most. Each region comprises a subset of resources found in the core region 1801. Thus a smaller design that requires fewer resources may be placed inside region 1802, or even 1803. A software tool is able to determine the resource content, and choose an appropriate region to place and route the design. The region 1802, which is smaller than region 1801, interfaces with a subset of I/O structures 1811; the subset I/O structures also labeled 1811 in FIG. 18A. For region 1802, I/O structures 1811_B1-1811_F1 are left perimeter structures, 1811_B2-1811_F2 are bottom perimeter structures, 1811_B3-1811_F3 are right perimeter structures, and 1811_B4-1811_F4 are top perimeter structures. Power and ground pad structures are arranged in such a way, they are common to all regions. A pad structure is assumed to include buffer circuits, bond pad structures, ESD structures, registers, control circuits and other circuits found in ICs. In FIG. 18A, unlike for region 1801 wherein the I/O structures were adjacent to the perimeter of the region, for region 1802, the IO structures are distanced by circuits contained in region 1801 from the perimeter of 1802. Registers 1821 are provided in the FPGA hardware such that a software tool is able to automatically recognize the region boundaries not adjacent to I/O structures; insert a register and couple either logic input or logic output to the register output or input respectively first; then couple the register input or output to corresponding I/O structure as shown. Register 1821_B2 couples to I/O structure 1811_B2. Similarly, the region 1803, which is smaller than region 1802, interfaces with a subset of I/O structures 1811; the subset I/O structures also labeled 1811 in FIG. 18A. For region 1803, I/O structures 1811_C1-1811_E1 are left perimeter structures, 1811_C2-1811_E2 are bottom perimeter structures, 1811_C3-1811_E3 are right perimeter structures, and 1811_C4-1811_E4 are top perimeter structures. Power and ground pad structures are arranged in such a way, they are common to all regions. For region 1803, the 10 structures are distanced by circuits contained in region 1801 and in 1802 from the perimeter of 1803. Registers 1831 are provided in the FPGA hardware such that a software tool is able to automatically recognize the region boundaries not adjacent to I/O structures; insert a register and couple either logic input or logic output to the register output or input respectively first; then couple the register input or output to corresponding I/O structure as shown. Register 1831_C2 couples to I/O structure 1811_C2. It is understood that the FPGA in FIG. 18A comprises more than the few pads shown for illustrative purposes, and region 1803 may comprise hundreds of I/O structures.

FIGS. 18B, 18C and 18D show three MPGA devices constructed with the identical resources found in regions 1801, 1802 and 1803 respectively. A first module layer comprising transistors of region 1802 is substantially identically duplicated in the core region of FIG. 18C. A second module layer comprising a plurality of interconnects, positioned above the first module layer is also substantially identically duplicated in FIG. 18C. The subset of I/O regions common to region 1802 in FIG. 18A is also duplicated in FIG. 18C. In one embodiment, registers 1821 are specially placed in FIG. 18A, and those are not duplicated in FIG. 18C; instead logic input or output is directly coupled to the corresponding I/O structure. The software tool is able to identify the timing difference in the case of having a register in the FPGA to having no-register in the MPGA and use the appropriate delay numbers to calculate signal delays in the MPGA. As seen to one of ordinary skill, when the transistor layouts and metal interconnects layouts are substantially identical between regions 1802 in FIG. 18A, and region 1802 in FIG. 18C; the logic placement is identical and logical net connects is identical and the timing delays are also identical within the region 1802 in both devices. Only input/output delays are different, but the difference is pre-characterized and known such that the software tool is able to provide an accurate design conversion from the FPGA to the cheaper and economical smaller MPGA. One of ordinary skill may appreciate that a design placed and routed in the region 1803 within FPGA in FIG. 18A, can be identically placed and routed in MPGA shown in FIG. 18D; and a design placed and routed in the region 1801 within FPGA in FIG. 18A, can be identically placed and routed in MPGA shown in FIG. 18B. It can also be seen the subset of I/O pad structures for the region 1803 in FIG. 18A is matched to I/O structures in MPGA of FIG. 18D without the need to duplicate registers 1831 of FIG. 18A in the MPGA of FIG. 18D.

The arrangement of regions 1801-1803 is not limited to concentric regions, or to only two regions. It is conceivable that many regions may exist within the MPGA, each region uniquely mapping to an MPGA of equal resources and I/O density. A second embodiment of an FPGA is shown in FIG. 19A, which further provides the ability to port identically mapped designs to MPGAs shown in FIGS. 19B, 19C and 19D. The methodology to map designs is identical to that described for FIG. 18, and not repeated. The difference between FIG. 18A and FIG. 19A is in the manner in which regions 1901, 1902 and 1903 are defined. All three regions now contain two edges of the die, thus sharing common pads 1911_A1-1911_C1 and 1911_A4-1911_C4. These I/O structures do not require special registers to interface with circuit blocks within regions 1901-1903 regardless of the region chosen for the placement. However, regions 1902 and 1903 comprise at least two region boundaries that do not coincide with the I/O boundary. Such regional boundaries are provided with registers (registers 1921 for region 1902, and registers 1931 for region 1903) similar to that in FIG. 18A for the software tool to pick when coupling to I/O structures 1911_A2-1911_C2 and 1911_A3-1911_C3 is required.

An integrated circuit design platform, comprising: a field programmable gate array (FPGA) prototype device in FIG. 18A comprised of: a circuit layout (in region 1801) comprising a plurality of field programmable logic blocks and a plurality of layers of field programmable interconnects; and a set of input/output pad structures 1811; and a first region 1802 within the circuit layout, said region having registers 1821 at one or more boundaries of the region, a said register capable of coupling to a said input/output pad structure 1811; and a first metal programmable gate array (first MPGA FIG. 18C) production device comprised of: an substantially identical layout of programmable logic blocks in region 1902 as in the first region 1802 of the FPGA FIG. 18A; and a substantially identical layout of one or more layers of programmable interconnects as in the first region 1802 of the FPGA; wherein, a design mapped into the first region 1802 of the FPGA FIG. 18A is identically mapped to the first MPGA of FIG. 19C.

The design platform, wherein the FPGA in FIG. 18A comprises a configuration circuit to field program the programmable logic blocks and programmable interconnects; and the logic blocks are formed on a first module layer and the configuration circuit is formed on a second module layer positioned substantially above the first module layer. Thus when the configuration circuits are converted from user programmable circuits to mask-programmable circuits in the MPGA, the underlying logic placement and the interconnects are substantially kept identical between the two devices, enabling a very easy and simple design conversion from the expensive FPGA to cheaper and better MPGA.

An integrated circuit design platform, comprising: a prototype field programmable (FPGA) device in FIG. 19A comprising a layout of electronic circuits (in region 1901) and input/output pads 1911; and a production mask programmable (MPGA) device in FIG. 19C comprising: a layout of electronic circuits (in region 1902) substantially identical to a region 1802 within the prototype FPGA in FIG. 19A; and a subset of input/output pads 1911 as within the prototype FPGA 1811; wherein, a design placed and routed within the region 1802 of the prototype FPGA using the subset of input/output pads 1811 as in the production MPGA 1911 is identically placed and routed in the production MPGA in FIG. 19C.

A smaller mask programmable gate array (MPGA) device in FIG. 19D derived from a larger field programmable gate array (FPGA) device in FIG. 19A, comprising: a layout of transistors and a plurality of interconnect layers (in region 1903 of FIG. 19D) substantially identical to a region (1903 in FIG. 19A) of the FPGA; and input/output pads (1911 in FIG. 19D) matching a subset of the input/output pads of the FPGA (1911 in FIG. 19A); wherein, a design that is mapped to said region of the FPGA (1901 in FIG. 19A) device using said subset of input/output pads (1911 in FIG. 19A) by a user programmable means can be identically mapped to the MPGA (in FIG. 19D) by a hard-wire circuit.

A method of mapping a design to a smaller region of an FPGA (1802 in FIG. 18A), comprising: inserting a register 1821 at a boundary of a smaller region 1802 of the FPGA during logic placement; and coupling a logic block (within region 1802) to said register 1821, and coupling said register 1821 to an input/output pad 1811 located at the edge of the FPGA die. The method further comprised of identically mapping the same design to an MPGA (in FIG. 18C) comprising substantially identical transistor layout of said region 1802 of the FPGA, comprising: coupling said logic block to an input/output pad of the MPGA die (1811 in FIG. 18C) without the intermediate register.

In the conversion platform comprising the FPGA in FIG. 18A and MPGA in FIG. 18C, said region 1802 of the FPGA and said MPGA further comprises an exact layout of one or more pass-gate devices to couple a said programmable logic block to a said interconnect wire, wherein: in the FPGA, the pass-gate device couples the logic block to the interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising: a logic one to couple the logic block to the interconnect wire; and a logic zero to decouple the logic block from the interconnect wire; and in the MPGA, the pass-gate device couples the logic block to the interconnect wire, said pass-gate device controlled by an output of a ROM bit, said ROM bit comprising: a metal connection to power bus to couple the logic block to the interconnect wire; and a metal connection to ground bus to decouple the logic block from the interconnect wire. When the RAM bit in a 3D configuration within the FPGA is replaced by a hard-wired ROM bit in the MPGA, the circuit behavior and interconnect pattern is maintained between the two devices.

In the conversion platform comprising the FPGA in FIG. 18A and MPGA in FIG. 18C, said region 1802 of the FPGA and said MPGA further comprises an exact layout of one or more pass-gate devices to couple said one or more logic blocks to a said interconnect wire, wherein: in the FPGA, a pass-gate device couples a logic block to an interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising: a logic one to couple the logic block to the interconnect wire; and a logic zero to decouple the logic block from the interconnect wire; and in the MPGA, said pass-gate device is decoupled from said interconnect wire when the RAM bit comprises a logic zero; and in the MPGA, said pass-gate device is replaced by a metal jumper when the RAM bit comprises a logic one. By this conversion, an interconnect wire in the FPGA comprises a high capacitance due to the pass-gate device junctions coupled to the interconnect wire, and wherein said interconnect wire in the MPGA comprises less capacitance due to the pass-gate junctions decoupled from the interconnect wire; and an interconnect wire coupled to a logic block encounters a high resistance from the on pass-gate device in the FPGA, and wherein said interconnect wire coupled to the logic block in the MPGA encounters less resistance due to the metal-jumper. It is easily appreciated that in an FPGA any given wire segment is coupled to a plurality of logic blocks, both inputs and outputs of logic blocks, which makes FPGA slower and consume more power. In the conversion to an MPGA, much of the unwanted logic blocks can be decoupled from the wire segment, thereby making the MPGA faster or consume less power. It can be further appreciated that the position of the wire segment has not altered between the FPGA and the MPGA, thus the wire delays are easily pre-characterized and the conversion is made bit-stream compatible.

Clearly the new modular concept described in this and enclosed-by-reference applications disclose devices where the configuration circuit module layer is positioned above a circuit module layer. Thus between the FPGA (that comprises user RAM configuration module layer) and the derivative MPGA (that comprises a hard-wire configuration circuit) the circuit transistors in first module layer comprises an identical layout. The interconnect wires between the two devices also comprises a nearly identical layout: in a first embodiment when RAM bit is replaced by a ROM bit, the interconnect is identical; and in a second embodiment when nodes are disconnected from wire segments and pass-gates are replaced by metal jumpers, the interconnect is nearly identical. In both cases, the interconnect segments have not positionally changed.

Next, a brief description of the manufacturing process is discussed. During manufacturing, one or more digital circuits can be formed on a substrate. Next, the process selectively fabricates either a memory circuit or a conductive pattern substantially above the digital circuits to control portion of digital circuits. Finally, the process fabricates an interconnect and routing layer substantially above the digital circuits and memory circuits to connect digital circuits and one of the memory circuit or the conductive pattern.

The process can be modified to fabricate a generic field programmable gate array (FPGA) with the constructed memory circuit or an application specific integrated circuit (ASIC) with the constructed conductive pattern. Multiple ASICs can be fabricated with different variations of conductive patterns. The memory circuit and the conductive pattern have one or more substantially matching circuit characteristics. In this case, timing characteristics substantially unchanged by the circuit control option. The process thus fabricates a programmable logic device by constructing digital circuits on a substrate; and constructing a non-planar circuit on the substrate after constructing the digital circuits, the non-planar circuit being either a memory deposited to store data to configure the digital circuits to form a field programmable gate array (FPGA) or a conductive pattern deposited to hard-wire the digital circuits to form an application specific integrated circuit (ASIC), wherein the deposited memory and the conductive pattern have substantially matching timing characteristics. In another embodiment, the hard-wire ASIC option may be incorporated into the digital circuit layer 100. In another embodiment, the hard-wire ASIC option is incorporated into the routing layer 110.

Although an illustrative embodiment of the present invention, and various modifications thereof, have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to this precise embodiment and the described modifications, and that various changes and further modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention as defined in the appended claims.

Claims

1. An integrated circuit design platform, comprising:

a field programmable gate array (fpga) prototype device comprised of:

a circuits layout comprising a plurality of field programmable logic blocks and a plurality of layers of field programmable interconnects; and

a set of input/output pad structures; and

a first region within the circuits layout, said region having registers at one or more boundaries of the region, said registers capable of coupling to said input/output pad structures; and

a metal programmable gate array (mpga) production device fabricated separately from the fpga prototype device, the mpga production device comprised of:

a substantially identical circuit layout as in the first region of the fpga; and

a substantially identical layout of one or more layers of programmable interconnects as in the first region of the fpga;

wherein, a design mapped to the first region of the fpga is identically mapped to the mpga.

2. The platform of claim 1, wherein the fpga comprises a configuration circuit to field program the programmable logic blocks and programmable interconnects.

3. The platform of claim 2, wherein in the fpga, the transistors for logic circuits are formed on a first module layer and the configuration circuit is formed on a second module layer positioned substantially above or below the first module layer.

4. The platform of claim 2, wherein the configuration circuit comprises one or more of: resistor, capacitor, SRAM cell, DRAM cell, Flash cell, EPROM cell, EEPROM cell, Carbon nano-tube, resistance modulating element, ferro-electric element, electro-chemical cell, electro-mechanical element, optical element and electro-magnetic cell.

5. The platform of claim 1, wherein the mpga comprises a customized metal circuit to mask program the programmable logic blocks and programmable interconnects.

6. The platform of claim 5, wherein the customized metal circuit comprises one or more of: wire connection, wire disconnect, via connection, resistor element, shorted capacitor, capacitor, power bus connection, ground bus connection, transistor short, logic zero output connection, and logic one output connection.

7. The platform of claim 1, wherein said first region of the fpga and said first mpga further comprises comprise a substantially identical layout of one or more pass-gate devices to couple said programmable logic block to said an interconnect wire, wherein:

in the fpga, the pass-gate device couples the logic block to the interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising:

a logic one to couple the logic block to the interconnect wire; and

a logic zero to decouple the logic block from the interconnect wire; and

in the mpga, the pass-gate device couples the logic block to the interconnect wire, said pass-gate device controlled by an output of a ROM bit, said ROM bit comprising:

a metal connection to a power bus to couple the logic block to the interconnect wire; and

a metal connection to a ground bus to decouple the logic block from the interconnect wire.

8. The platform of claim 1, wherein said first region of the fpga and said first mpga further comprises comprise a substantially identical layout of one or more pass-gate devices to couple said one or more logic blocks to said an interconnect wire, wherein:

in the fpga, a pass-gate device couples a logic block to an interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising:

a logic one to couple the logic block to the interconnect wire; and

a logic zero to decouple the logic block from the interconnect wire; and

in the mpga, said pass-gate device is decoupled from said interconnect wire when the RAM bit comprises a logic zero;

wherein an interconnect wire in the fpga comprises a high capacitance due to the pass-gate device junctions coupled to the interconnect wire, and wherein said interconnect wire in the mpga comprises less capacitance due to the pass-gate junctions decoupled from the interconnect wire.

9. The platform of claim 1, wherein said first region of the fpga and said first mpga further comprises comprise a substantially identical layout of one or more pass-gate devices to couple said one or more logic blocks to a said an interconnect wire, wherein:

in the fpga, a pass-gate device couples a logic block to an said interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising:

a logic one to couple the logic block to the interconnect wire; and

a logic zero to decouple the logic block from the interconnect wire; and

in the mpga, said pass-gate device is replaced by a metal jumper when the RAM bit comprises a logic one;

wherein an interconnect wire coupled to a logic block encounters a high resistance from the on pass-gate device in the fpga, and wherein said interconnect wire coupled to the logic block in the mpga encounters less resistance due to the metal-jumper.

10. The platform of claim 1, further comprising:

said field programmable gate array (fpga) prototype device comprised of:

a second region within the circuits layout, said second region having registers at one or more boundaries of the region, said register registers capable of coupling to said input/output pad structure; and

a second metal programmable gate array (second mpga) production device comprised of:

a substantially identical circuits layout as in the second region of the fpga; and

a substantially identical layout of one or more layers of programmable interconnects as in the second region of the fpga;

wherein, a design mapped to the second region of the fpga is identically mapped to the second mpga.

11. An integrated circuit design platform, comprising:

a prototype field programmable (fpga) device comprising a layout of electronic circuits and input/output pads; and

a production mask programmable (mpga) device fabricated separately from the fpga prototype device, the mpga device comprising:

a layout of electronic circuits substantially identical to a region within the prototype fpga device; and

a subset of input/output pads as within the prototype fpga device;

wherein a design placed and routed within the region of the prototype fpga device using the subset of input/output pads as in the production mpga device, is identically placed and routed in the production mpga device.

12. The platform of claim 11, wherein the region of the fpga and the mpga has substantially identical layouts of transistors and substantially identical layouts of one or more layers of interconnects.

13. The platform of claim 11, wherein the mpga has at least one customized interconnect layer to map field programmable data in the prototype fpga to mask programmable data.

14. The platform of claim 11, wherein the fpga comprises a configuration circuit further comprising one or more of: resistor, capacitor, SRAM cell, DRAM cell, Flash cell, EPROM cell, EEPROM cell, Carbon nano-tube, resistance modulating element, ferro-electric element, electro-chemical cell, electro-mechanical element, optical element and electromagnetic cell.

15. The platform of claim 11, wherein the mpga comprises a customized metal circuit further comprising one or more of: wire connection, wire disconnect, via connection, resistor element, shorted capacitor, capacitor, power bus connection, ground bus connection, transistor short, logic zero output connection, and logic one output connection.

16. The platform of claim 11, wherein the fpga comprises a RAM bit, and wherein the mpga comprises a hard-wired ROM bit.

17. The platform of claim 11, wherein the mpga comprises one or more of:

a metal link to couple a node to a power supply voltage; and

a metal link to couple a node to a ground supply voltage; and

a metal jumper to short two nodes; and

a metal disconnect to isolate two nodes.

18. A small mask programmable gate array (mpga) device derived from a large field programmable gate array (fpga) device fabricated separately from the fpga prototype device, the mpga device, comprising:

a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the fpga device; and

input/output pads matching a subset of the input/output pads of the fpga device;

wherein, a design that is mapped to said small region of the fpga device using said subset of input/output pads by a user programmable means is identically mapped to the mpga device by a hard-wire circuit during a subsequent fabrication of the mpga device.

19. The device of claim 18, further comprising:

a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the fpga; and

a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the fpga.

20. The device of claim 18, wherein:

a first set of input/output pad pads to a first set of logic blocks within the mpga is identically mapped from that of the fpga; and

a second set of input/output pad pads to a second set of logic blocks within the mpga is mapped from the corresponding logic blocks to registers at region boundary to corresponding input/output pads of the fpga.

21. A method of producing a metal programmable gate array (mpga), said method comprising:

accessing a design for a circuits layout for a field programmable gate array (fpga), said circuits layout in said design comprising a plurality of field programmable logic blocks configured in a core region, said core region in said design comprising a plurality of sub-regions that are smaller than said core region, said design for said fpga further comprising a first region within said circuits layout and a register at a boundary of said first region, a plurality of layers of field programmable interconnects, and a set of input/output (I/O) pad structures; and

fabricating an mpga device based on said design, said design configured so that said fabricating of said mpga device is separate from fabrication of an fpga according to said design, said mpga device comprising a circuit layout comprising a subset of said plurality of said sub-regions that are in said design, said circuit layout of said mpga device comprising a substantially identical layout as in said first region of said design but excluding said register at said boundary of said first region, wherein said mpga device further comprises a substantially identical layout of one or more of said layers of programmable interconnects as in said first region of said design;

wherein said first region in said design is identically mapped to said mpga device.

22. The method of claim 21, wherein said design for said fpga comprises a plurality of input/output (I/O) pads arranged around a perimeter of said core region, wherein said mpga device interfaces with a subset of said plurality of I/O pads that are in said design.

23. The method of claim 21, wherein said design comprises power and ground pad structures that are arranged in positions that are common to all of said sub-regions.

24. The method of claim 21, wherein said mpga device further comprises:

a first module layer comprising field programmable logic blocks; and

a second module layer adjacent to said first module layer and comprising routing circuitry coupled to said field programmable logic blocks of said mpga device.

25. The method of claim 21, further comprising:

identifying a timing difference between an input/output (I/O) delay for said design and an I/O delay determined for said mpga device; and

compensating for said timing difference in said mpga device.

26. The method of claim 21, wherein said plurality of sub-regions comprises a first region and a second region positioned concentrically about the perimeter of said first region.

27. The method of claim 21, wherein sub-regions of said plurality of sub-regions share a first boundary and a second boundary.

28. The method of claim 21, wherein said mpga device further comprises a customized metal circuit to mask program programmable logic blocks and programmable interconnects in said mpga device.

29. The method of claim 28, wherein said customized metal circuit is selected from the group consisting of: wire connection, wire disconnect, via connection, resistor element, shorted capacitor, capacitor, power bus connection, ground bus connection, transistor short, logic zero output connection, and logic one output connection.

30. The method of claim 21, wherein said mpga device and said first region of said design further comprise a substantially identical layout of one or more pass-gate devices configured to couple a field programmable logic block to an interconnect wire, wherein in said mpga device, said pass-gate device is operable for coupling said logic block to said interconnect wire, said pass-gate device is controlled by an output of a ROM bit, and said ROM bit comprises:

a metal connection to a power bus to couple said field programmable logic block to said interconnect wire; and

a metal connection to a ground bus to decouple said field programmable logic block from said interconnect wire.

31. The method of claim 21, wherein said mpga device and said first region of said design further comprise a substantially identical layout of one or more pass-gate devices configured to couple a field programmable logic block to an interconnect wire, wherein in said mpga device, said pass-gate device is decoupled from said interconnect wire when a RAM bit comprises a logic zero.