A nonvolatile semiconductor memory device include: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends. A transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage. A load circuit is connected to the variable resistive element in series having an adjustable load resistance. A voltage generation circuit applies a voltage to both ends of a serial circuit. The variable resistive element can transit between the states by adjusting a resistance of the load circuit.

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Patent
   RE45345
Priority
Dec 08 2006
Filed
Sep 19 2013
Issued
Jan 20 2015
Expiry
Nov 05 2027
Inventors
Sato, Shin…
Assg.orig
Xenogenic …
Assg.curr
Xenogenic …
Entity
Large
Referenced by
0
References
8
Maint.:
all paid
CROSS-REFERENCE TO R…
First Embodiment
Second Embodiment
Third Embodiment
INDUSTRIAL APPLICABI…
0. 7. A device comprising:
a memory cell including a variable resistive element having two terminals;
a load circuit connected to the variable resistive element and configured to switch load resistive characteristics between first load resistive characteristics and second load resistive characteristics, wherein the second load resistive characteristics have a resistance higher than the first load resistive characteristics; and
a voltage generation circuit configured to apply a voltage to a circuit formed by the variable resistive element and the load circuit;
wherein the variable resistive element is configured to write to a stored state upon changing between a low resistance state and a high resistance state in response to application of the voltage to the variable resistive element;
wherein the variable resistive element is configured to show asymmetric characteristics such that, when a polarity of an applied voltage to a first terminal of the memory cell compared to a second terminal is a first polarity, a first threshold voltage is lower than a second threshold voltage, wherein the first threshold voltage comprises a lower limit value of an absolute value of the applied voltage required for the resistive characteristics to transit from the low resistance state to the high resistance state, and wherein the second threshold voltage comprises a lower limit value of an absolute value of the applied voltage required for the resistive characteristics to transit from the high resistance state to the low resistance state; and
wherein the load circuit is further configured to switch the load resistive characteristics to show:
the first load resistive characteristics during a first writing operation in which the load resistive characteristics of the variable resistive element transit from the low resistance state to the high resistance state; and
the second load resistive characteristics during a second writing operation in which the load resistive characteristics of the variable resistive element transit from the high resistance state to the low resistance state.
1. A nonvolatile semiconductor memory device comprising:
a memory cell having a variable resistive element having two terminals, the variable resistive element having resistive characteristics defined by current-voltage characteristics at both ends, the resistive characteristics transiting between two stably provided resistive characteristics of a low resistance state and a high resistance state when a voltage satisfying a predetermined condition is applied to the both ends;
a load circuit connected to one end of the variable resistive element in series, the load circuit having load resistive characteristics defined by the current-voltage characteristics, the load resistive characteristics being switched between first load resistive characteristics and second load resistive characteristics, the second load resistive characteristics having a resistance higher than the first load resistive characteristics; and
a voltage generation circuit for applying a voltage to both ends of a serial circuit configured by the variable resistive element and the load circuit, wherein
a stored state of the variable resistive element is determined whether the resistive characteristics are in the low resistance state or the high resistance state and written when the resistive characteristics transit between the low resistance state and the high resistance state in response to application of a voltage to the both ends of the variable resistive element,
the variable resistive element shows asymmetric characteristics in which when a polarity of an applied voltage to one terminal based on the other terminal is a first polarity, a first threshold voltage is lower than a second threshold voltage, the first threshold voltage being a lower limit value of an absolute value of the applied voltage required for the resistive characteristics to transit from the low resistance state to the high resistance state, the second threshold voltage being a lower limit value of an absolute value of the applied voltage required for the resistive characteristics to transit from the high resistance state to the low resistance state, and when the polarity of the applied voltage is a second polarity different from the first polarity, the first threshold voltage is higher than the second threshold voltage,
the load resistive characteristics of the load circuit are switched so as to show the first load resistive characteristics during a first writing operation in which the resistive characteristics of the variable resistive element transit from the low resistance state to the high resistance state, and show the second load resistive characteristics during a second writing operation in which the resistive characteristics of the variable resistive element transit from the high resistance state to the low resistance state, and
the voltage generation circuit applies a first writing voltage to the both ends of the serial circuit of the variable resistive element and the load circuit so that a voltage of the first polarity having an absolute value equal to or higher than the first threshold voltage is applied to the both ends of the variable resistive element of the memory cell to be written during the first writing operation, and applies a second writing voltage to the both ends of the serial circuit of the variable resistive element and the load circuit so that the voltage of the first polarity having the absolute value equal to or higher than the second threshold voltage is applied to the both ends of the variable resistive element of the memory cell to be written during the second writing operation.
2. The nonvolatile semiconductor memory device according to claim 1, wherein
the variable resistive element has a three-layer structure in which a variable resistor is sandwiched between a first electrode and a second electrode.
3. The nonvolatile semiconductor memory device according to claim 2, wherein
the memory cell has a rectifying element connected to the variable resistive element in series, and
the rectifying element provides forward bias when the voltage having the first polarity is applied to the both ends of the variable resistive element.
4. The nonvolatile semiconductor memory device according to claim 3, wherein
when the first polarity is a positive polarity, a Schottky barrier diode is provided at an interface between an N-type polycrystalline semiconductor and a lower electrode that is the lower of the first electrode and the second electrode, the N-type polycrystalline semiconductor being formed so as to be in contact with a lower surface of the lower electrode, and
when the first polarity is a negative polarity, the Schottky barrier diode is provided at an interface between a P-type polycrystalline semiconductor and the lower electrode, the P-type polycrystalline semiconductor being formed so as to be in contact with the lower surface of the lower electrode.
5. The nonvolatile semiconductor memory device according to claim 4, wherein
when the first polarity is the positive polarity, a P-type impurity is implanted to a part of a contact region with the lower electrode in the N-type polycrystalline semiconductor, and
when the first polarity is the negative polarity, an N-type impurity is implanted to a part of the contact region with the lower electrode in the P-type polycrystalline semiconductor.
6. The nonvolatile semiconductor memory device according to claim 3, wherein
when the first polarity is a positive polarity, a PN junction diode includes a P-type upper polycrystalline semiconductor formed so as to be in contact with a lower layer of the lower electrode, and an N-type lower polycrystalline semiconductor formed so as to be in contact with a lower layer of the upper polycrystalline semiconductor, and
when the first polarity is a negative polarity, a PN junction diode includes an N-type upper polycrystalline semiconductor formed so as to be in contact with a lower layer of the lower electrode, and a P-type lower polycrystalline semiconductor formed so as to be in contact with a lower layer of the upper polycrystalline semiconductor.
0. 8. The device of claim 7, wherein the voltage generation circuit is further configured to:
apply a first writing voltage to the circuit formed by the variable resistive element and the load circuit so that a voltage of the first polarity having an absolute value equal to or higher than the first threshold voltage is applied to the variable resistive element during the first writing operation; and
apply a second writing voltage to the circuit formed by the variable resistive element and the load circuit so that the voltage of the first polarity having the absolute value equal to or higher than the second threshold voltage is applied to the variable resistive element during the second writing operation.
0. 9. The device of claim 7, wherein the variable resistive element has a three-layer structure, and wherein the three-layer structure comprises a first electrode, a second electrode, and a variable resistor positioned between the first electrode and the second electrode.
0. 10. The device of claim 9, further comprising a Schottky barrier diode located at an interface between an N-type polycrystalline semiconductor and a lower electrode that is the lower of the first electrode and the second electrode, wherein the N-type polycrystalline semiconductor is in contact with a lower surface of the lower electrode.
0. 11. The device of claim 10, wherein the lower electrode comprises a contact region including an implanted P-type impurity.
0. 12. The device of claim 10, further comprising a PN junction diode including:
a P-type upper polycrystalline semiconductor in contact with a lower layer of the lower electrode; and
an N-type lower polycrystalline semiconductor in contact with a lower layer of the P-type upper polycrystalline semiconductor.
0. 13. The device of claim 9, further comprising a Schottky barrier diode located at an interface between a P-type polycrystalline semiconductor and a lower electrode that is the lower of the first electrode and the second electrode, wherein the P-type polycrystalline semiconductor is in contact with a lower surface of the second electrode.
0. 14. The device of claim 13, wherein the lower electrode comprises a contact region including an implanted N-type impurity.
0. 15. The device of claim 13, further comprising a PN junction diode including:
an N-type upper polycrystalline semiconductor in contact with a lower layer of the lower electrode; and
a P-type lower polycrystalline semiconductor in contact with a lower layer of the N-type upper polycrystalline semiconductor.
0. 16. The device of claim 7, wherein the memory cell comprises a rectifying element connected to the variable resistive element in series, and wherein the rectifying element is configured to provide a forward bias when the applied voltage having the first polarity is applied to the variable resistive element.
0. 17. The device of claim 7, further comprising a word line selection circuit configured to:
select a word line of a memory cell array that corresponds to an address signal; and
apply a selected word line voltage to the selected word line for respective memory operations.
0. 18. The device of claim 7, further comprising a bit line selection circuit configured to:
select a bit line of a memory cell array that corresponds to an address signal; and
individually apply a selected bit line voltage to the selected bit line for respective memory operations.
0. 19. The device of claim 7, further comprising a voltage switching circuit configured to:
apply a selected word line voltage and an unselected word line voltage to a word line selection circuit; and
apply a selected bit line voltage and an unselected bit line voltage to a bit line selection circuit.
CROSS-REFERENCE TO RELATED APPLICATIONS

This application is

Now, in order to satisfy the above requirement, V<Vb should be satisfied when I=Ib. Thus, the Equation (1) and the condition lead to the following Equation (2):
(Va−Vb)/(Ib−Ia)<R1   (2)

Now, the resistance value in the left term of the Equation (2) corresponds to the critical resistance value. The resistance value R1 corresponds to the first resistance value, and can be expressed by the following Equation (3) by using respective coordinate values of the characteristic point Ta (Va, Ia) and the intersecting point T1 (Vt1, It1).
R1=(Va−Vt1)/(It1−Ia)   (3)

Furthermore, then, the voltage amplitude Vda of voltage pulses that have the variable resistive element transit from the high resistance state to the low resistance state through load resistance should have higher voltage than the second critical voltage VA. In fact, since the value obtained by substituting 0 for I in the Equation (1) showing the load resistive characteristic line C1 is the second critical voltage VA, the voltage amplitude Vda should satisfy the following Equation (4).
Vda>Va+R1×Ia   (4)

We continue to describe a range of load resistive characteristics desirable for a transition from the low resistance state to the high resistance state, and a range of drive voltage Vdb (voltage amplitude of voltage pulses) to be applied to a serial circuit of a load circuit and a variable resistive element (memory cell). If load resistance of resistance value R2 is connected in series to a variable resistive element having the resistive characteristics shown in FIG. 7A, the load resistive characteristics passing through the characteristic point Tb (Vb, Ib) are plotted as a straight line C2 in FIG. 7C. Then, the drive voltage Vdb is defined as a “first critical voltage VB”. In order to perform a stable operation from the low resistance state to the high resistance state, it is required that the load resistive characteristic line C2 intersect the I-V characteristic curve in the high resistance state at a point T2 (Vt2, It2) on the low voltage side of the characteristic point Ta (Va, Ia) from the high resistance state to the low resistance state. In fact, the load resistance characteristic line C2 going through the characteristic point Tb in FIG. 7C can be expressed by the Equation (5):
V=−R2×(I−Ib)+Vb   (5)

Now, in order to satisfy the above requirement, V<Va should be satisfied when I=Ia. Thus, the Equation (5) and the condition lead to the following Equation (6):
(Va−Vb)/(Ib−Ia)>R2   (6)

Now, the resistance value in the left term of the Equation (6) corresponds to the critical resistance value. The resistance value R2 corresponds to the second resistance value, and can be expressed by the following Equation (7) by using respective coordinate values of the characteristic point Tb (Vb, Ib) and the intersecting point T2 (Vt2, It2).
R2=(Vt2−Vb)/(Ib−It2)   (7)

Furthermore, then, the voltage amplitude Vdb of voltage pulses that have the variable resistive element transit from the low resistance state to the high resistance state through load resistance should have higher voltage than the first critical voltage VB. In fact, since the value obtained by substituting 0 for I in the Equation (5) showing the load resistive characteristic line C2 is the first critical voltage VB, the voltage amplitude Vdb should satisfy the following Equation (8).
Vdb>Vb+R2×Ib   (8)

In the above description, although the second critical voltage VA and the first critical voltage VB are different, it is possible to set same voltage to voltage amplitude Vda of voltage pulses for having the variable resistive element from the high resistance state to the low resistance state and voltage amplitude Vdb of voltage pulses for having the variable resistive element from the low resistance state to the high resistance state, as far as they satisfy the Equations (4) and (8).

In this case, for instance, in switching operation from the low resistance state to the high resistance state, the voltage amplitude Vdb has considerably higher voltage than the first critical voltage VB, and in FIG. 7C, even if the load resistive characteristic line C2 moves in parallel to the right (the high voltage direction) and the intersection between the load resistive characteristic line C2 and the I-V characteristic curve in the high resistance state (characteristics A) moves to the high voltage side of the characteristic point Ta (Va, Ia), then bidirectional transitions occur between the high resistance state and the low resistance state, thus leading to unstable oscillation condition. However, when application of voltage pulses ends, the load resistive characteristic line C2 moves in parallel to the left (direction of low voltage) as the voltage amplitude Vdb lowers, and the intersection between the load resistive characteristic line C2 and the I-V characteristic curve in the high resistance state (characteristics A) moves to the low voltage side of the characteristic point Ta (Va, Ia). Thus, a transition to the high resistance state finally occurs and the resistive characteristics become stable in the high resistance state. Furthermore, in switching operation from the high resistance state to the low resistance state, the voltage amplitude Vda has considerably higher voltage than the second critical voltage VA, and in FIG. 7B, even if the load resistive characteristic line C1 moves in parallel to the right (the high voltage direction) and the intersection between the load resistive characteristic line C1 and the I-V characteristic curve in the low resistance state (characteristics B) moves to the high voltage side of the characteristic point Tb (Vb, Ib), then bidirectional transitions occur between the high resistance state and the low resistance state, thus leading to unstable oscillation condition. However, when application of voltage pulses ends, the load resistive characteristic line C1 moves in parallel to the left (direction of low voltage) as the voltage amplitude Vda lowers, and the intersection between the load resistive characteristic line C1 and the I-V characteristic curve in the low resistance state (characteristics B) moves to the low voltage side of the characteristic point Tb (Vb, Ib). Thus, a transition to the low resistance state finally occurs and the resistive characteristics becomes stable in the low resistance state. Then, due to the above, it is possible to set the voltage amplitude Vda and the voltage amplitude Vdb to same voltage in the device of the present invention.

In view of the above consideration, when the internal resistance Rc of the variable resistive element 21 is considered, that is, when the resistive characteristics become asymmetric based on the positive and negative applied voltages, a description will be made below of a case where the transition of the resistance state of the variable resistive element 21 is controlled by switching the load resistance Rz. Here also, the description will be made of the variable resistive element 21 showing the I-V characteristics in FIG. 5.

The graph of the I-V characteristics in FIG. 5 shows a relation between the voltage applied to both ends of the serial circuit of the load resistance Rz and the variable resistive element 21 and the current flowing in the serial circuit under the condition that the load resistance Rz=0. Thus, as the load resistance Rz is sequentially increased from this state, since the load resistance Rz is connected to the internal resistance Rc in series, it is equivalent to adding the resistance value of the load resistance Rz to the resistance value of the internal resistance Rc in FIG. 5, so that the load resistance component (Rc+Rz) connected in series to the variable resistance component Rv (showing the symmetric property) in the variable resistive element 21 is increased (the inclination of the load resistance component in FIG. 5 becomes gentle). A description will be made of the above with reference to FIG. 8 shown in the same way as FIG. 5.

When the load resistance Rz is not considered, that is, when the load resistance Rz=0, according to the above consideration, in the case where the positive voltage is applied, although the transition from the high resistance state (A) to the low resistance state (B) can be stably made, the transition from the low resistance state (B) to the high resistance state (A) cannot be stably made. Meanwhile, in the case where the negative voltage is applied, although the transition from the low resistance state (B) to the high resistance state (A) can be stably made, the transition from the high resistance state (A) to the low resistance state (B) cannot be stably made. Therefore, when it is assumed that the transition from the low resistance state (B) to the high resistance state (A) can be stably made with the positive voltage by increasing the load resistance Rz to a predetermined value Z (>0), the switching characteristics are provided in response to only the application of the positive voltage (unipolar switching), by the switching control of the value of the load resistance Rz. Similarly, when it is assumed that the transition from the high resistance state (A) to the low resistance state (B) can be stably made with the negative voltage by setting the load resistance Rz to a predetermined value Z (>0), the switching characteristics are provided in response to only the application of the negative voltage (unipolar switching), by the switching control of the value of the load resistance Rz. In other words, since the switching characteristics can be provided in response to the applied voltage having the same polarity, the advantage of the unipolar switching can be obtained. In view of the above consideration, it will be verified whether the transition from the low resistance state to the high resistance state can be stably made in response to the application of the positive voltage and whether the transition from the high resistance state to the low resistance state can be stably made in response to the application of the negative voltage, by changing the value of the load resistance Rz.

First, it will be verified whether or not the transition from the low resistance state (B) to the high resistance state (A) can be stably made in the range of the positive polarity, by increasing the value of the load resistance Rz. That is, referring to FIG. 8, when the load resistance Rz is increased after the voltage is applied to satisfy the characteristic point T15 (or at the same time of this application), the resistive characteristics of the variable resistive element 21 transit to the high resistance state, and the characteristic point is moved from T15 to T16z. However, since the voltage at the T16z is higher than the voltage at the characteristic point T11 to cause the transition from the high resistance state to the low resistance state, the resistance state cannot be stable in the high resistance state and becomes an oscillation state. That is, even when the value of the load resistance Rz is changed, the transition from the low resistance state (B) to the high resistance state (A) still cannot be stably made in the range of the positive polarity, and the unipolar switching cannot be performed.

Next, it is verified whether or not the transition from the high resistance state (A) to the low resistance state (B) can be stably made in the range of the negative polarity, by increasing the value of the load resistance Rz. That is, referring to FIG.
V=−R3×(I−Ia)+Va   (10)

Now, in order to satisfy the above requirement, V<Vb should be satisfied when I=Ib. Thus, the Equation (10) and the condition lead to the following Equation (11). The resistance value in the left term of the Equation (11) corresponds to the critical resistance value.
(Va−Vb)/(Ib−Ia)<R3   (11)

In addition, in MOSFET, even though voltage between source and drain has increased, increase in current is controlled when the voltage reaches a saturation region. Thus, the Equation (11) can be satisfied if the gate voltage is set so that the saturated current will be smaller than the current value (first threshold current) Ib at the characteristic point Tb (Vb, Ib).

Furthermore, as with the case in which linear load resistance is used, it is necessary that the voltage amplitude Vda of the voltage pulse for having the variable resistive element transit from the high resistance state to the low resistance state through MOSFET have higher voltage than the second critical voltage VA (Vda>VA). However, in FIG. 17B, the second critical voltage VA is given by a voltage value of the intersection of the load resistive characteristic curve C3 going through the characteristic point Ta (Va, Ia) and the voltage axis.

We continue to describe a range of load resistive characteristics desirable for a transition from the low resistance state to the high resistance state, and a range of drive voltage Vdb (voltage amplitude of voltage pulses) to be applied to a serial circuit of a load circuit and a variable resistive element (memory cell). If the variable resistive element has the resistive characteristics shown in FIG. 7A, and the gate voltage of MOSFET is set to high level (VH) so as to use load resistive characteristics C4, the load resistive characteristics going through the characteristic point Tb (Vb, Ib) are plotted like the curve C4 in FIG. 17C. Then, the drive voltage Vdb is defined as the first critical voltage VB. In order to perform stable operation from the low resistance state to the high resistance state, it is required that the load resistive characteristic line C4 intersect the I-V characteristic curve in the high resistance state at a point T4 (Vt4, It4) on the low voltage side of the characteristic point Ta (Va, Ia) from the high resistance state to the low resistance state. In fact, since, to the two resistive characteristics shown in FIG. 7A, the load resistance characteristic line C4 going through the characteristic point Tb in FIG. 17C and the intersecting point T4 (Vt4, It4) functions equivalent to load resistance of the second resistance value R4 defined by respective coordinate values of the characteristic point Tb (Vb, Ib) and the intersecting point T4 (Vt4, It4) of the Equation (12) as shown below, and thus the load resistance characteristic line C4 is expressed by the Equation (13) if the load resistive characteristics are represented by the second resistance value R4 for convenience.
R4=(Vt4−Vb)/(Ib−It4)   (12)
V=−R4×(I−Ib)+Vb   (13)

Now, in order to satisfy the above requirement, V<Va should be satisfied when I=Ia. Thus, the Equation (13) and the condition lead to the following Equation (14). The resistance value in the left term of the Equation (14) corresponds to the critical resistance value.
(Va−Vb)/(Ib−Ia)>R4   (14)

In addition, since the load resistive characteristic curve C4 needs to intersect the characteristic point Tb (Vb, Ib), the gate voltage should be set so that the saturated current of MOSFET can be larger than the current value Ib at the characteristic point Tb (Vb, Ib) (first threshold current).

Furthermore, then, as with the case in which linear load resistance is used, it is necessary that the voltage amplitude Vdb of the voltage pulse for having the variable resistive element transit from the low resistance state to the high resistance state through MOSFET have higher voltage than the first critical voltage VB (Vdb>VB). However, in FIG. 17C, the first critical voltage VB is given by a voltage value of the intersection of the load resistive characteristic curve C4 going through the characteristic point Tb (Vb, Ib) and the voltage axis.

In addition, due to similar reasons to those in the case in which linear load resistance is used, although the second critical voltage VA and the first critical voltage VB differ, it is possible to set them to same voltage as far as the condition that the voltage amplitude Vda of voltage pulses for having the variable resistive element transit from the high resistance state to the low resistance state has higher voltage than the second critical voltage VA (Vda>VA), and the condition that the voltage amplitude Vdb of voltage pulses for having the variable resistive element transit from the low resistance state to the high resistance state has higher voltage than the first critical voltage VB (Vdb>VB) are met, respectively.

In the following, we describe specific circuit configuration of the load resistive characteristic variable circuit 14, with reference to FIG. 18 and FIG. 19. FIG. 18 schematically shows a relation of the variable resistive element 21 of the selected memory cell to be written, the load circuit and the voltage switch circuit 17. In FIG. 18, the load circuit can be treated as all circuits excluding the selected memory cell in the circuit to which voltage pulses are applied from the voltage switch circuit 17, and include the word line decoder 12, the bit line decoder 13, the load resistive characteristic variable circuit 14, and parasitic resistance of signal wiring such as the selected word line or selected bit line or the like. Thus, the load resistive characteristics are assumed as the current-voltage characteristics of synthetic circuit of all circuits excluding the selected memory cell. In the example shown in FIG. 18, ground voltage Vss is applied to the selected bit line through the bit line decoder 13 from the voltage switch circuit 17, voltage for programming Vpp or voltage for erasing Vee are applied to the selected word line through the load resistance characteristic variable circuit 14 and the word line decoder 12. Although voltage for programming Vpp and voltage for erasing Vee are applied as voltage pulses to the selected word line, the pulse width (application duration) thereof is adjusted through control from the control circuit on the side of the voltage switch circuit 17 that supplies voltage for programming Vpp or voltage for erasing Vee, or on the side of the load resistive characteristic variable circuit 14 or the word line decoder 12 that is supplied with the voltage.

FIGS. 19 A to 19E show five examples of circuit configurations of the load resistive characteristic variable circuit 14. FIG. 19A shows the load resistive characteristic variable circuit 14 configured by parallel connection of P-type MOSFET 31 that is always in ON state and P-type MOSFET 32 that can be switched ON and OFF by a control signal Sc1. If the P-type MOSFET 31 and P-type MOSFET 32 are set to same size, switching of the load resistive characteristics as shown in FIG. 17A becomes possible by the control signal Sc1. In addition, use of a resistive element having linear or nonlinear resistive characteristics or a diode adapted to voltage polarities could also implement the load resistance characteristic circuit 14 capable of switching the load resistive characteristics by turning the P-type MOSFET 32 ON and OFF.

FIG. 19B shows the load resistive characteristic variable circuit 14 configured by parallel connection of P-type MOSFETs 33, 34 that can be switched ON or OFF by two control signals Sc2, Sc3. The P-type MOSFETs 33, 34 are controlled so that one is turned ON while the other is turned OFF. In the example shown in FIG. 19B, switching of the load resistive characteristics as shown in FIG. 17A becomes possible by making gate width or the like of the P-type MOSFETs 33, 34. In addition, the P-type MOSFETs 33, 34 may have same size and resistance component of different resistance values may be added in series to both or any one of them.

FIG. 19C shows the load resistive characteristic variable circuit 14 configured by one P-type MOSFET 35 that can control the gate voltage in multiple stages by one control signal Sc4. Switching of the load resistive characteristics as shown in FIG. 17A becomes possible, by configuring the control signal Sc4 so that one signal level for turning OFF the P-type MOSFET 35 and two signal levels for turning ON the P-Type MOSFET 35 can be outputted, and by switching the two signal levels for turning ON the P-type MOSFET 35.

FIG. 19D shows the load resistive characteristic variable circuit 14 configured by one P-type MOSFET 36 that can control the gate voltage and back gate (substrate) voltage in two stages, respectively, with two control signals Sc5, Sc6. The control signal Sc5 controls whether to turn ON or OFF the P-type MOSFET 36, while the control signal Sc6 adjusts the back gate voltage of the P-type MOSFET 36, thus changing the threshold voltage. Switching of the load resistive characteristics as shown in FIG. 17A becomes possible by turning ON the P-type MOSFET 36 and switching the threshold voltage in two ways to high or low, with the back gate voltage.

FIG. 19E shows the load resistive characteristic variable circuit 14 configured by one resistive control element 37 that can control the gate voltage in multiple stages with one control signal Sc7. As the resistive control element 37, a transfer gate composed of anything other than MOSFET or that composed of a single channel transistor or the like can be used. Switching of the load resistive characteristics becomes possible by switching signal levels of the control signal Sc7.

As shown in FIG. 1 and FIG. 18, in the above embodiment, we described the case in which the load resistive characteristic variable circuit 14 is provided between the voltage switch circuit 17 and the word line decoder 12, and voltage for programming Vpp and voltage for erasing Vee of same voltage polarity is applied to the load resistive characteristic circuit 14 from the voltage switch circuit 17. However, the load resistive characteristic variable circuit 14 is not limited to this configuration example, and may be provided within the word line decoder 12, between the word line decoder 12 and the memory cell array 11, between the bit line decoder 13 and the memory cell array 11, within the bit line decoder 13, between the bit line decoder 13 and the voltage switch circuit 17, or within the voltage switch circuit 17, for instance. In addition, if the load resistive characteristic variable circuit 14 is provided within the word line decoder 12 or the bit line decoder 13, a transistor for selecting a word line constituting the word line decoder 12 or that for selecting a bit line constituting the bit line decoder 13 may be configured by the same transistor as the load resistive characteristic variable circuit 14. In addition, the load resistive characteristic variable circuit 14 may not only be formed in one location, but also distributed in more than one location.

In addition, if the load resistive characteristic variable circuit 14 is configured by using MOSFET, depending on where it is formed or voltage polarity of voltage for programming Vpp and voltage for erasing Vee, N-type MOSFET may replace P-type MOSFET.

In the following, we describe the programming operation of the memory cells of the device of the present invention. In the following description, the programming operation is the case of having the resistive characteristics of the variable resistive element of the selected memory cell transit from the low resistance state to the high resistance state.

First, when the control circuit 16 is instructed by an address signal, a data entry signal, a control input signal, or the like from the external to program into a memory cell specified by the address signal, it activates the voltage switch circuit 17 and gives instruction to output voltage to be applied to each of the selected word line, unselected word line, selected bit line, and unselected bit line, during programming. The voltage switch circuit 17 supplies voltage for programming Vpp generated at the voltage generation circuit (not shown) to the word line decoder 12 through the load resistive characteristic variable circuit 14, supplies to the word line decoder 12 and the bit line decoder 13 programming inhibit voltage Vpp/2 that is one-half of the voltage for programming Vpp, and supplies ground voltage Vss to the bit line decoder 13. In addition, the control circuit 16 controls so that the load resistive characteristic variable circuit 14 can be load resistive characteristics for programming operation. In this embodiment, it controls so that the load resistive characteristics can be in the lower resistance state. As a result, by setting the voltage for programming Vpp higher than or equal to the above first critical voltage, voltage obtained by subtracting the voltage drop at the load resistive characteristic variable circuit 14 and the word line decoder 12 from the voltage for programming Vpp is applied to the selected word line through the load resistive characteristic variable circuit 14 and the word line decoder 12, while voltage increased from ground voltage Vss depending on the voltage drop at the bit line decoder 13 is applied to the selected bit line. Then, voltage higher than or equal to the first threshold voltage necessary for having the resistive characteristics transit from the low resistance state to the high resistance state is applied to both ends of the selected memory cell, the resistive characteristics transit from the low resistance state to the high resistance state, and programming completes. Then, as the variable resistive element transits to the high resistance state, a synthetic resistance value of the serial circuit of the load circuit and the memory cells increases, current flowing through the load circuit decreases, and voltage drop at the load circuit decreases. Thus, although voltage to be applied to both ends of the selected memory cell after transition to the high resistance state increases, the transition to the high resistance state occurs in a stable manner in a voltage condition in which voltage at both ends of the selected memory cell is lower than the second threshold voltage due to the load resistive characteristics selected by control of the load resistive characteristic variable circuit 14. As a result, the variable resistive element can maintain the high resistance state in a stable manner after voltage surges.

In addition, since voltage obtained by subtracting the voltage drop at the word line decoder 12 from the programming inhibit voltage Vpp/2 is applied to the unselected word line through the word line decoder 12 while voltage that increases by the voltage drop at the bit line decoder 13 from the programming inhibit voltage Vpp/2 is applied to the unselected bit line through the bit line decoder 13, no voltage is applied to the unselected memory cells that connect to the unselected word line and unselected bit line, and voltage obtained by subtracting the voltage drop at the word line decoder 12 and bit line decoder 13 from the programming inhibit voltage Vpp/2 is applied to the unselected memory cells that connect to the unselected word line and the selected bit line and those that connect to the selected word line and unselected bit line. Thus, any unwanted programming operation to the unselected memory cells can be prevented, by setting the voltage for programming Vpp so that at least the programming inhibit voltage Vpp/2 is lower than the first threshold voltage necessary for transiting the resistive characteristics from the low resistance state to the high resistance state.

In the following, we describe the erasing operation of memory cells. Now, the erasing operation is the case of having the resistive characteristics of the variable resistive element of the selected memory cell transit from the high resistance state to the low resistance state.

First, when the control circuit 16 is instructed by an address signal, a data entry signal, or a control input signal, etc. from the external to perform erasing of a target memory cell specified by the address signal, it activates the voltage switch circuit 17 and gives instruction to output voltage to be applied to each of the selected word line, unselected word line, selected bit line, and unselected bit line, during erasing. The voltage switch circuit 17 supplies voltage for erasing Vee of the same polarity as voltage for programming Vpp generated at the voltage generation circuit (not shown) to the word line decoder 12 through the load resistive characteristic variable circuit 14, supplies to the word line decoder 12 and the bit line decoder 13 erasing inhibit voltage Vee/2 that is one-half of the voltage for erasing Vee, and supplies ground voltage Vss to the bit line decoder 13. In addition, the control circuit 16 controls so that the load resistive characteristic variable circuit 14 can be load resistive characteristics for erasing operation. In this embodiment, it controls so that the load resistive characteristics can be in higher resistance state. As a result, by setting the voltage for erasing Vee higher than or equal to the above second critical voltage, voltage obtained by subtracting the voltage drop in the load resistive characteristic variable circuit 14 and the word line decoder 12 from the voltage for erasing Vee is applied to the selected word line through the load resistive characteristic variable circuit 14 and the word line decoder 12, while voltage increased from ground voltage Vss depending on the voltage drop at the bit line decoder 13 is applied to the selected bit line. Then, voltage higher than or equal to the second threshold voltage necessary for having the resistive characteristics transit from the high resistance state to the low resistance state is applied to both ends of the selected memory cell, the resistive characteristics transit from the high resistance state to the low resistance state, and erasing completes. Then, as the variable resistive element transits to the low resistance state, a synthetic resistance value of the serial circuit of the load circuit and the memory cells decreases, current flowing through the load circuit increases, and voltage drop at the load circuit increases. Thus, although voltage to be applied to both ends of the selected memory cell after transition to the low resistance state decreases, the transition to the low resistance state occurs in a stable manner in a voltage condition in which voltage at both ends of the selected memory cell is lower than the first threshold voltage due to the load resistive characteristics selected by control of the load resistive characteristic variable circuit 14. As a result, the variable resistive element can maintain the low resistance state in a stable manner after voltage surges.

In addition, since voltage obtained by subtracting the voltage drop at the word line decoder 12 from the erasing inhibit voltage Vee/2 is applied to the unselected word line through the word line decoder 12 while voltage that increases by the voltage drop at the bit line decoder 13 from the erasing inhibit voltage Vee/2 is applied to the unselected bit line through the bit line decoder 13, no voltage is applied to the unselected memory cells that connect to the unselected word line and unselected bit line, and voltage obtained by subtracting the voltage drop at the word line decoder 12 and bit line decoder 13 from the erasing inhibit voltage Vee/2 is applied to the unselected memory cells that connect to the unselected word line and the selected bit line and those that connect to the selected word line and unselected bit line. Thus, any unwanted erasing operation to the unselected memory cells can be prevented, by setting the voltage for erasing Vee so that at least the erasing inhibit voltage Vee/2 is lower than the second threshold voltage necessary for having the resistive characteristics transit from the high resistance state to the low resistance state.

In addition, although the second critical voltage VA and the first critical voltage VB are different, due to the reasons described above, it is possible to set the voltage for programming Vpp and that for erasing Vee to same voltage in this embodiment. In addition, the pulse widths of both voltage for programming Vpp and that for erasing Vee may be set to short pulse width such as 100 ns or shorter, for instance, and both pulse widths may be of same length. This could make it possible to distinguish programming operations from erasing operations only by switching the load resistive characteristics of the load resistive characteristic variable circuit 14, thereby considerably simplify the circuit configuration.

A known readout operation for memory cells written through the conventional unipolar switching operation or bipolar switching operations may be used as readout operations of memory cells of the device of the present invention. In addition, we omit detailed description of the readout operation as it is not the main object of the present invention.

As described above, according to the device of the present invention, since the load resistive characteristics of the load circuit can be switched between the two different load resistive characteristics, and the two load resistive characteristics can be selectively switched between the case where the resistive characteristics of the variable resistive element as the writing target transit from the low resistance state to the high resistance state and the case where the resistive characteristics transit from the high resistance state to the low resistance state, regardless of symmetric property of the element structure of the variable resistive element, a length of the voltage application time, or the polarity of the applied voltage, the load resistive characteristics can be set so as to separately satisfy the following two conditions to perform the stable switching operation as the variable resistive element that is a new aspect of the inventors of the present invention, such that, (1) when the resistive characteristics of the variable resistive element transit from the high resistance state to the low resistance state, a voltage higher than the threshold voltage of the transition is to be applied while the threshold voltage of the transition is lower than a threshold voltage of a transition in an opposite direction, and (2) when the resistive characteristics of the variable resistive element transit from the low resistance state to the high resistance state, a voltage higher than the threshold voltage of the transition is to be applied while the threshold voltage of the transition is lower than the threshold voltage of the transition in the opposite direction. Thus, the resistive characteristics of the variable resistive element can be switched between the high resistance state and the low resistance state in a stable manner.

Thus, especially, when the unipolar switching operation is implemented in the variable resistive element showing the bipolar switching characteristics by switching the load resistance, the unipolar switching operation can be implemented by supplying the both ends of the variable resistive element with the voltage showing the polarity in which the first threshold voltage to be applied to both ends of the variable resistive element to transit from the low resistance state to the high resistance state is lower than the second threshold voltage to be applied to both ends of the variable resistive element to transit from the high resistance state to the low resistance state under the condition that the load resistance is not considered, to control the switching of the load resistance.

Manufacturing Method of Device of the Invention

Next, a manufacturing method of the device of the present invention will be described with reference to the drawings.

First Embodiment

A description will be made of a first embodiment (hereinafter occasionally referred to as the “present embodiment”) according to a manufacturing method of the device of the present invention, with reference to FIGS. 20 to 36. FIG. 20 is a schematic view showing a memory cell to be formed in the present embodiment, and FIG. 21 is a plan view showing the memory cell. The device of the present invention manufactured in the present embodiment is configured by a first wiring including a tungsten (W) layer and a TiN adhesive layer, a memory cell portion including a TiN barrier metal, a resistance lowering layer formed of TiN-type polysilicon, a TiN lower electrode, and a TiOxNy variable resistor, and a second wiring including an upper electrode and a tungsten layer. In addition, FIGS. 22 to 32 show the manufacturing method of the present embodiment in the order of steps. In FIGS. 22 to 32, figures A each show a vertical sectional view taken along line X-X′ in FIG. 20, and figures B each show a vertical sectional view taken along line Y-Y′ in FIG. 20. In addition, although a single memory cell is shown in FIG. 20 to simplify the figure, a plurality of memory cells are actually arranged in an X direction and a Y direction with or without regular intervals.

In addition, the following figures schematically show the sectional structure, and a contraction scale in the drawing does not always coincide with a contraction scale of the actual structure. The same is true in a second embodiment and thereafter.

In addition, conditions such as a dimension of the film thickness etc., a concentration, and a temperature described below are just examples and the present invention is not limited thereto. The same is true in the following embodiments.

In addition, in the present embodiment, a description will be made of a case where the unipolar switching operation is implemented by applying a voltage whose polarity is positive at the upper electrode with respect to the lower electrode.

First, as shown in FIG. 22, a tungsten layer 53 serving as the first wiring is formed on an insulation film 51 formed of SiO2 or the like overlying a substrate made of silicon or the like through a adhesive layer 52 composed of TiN or the like. Although tungsten is used for the first wiring in the present embodiment, the present invention is not limited thereto and a transition metal such as Ti, Cu, Co or Ta, or an alloy of these metals containing tungsten, or oxide or nitride showing conductivity may be used alternatively. In addition, although TiN is used for the adhesive layer 52 in the present embodiment, the present invention is not limited thereto and TaN or TiW may be used alternatively. The layers of TiN and W are formed by a well-known method such as a CVD (Chemical Vapor Deposition) method or a sputtering method. The film thickness of the TiN adhesive layer 52 is about 30 nm, and the film thickness of the tungsten first wiring 53 is about 200 nm. In addition, the adhesive layer 52 may be deposited depending on the kind of the metal used in the first wiring 53 and the adhesive layer 52 is not an indispensable layer.

Then, as shown in FIG. 23, these laminated-layer structure is processed and formed into the shape of a line so as to become the first wiring by a well-known dry etching method through a resist as a mask patterned by a photolithography method. The wiring width and the wiring interval at this time are set to 250 nm.

Then, as shown in FIG. 24, an insulation film 54 of SiO2 or the like is formed on the first wiring and between the wirings. The SiO2 layer is formed by a plasma CVD method or a HDP (High Density Plasma) CVD method. Since the SiO2 layer is flattened by polishing in a following CMP (Chemical Mechanical Polishing) step, the film thickness of the SiO2 layer needs to be at least thicker than the first wiring. In the present embodiment, the SiO2 layer is formed to be 400 nm in thickness.

Then, as shown in FIG. 25, the SiO2 layer is polished by the well-known CMP method to remove the SiO2 layer on the first wiring 53 and flatten it. Since it is necessary to expose the tungsten surface by completely removing the SiO2 layer on the first wiring 53, the tungsten layer is also polished, but since the polishing rate of SiO2 to tungsten is high enough (about 10 or more), a polished thickness of the tungsten layer is considerably smaller than the formed thickness of the tungsten layer.

In addition, the method for forming the first wiring 53 is not limited to the above, and a well-known damascene process may be used.

Then, as shown in FIG. 26, the memory cell portion is formed. First, a barrier metal layer 55 is formed of TiN and a resistance lowering layer 56 is formed of Ti so as to be 30 nm and 10 nm in thickness, respectively. The barrier metal layer 55 is formed in order to prevent the reaction between polysilicon to be formed above and tungsten of the first wiring, and the resistance lowering layer 56 is formed in order to lower the adhesive resistance with polysilicon to be formed above. Although TiN is used for the barrier metal layer 55 in the present embodiment, the present invention is not limited thereto and TaN or TiW may be used instead. In addition, Ti is used for the resistance lowering layer 56 in the present embodiment, the present invention is not limited thereto and Co or Ni may be used.

Thereafter, an N-type polysilicon 57 layer serving as a component of the Schottky barrier diode is further formed by a well-known LP (Low Pressure) CVD method. According to this method, the N-type polysilicon layer is formed by mixing a dopant that becomes an N type such as PH3 while the polysilicon layer is formed. As an alternative method, a solid-phase diffusion method or a method for forming the N type by use of ion implantation may be used. In addition, a method for polycrystallizing an amorphous layer by a heat treatment may also be used. Thus, the dopant concentration of the formed N-type polysilicon layer 57 is about 5×1018 atoms/cm3, and the film thickness thereof is about 150 nm. In addition, although polysilicon is used in the present embodiment, the present invention is not limited thereto and a semiconductor material such as Ge and GaAs may be used alternatively. Further, a TiN layer serving as a metal side electrode of the Schottky barrier diode and a lower electrode 58 of the variable resistor is formed to be 100 nm in thickness. Since this TiN layer is removed a little in the following step of flattening an insulation film, the film thickness thereof needs to be set in view of an amount of the removal. In addition, although the TiN layer combines the metal side electrode of the Schottky barrier diode and the lower electrode of the variable resistor, another material having a relatively large work function such as Pt, Co, or Ni may be inserted as the metal side electrode of the Schottky barrier diode.

Next, as shown in FIG. 27, the laminated-layer structure serving as the Schottky barrier diode is processed and formed into the shape of a column by a well-known dry etching method through a resist as a mask patterned by a well-known photolithography method. This column-shaped structure is processed so as to be arranged on the first wiring and a diameter thereof is 130 nm.

Next, as shown in FIG. 28, an insulation film 59 is formed of SiO2 or the like on the column-shaped structure and between the column-shaped structures. This SiO2 layer is formed by the plasma CVD method or the HDPCVD method. Since the formed SiO2 layer is flattened by polishing the SiO2 layer in the later CMP step, the layer needs to be thicker than the thickness (height) of the column-shaped structure. In the present embodiment, the thickness of the SiO2 layer is about 500 nm.

Then, as shown in FIG. 29, the SiO2 layer is polished by the well-known CMP method to remove and flatten the SiO2 layer on the column-shaped structure. Since it is necessary to expose the surface of the TiN layer by completely removing the SiO2 layer on the column-shaped structure, the TiN layer positioned in the uppermost layer of the column-shaped structure is also polished, but since the polishing rate of SiO2 to the TiN is high enough (about 10 or more), a polished thickness of the TiN layer is considerably smaller than the formed thickness of the TiN layer.

Then, as shown in FIG. 30, a titanium oxynitride (hereinafter described as the “TiON” for example) serving as a variable resistor 60 is formed by oxidizing the exposed surface of the TiN layer. According to the present embodiment, the TiON layer is formed by being held in an atmosphere of atmospheric-pressure oxygen containing 10% by weight of ozone at a substrate temperature of 300° C. for 10 minutes. At this time, the film thickness of the TiON layer is about 10 nm. However, the method for forming the TiON variable resistor is not limited to the above method, and the conditions can be changed within a range of 5 to 100% by weight of ozone concentration, and 250 to 500° C. of the substrate temperature. In addition, as other methods, a heat treatment in a reduced-pressure oxygen atmosphere or an oxygen plasma atmosphere, or an oxidizing method using an oxidizing chemical solution can be used.

Then, as shown in FIG. 31, TiN serving as a adhesive layer 61 of the second wiring layer and tungsten serving as a second wiring layer 62 are deposited. The adhesive layer 61 functions not only as the adhesive layer of the second wiring layer 62 but also as the upper electrode of the variable resistor. In the present embodiment, although tungsten is used for the second wiring layer 62 similar to the first wiring, the present invention is not limited thereto and a transition metal such as Ti, Cu, Co or Ta or an alloy of these metals containing tungsten, or an oxide or nitride showing conductivity may be used alternatively.

Then, as shown in FIG. 32, the laminated-layer structure is processed and formed to be in the shape of a line by the well-known dry etching method through the resist as a mask patterned by a well-known photolithography method so that these laminated-layer structure becomes the second wiring. At this time, the second wiring needs to be arranged just above the column-shaped structure serving as the memory cell portion. In addition, the wiring width and wiring interval at this time is about 250 nm. Thereafter, an interlayer insulation film is formed and a flattening step is performed according to need, whereby the desirable nonvolatile semiconductor memory device can be manufactured.

The memory cells formed as described above are structured on the upper wiring layer (on the second wiring in the present embodiment) repeatedly, whereby a three-dimensional memory array can be built and the semiconductor memory device having the highly integrated variable resistive elements can be manufactured as shown in FIG. 33.

In addition, as a variation of the present embodiment, as shown in FIG. 34, a P-type polysilicon layer 63 can be inserted to a part where the N-type polysilicon layer 57 is in contact with the lower electrode 58. The P-type polysilicon layer 63 can be formed by ion implantation with boron in an oblique direction after the column-shaped structure serving as the memory cell portion has been formed (after the step shown in FIG. 27). When the structure shown in FIG. 34 is formed, in the case where the reverse voltage is applied to the Schottky barrier diode, a reverse current can be reduced due to the spread of a depletion layer from the PN junction as compared with the general Schottky barrier diode, so that the preferable device characteristics having less sneak path current can be obtained.

In addition, as still another variation in the present embodiment, as shown in FIG. 35, a P-type polysilicon layer 64 can be inserted between the N-type polysilicon layer 57 and the lower electrode 58. The P-type polysilicon layer 64 can be formed by the LPCVD method similar to the N-type polysilicon layer. Thus, since the PN junction diode is formed in the memory cell portion instead of the Schottky barrier diode, the preferable device characteristics having further less sneak path current can be obtained.

Although the description has been made of the case where the memory cell having the variable resistive element showing the bipolar switching characteristics by itself is manufactured in the above embodiment, for example, when the memory cell having the variable resistive element not showing the bipolar switching characteristics by itself is manufactured, the polysilicon layer 57 can be both N and P conductivity types. In this case, as shown in FIG. 36, the lower electrode 65 is formed of Cu, the variable resistor 66 is formed of CuO by oxidizing Cu, and the upper electrode 67 is formed of Ti, Ta, W, or the like.

In addition, at this time, when the polysilicon layer 57 is formed of N-type polysilicon, it is necessary to insert a metal electrode 68 having a relatively large work function such as Pt, Co, Ni, or the like between the lower electrode 65 and the N-type polysilicon layer 57, as an electrode to form the Schottky barrier diode with the N-type polysilicon layer 57. On the other hand, when the polysilicon layer 57 is formed of P-type polysilicon, it is necessary to insert a metal electrode 68 having a relatively small work function such as Ti, Ta, W, or the like between the lower electrode 65 and the P-type polysilicon layer 57, as an electrode to form the Schottky barrier diode with the P-type polysilicon layer 57.

Second Embodiment

A description will be made of a second embodiment (hereinafter occasionally referred to as the “present embodiment”) according to the manufacturing method of the device of the present invention, with reference to FIGS. 37 to 49. FIG. 37 is a schematic view showing a memory cell to be formed in the present embodiment, and FIG. 38 is a plan view showing the memory cell. The device of the present invention to be manufactured in the present embodiment is configured by a first wiring layer including an N+ layer and an N− layer formed in a P-type silicon substrate, a memory cell portion including a TiN lower electrode and a TiON variable resistor, a second wiring including a TiN layer serving as an upper electrode and a adhesive layer, and a W layer. In addition, FIGS. 39 to 46 show the manufacturing method of the present embodiment in the order of steps. In FIGS. 39 to 46, figures A each show a vertical sectional view taken along line X-X′ in FIGS. 38, and figures B each show a vertical sectional view taken along line Y-Y′ in FIG. 38. In addition, also in the present embodiment, similar to the first embodiment, a description will be made of a case where the unipolar switching operation is implemented by applying a voltage whose polarity is positive at the upper electrode with respect to the lower electrode.

First, as shown in FIG. 39, an N+ layer 72 and an N− layer 73 are formed in a P-type silicon substrate 71 by a well-known method such as ion implantation. The dopant concentration of the N+ layer at this time is 5×1020 atoms/cm3, and the dopant concentration of the N− layer is 1×1017 atoms/cm3. The concentrations are set to the above values because the N+ layer 72 needs to be sufficiently small in resistance as the first wiring layer while the N− layer 73 needs to form the Schottky junction in a contact with the TiN film serving as the lower electrode of the variable resistor.

Then, as shown in FIG. 40, an element isolation region 74 is provided by a well-known element isolation method, and the N+ layer 72 and the N− layer 73 are formed to be in the shape of a line. The N+ layer 72 and the N− layer 73 obtained in this way function as the first wiring.

Then, as shown in FIG. 41, a TiN layer serving as the metal side electrode of the Schottky barrier diode and the lower electrode 75 of the variable resistor is formed. At this time, the TiN layer is formed by a well-known method such as the sputtering method or the CVD method. In addition, since the TiN layer is removed a little in a later step of flattening an insulation film later, the film thickness thereof has to be set in view of an amount of the removal. In addition, the layer is formed so as to be in the shape of a line by the well-known dry etching method through a resist as a mask patterned by the well-known photolithography method.

Then, as shown in FIG. 42, an SiO2 insulation film 76 is formed on the TiN layer and between the TiN layers. The SiO2 layer is formed by the plasma CVD method or the HDPCVD method. Since the SiO2 layer is flattened by polishing in the later CMP step, the film thickness of the SiO2 layer needs to be at least thicker than the thickness (height) of the lower electrode 75. In the present embodiment, the SiO2 layer is deposited to be about 300 nm in thickness.

Then, as shown in FIG. 43, the SiO2 layer is polished by the well-known CMP method to remove and flatten the SiO2 layer on the lower electrode 75. Since it is necessary to expose the surface of TiN by completely removing the SiO2 layer on the TiN layer, the TiN layer itself is also polished, but since the polishing rate of SiO2 to TiN is high enough (about 10 or more), a polished thickness of the TiN layer is considerably smaller than the formed thickness of the layer.

Then, as shown in FIG. 44, a TiON layer serving as a variable resistor 77 is formed by oxidizing the exposed surface of the TiN layer. According to the present embodiment, the variable resistor is formed by being held in an atmosphere of atmospheric-pressure oxygen containing 10% by weight of ozone at a substrate temperature of 300° C. for 10 minutes. At this time, the film thickness of the variable resistor is 10 nm. However, the method for forming the variable resistor is not limited thereto, and the conditions can be changed within a range of 5 to 100% by weight of ozone concentration, and 250 to 500° C. of the substrate temperature. In addition, as an alternative method, a heat treatment in a reduced-pressure oxygen atmosphere or an oxygen plasma atmosphere, or an oxidizing method using an oxidizing chemical solution can be used.

Then, as shown in FIG. 45, a TiN layer serving as a adhesive layer 78 of a second wiring layer and a tungsten layer serving as a second wiring layer 79 are formed. The adhesive layer 78 functions not only as the adhesive layer of the second wiring layer 79 but also as the upper electrode of the variable resistor. Although tungsten is used for the second wiring layer in the present embodiment, the present invention is not limited thereto and a transition metal such as Ti, Cu, Co or Ta or an alloy of these metals containing tungsten, or an oxide or nitride showing conductivity may be used alternatively.

Then, as shown in FIG. 46, the laminated-layer structure is processed and formed to be in the shape of a line by the well-known dry etching method through the resist as a mask patterned by the well-known photolithography method so as to become the second wiring. In this processing of the second wiring layer, the process is performed to reach the variable resistor 77 and the lower electrode 76. After being processed in such a manner, the variable resistor becomes a shape of a rectangle. Thereafter, an interlayer insulation film is formed and a flattening step is performed according to need, whereby the desirable nonvolatile semiconductor memory device can be manufactured.

As the manufacturing method to implement the present embodiment has been described above, when the present embodiment is combined with the first embodiment, the three-dimensional memory cell array as shown in FIG. 47 can be provided.

In addition, as a variation of the present embodiment, as shown in FIG. 48, a P layer 80 may be formed instead of the N− layer 73. The P layer 80 can be formed by the ion implantation similar to the N+ layer. In this way, a PN junction diode is formed instead of the Schottky barrier diode, thereby the preferable device characteristics having less sneak path current can be obtained.

In addition, although the description has been made of the case where the memory cell having the variable resistive element showing the bipolar switching characteristics by itself is manufactured in the above embodiment, for example, when the memory cell having the variable resistive element not showing the bipolar switching characteristics by itself is manufactured, as shown in FIG. 49, the lower electrode 82 is formed of Cu, the variable resistor 83 is formed of CuO by oxidizing Cu, and the upper electrode 84 is formed of Ti, Ta, W, or the like. Furthermore, in this case, it is necessary to insert a metal electrode 81 having a relatively large work function such as Pt, Co, Ni, or the like between the lower electrode 82 and the N− layer 73, as a metal electrode to form the Schottky barrier diode. In addition, in the case of the above memory cell, the conductivity types of the silicon substrate and the implanted ion can be inverted, and in this case, it is necessary to insert a metal electrode 81 having a relatively small work function such as Ti, Ta, W, or the like between the lower electrode 82 and the N− layer 73, as an electrode to form the Schottky barrier diode.

Third Embodiment

A description will be made of a third embodiment (hereinafter occasionally referred to as the “present embodiment”) according to the manufacturing method of the device of the present invention, with reference to FIGS. 50 to 60. FIG. 50 is a schematic view showing a memory cell formed in the present embodiment, and FIG. 51 is a plan view showing the memory cell. The device of the present invention to be manufactured in the present embodiment is configured by a first wiring including a W layer and a TiN adhesive layer, a memory cell portion including a TiN barrier metal, a TiN-type polysilicon resistance lowering layer, a TiN lower electrode and a TiON variable resistor, and a second wiring including an upper electrode, a adhesive layer and a W layer. In addition, FIGS. 52 to 58 show the manufacturing method of the present embodiment in the order of steps. In FIGS. 52 to 58, figures A each show a vertical sectional view taken along line X-X′ in FIG. 51, and figures B each show a vertical sectional view taken along line Y-Y′ in FIG. 51. In addition, although a single memory cell is shown in FIG. 50 to simplify the figure, a plurality of memory cells are actually arranged in the X direction and the Y direction with or without regular intervals.

In addition, also in the present embodiment, similar to the first embodiment, a description will be made of a case where the unipolar switching operation is implemented by applying a voltage whose polarity is positive at the upper electrode with respect to the lower electrode.

First, as shown in FIG. 52, a tungsten layer 93 serving as a first wiring is formed on an insulation film 91, formed of SiO2 or the like, overlying on a substrate made of silicon or the like through a adhesive layer 92 composed of TiN or the like. Although tungsten is used for a first wiring in the present embodiment, the present invention is not limited thereto and a transition metal such as Ti, Cu, Co or Ta, or an alloy of these metals containing tungsten, or oxide or nitride showing conductivity may be used alternatively. In addition, although TiN is used for the adhesive layer 92 in the present embodiment, the present invention is not limited thereto and TaN or TiW may also be used alternatively. The TiN adhesive layer 92 and the tungsten first wiring 93 are formed by a well-known method such as the CVD method or the sputtering method. The film thickness of the TiN adhesive layer is about 30 nm, and the film thickness of the tungsten first wiring is about 200 nm. In addition, the adhesive layer 92 may be deposited depending on the kind of the metal used in the first wiring 93 and the adhesive layer 92 is not necessarily an indispensable layer.

After the tungsten layer 93 has been formed, the memory cell portion is formed. First, a TiN layer as a barrier metal 94 and a Ti layer as a resistance lowering layer 95 are formed to be 30 nm and 10 nm in thickness, respectively. The barrier metal layer is formed in order to prevent the reaction between a polysilicon layer to be formed above and tungsten of the first wiring, and the resistance lowering layer is formed in order to reduce the adhesive resistance with the polysilicon layer to be formed above. Although TiN is used for the barrier metal 94 in the present embodiment, the present invention is not limited thereto and TaN or TiW may also be used. In addition, Ti is used for the resistance lowering layer 95 in the present embodiment, the present invention is not limited thereto and Co or Ni may also be used.

Further, an N-type polysilicon layer 96 serving as a component of a Schottky barrier diode is then formed by the well-known LPCVD method. According to this method, the N-type polysilicon layer is formed by mixing a dopant that becomes an N type such as PH3 while the polysilicon layer is formed. As an alternative method, a solid-phase diffusion method or a method for forming the N type by use of ion implantation may be used. In addition, a method for polycrystallizing an amorphous layer by a heat treatment may be used.

Thus, the dopant concentration of the formed N-type polysilicon layer is about 5×1018 atoms/cm3, and the film thickness thereof is 150 nm. Further, a TiN layer serving as a metal side electrode of the Schottky barrier diode and a lower electrode 97 of the variable resistor is formed to be 100 nm in thickness. Since this TiN layer is removed a little in the later step of flattening an insulation film, the film thickness thereof needs to be set in view of an amount of the removal. In addition, while the TiN layer combines the metal side electrode of the Schottky barrier diode and the lower electrode of the variable resistor, another material having a relatively large work function such as Pt, Co, Ni, or the like may be inserted as the metal side electrode of the Schottky barrier diode.

Then, as shown in FIG. 53, the laminated-layer structure is processed and formed into the shape of a line so as to become the first wiring and the memory cell portion by the well-known dry etching method using a resist as a mask patterned by the photolithography method. The wiring width and the wiring interval at this time are set to about 130 nm.

Then, as shown in FIG. 54, an SiO2 insulation film 98 is formed on the first wiring and between the wirings. The SiO2 film is formed by the plasma CVD method or the HDPCVD method. Since the SiO2 layer is flattened by polishing in the later CMP step, the film thickness of the SiO2 layer needs to be at least thicker than the first wiring. In the present embodiment, the SiO2 layer is formed to be 700 nm in thickness.

Then, as shown in FIG. 55, the SiO2 layer is polished by the well-known CMP method to remove the SiO2 layer on the first wiring and the memory cell portion and flatten the layer. Since it is necessary to expose the TiN surface by completely removing the SiO2 layer on the first wiring, the TiN layer positioned uppermost layer of the memory cell portion is also polished, but since the polishing rate of SiO2 to TiN is high enough (about 10 or more), a polished thickness of the TiN layer is considerably smaller than the formed thickness of the layer.

Then, as shown in FIG. 56, a TiON layer serving as a variable resistor 99 is formed by oxidizing the exposed surface of the TiN layer. According to the present embodiment, the variable resistor is formed by being held in an atmosphere of atmospheric-pressure oxygen containing 10% by weight of ozone at a substrate temperature of 300° C. for 10 minutes. At this time, the film thickness of the variable resistor is about 10 nm. However, the method for forming the variable resistor is not limited thereto, and the conditions can be changed within a range of 5 to 100% by weight of ozone concentration, and 250 to 500° C. of the substrate temperature. In addition, as an alternative method, a heat treatment in a reduced-pressure oxygen atmosphere or an oxygen plasma atmosphere, or the oxidizing method using an oxidizing chemical solution can be used.

Then, as shown in FIG. 57, a TiN layer serving as a adhesive layer 100 of a second wiring layer and a tungsten layer serving as a second wiring layer 101 are formed. The adhesive layer 100 functions not only as the adhesive layer of the second wiring layer 101 but also as an upper electrode of the variable resistor 99. Although tungsten is used for the second wiring layer similar to the first wiring in the present embodiment, the present invention is not limited thereto and a transition metal such as Ti, Cu, Co or Ta or an alloy of these metals containing tungsten, or an oxide or nitride showing conductivity may also be used.

Then, as shown in FIG. 58, the laminated-layer structure is processed by the well-known dry etching method through the resist as a mask patterned by the well-known photolithography method so as to become the second wiring and the memory cell portion. At this time, the process is performed to reach the TiN layer serving as the barrier metal 94 on the first wiring. The wiring width and the wiring interval at this time are about 130 nm. Thereafter, an interlayer insulation film is formed and a flattening step is performed according to need, whereby the desired nonvolatile semiconductor memory device can be manufactured.

The memory cells formed as described above are structured on the upper wiring layer (on the second wiring in the present embodiment) repeatedly, whereby a three-dimensional memory array having the same structure as shown in FIG. 33 can be built and the semiconductor memory device having the highly integrated variable resistive elements can be manufactured.

In addition, also in the present embodiment, similar to the first embodiment, a P-type polysilicon 102 may be formed at a part where the N-type polysilicon 96 is in contact with the lower electrode 97 by ion implantation from the oblique direction (refer to FIG. 59), and a P-type polysilicon layer 103 may be inserted between the N-type polysilicon layer 96 and the lower electrode 97 (refer to FIG. 60).

Furthermore, when the memory cell having the variable resistive element not showing the bipolar switching characteristics by itself is manufactured, similar to the first embodiment, the polysilicon layer 96 can have either N-type or P-type conductivity. In this case, the lower electrode 97 is formed of Cu, the variable resistor 99 is formed of CuO by oxidizing Cu, and the upper electrode 100 is formed of Ti, Ta, W, or the like. In this case also, a metal electrode is inserted between the polysilicon layer and the lower electrode 97 to form the Schottky barrier diode, depending on the conductivity type of the polysilicon layer 96.

INDUSTRIAL APPLICABILITY

The present invention can be used in a nonvolatile semiconductor memory device comprising a variable resistive element resistive characteristics of which change as result of voltage application, and, in particular, is effective in implementation of the nonvolatile semiconductor memory device capable of high-speed switching operations to the variable resistive element in a stable manner.

INVENTORS:

Sato, Shinichi, Tanaka, Kenichi, Awaya, Nobuyoshi, Hosoi, Yasunari, Yamazaki, Shinobu

THIS PATENT IS REFERENCED BY THESE PATENTS:
Patent Priority Assignee Title
THIS PATENT REFERENCES THESE PATENTS:
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