Integrated circuit for clock generation for memory devices

Abstract

A device for generating clock signals for use with a plurality of ddr memory devices on a dual in-line memory module (dimm) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK32) at respective data outputs of the plurality of flip-flops. A multiplexer commonly coupled to the data outputs of the flip-flops selects one of the shifted clock signals (CLK 21, . . . , CLK32) to serve as an output clock signal for transmission of the buffered data to a memory device.

Description

This patent application claims priority from German Patent Application No. 10 2007 020 005.8, filed 27 Apr. 2007, and from U.S. Provisional Patent Application No. 61/016,674, filed 26 Dec. 2007.

FIELD OF THE INVENTION

The invention relates to an integrated electronic device for generating clock signals for FIG. 2 shows a simplified block diagram of the clocking circuit of FIG. 1; FIG. FIGS. 1 shows a and 2 show simplified block diagram diagrams of an example implementation of an interface integrated circuit (IC) 100 in accordance with an embodiment of the invention. A data input receives data from a memory controller or the like (not shown). The input data D-IN applied at data input terminal has a bus width of N2. A clock input CLK receives a first clock signal CLK1 in the form of a high speed clock. The input data D-IN comprises all kinds of data, address information and control information to be exchanged with memory modules or ICs 902-1 to 902-8 that are secured on a DIMM board or circuit board 906 and are in communication with an interface IC or module 100 (as shown in FIG. 10). The first clock signal CLK1 is divided by a clock divider 202 in block DIV-SH clocking circuit 102 to derive a second clock signal CLK20 (not shown in FIG. 1) having a lower frequency. The frequency of the first clock signal CLK1 will typically be an integer multiple of the frequency of the second clock signal CLK20. Block DIV-SH Clocking circuit 102 also includes an internal shift register 204 (which may be similar to those described below in connection with FIGS. 2 and 3 and 4). The shift register 204 provides a plurality of phase-shifted derivatives of the second clock signal, a selected one of which may be chosen in response to applied selection signals SEL of bus width N1 by way of multiplexer 206 (an example of which can be seen in greater detail in FIG. 9). Clock signals CLKXY and CLK-OUT have the specific phase of one (or more in the case of a bus) of the phase-shifted derivatives of clock signal CLK20, determined according to the applied selection signals SEL.

Clock signal CLKXY is used as a core clock. Signal CLKXY has the same frequency as CLK20 and a specific phase relationship with respect to clock signals CLK20 and CLK1. The phase of signal CLKXY is selected by one or more of the selection signals SEL. Also, the phase-shifted clock signals at the output pins CLK_OUT of bus width M are selected by selection signals SEL. The block designated by DIGL represents various additional digital logic, buffers or combinatorial logic which may be coupled between the input D-IN and an output buffer BUF2 104. The bus width for data, command and address signals will vary according to the specific architecture of a particular implementation. Thus, the reference numbers N1, N2, N3, N4 and M represent different possible bus width combinations.

FIG. 2 3 shows in more detail an example implementation of a shift register 204-1 of the type implemented in block DIV-SH clocking circuit 102. The second clock signal CLK20 is fed as an input signal to the data input D of a first flip-flop FF1 302-1. The first clock signal CLK1, with a frequency that is an integer multiple of the frequency of the second clock signal CLK20, is fed to the clock inputs of the flip-flops 302-1 to 302-4. The flip-flops FF1, FF2, FF3 and FF4 302-1 to 302-4 are coupled in typical shift register configuration, with the output Q of each preceding flip-flop (e.g., Q of FF1 flip-flop 302-1) coupled to the data input D of each following flip-flop (e.g., D of FF2 flip-flop 302-2). In this way, a number of phase-shifted clock signals CLK21, CLK22, CLK23 and CLK24 are produced, each being shifted by one clock cycle with respect to a preceding clock signal.

FIG. 3 4 shows a simplified schematic of a differential shift register 204-2 implementation according to an example embodiment of the invention. The differential shift register comprises six flip-flops FF1 to FF6 402-1 to 402-6. All flip-flops 402-1 to 402-6 receive differential clock signals CLK1 and CLK1Z, where signal CLK1Z is the inverted version of signal CLK1. (A “Z” used at the end of the reference legend of a signal indicates the inverted form of the signal without the “Z”). The frequency of differential clock signals CLK20, CLK20Z is substantially smaller than the frequency of CLK1, CLK1Z. In the present embodiment, the frequency of signal CLK1 may, e.g., be six times the frequency of signal CLK20. Signal CLK20 can be derived from signal CLK1 in known ways using a clock divider 202. The circuit shown in FIG. 3 4 serves to provide twelve derivative clock signals CLK21- to CLK32 of the slower clock signal CLK20. Flip-flops FF1, FF2 and FF3 402-1 to 402-3 are clocked by the rising edge of signal CLK1, whereas FF4, FF5 and FF6 flip-flops 402-4 to 402-6 are clocked by the falling edge of signal CLK1 (i.e., the rising edge of CLK1Z). This is achieved by simply interchanging the differential clock signals CLK1, CLK1Z at the clock inputs of the two groups of flips-flops. An additional inverter is not needed. Therefore, e.g., for DDR applications, using differential clock signals, such as signals CLK1 and CLK1Z, in a fully differential approach without an inverter is particularly useful. The propagation delay of even a single inverter (or any other single gate) would introduce additional and unwanted phase shift in the range of several percent of the period of the clock signals. Because the rising and falling edges of the fast signal CLK1 are used, the derivatives derivative signals CLK21-CLK32 are shifted with respect to each other by half the period of signal CLK1 (½ UI). So, the granularity of the phase shifter is reduced to ½ UI of the fast clock signal CLK1.

Preferably, signal CLK20 may be inverted before being fed to the input of the phase shifter 204-2 shown in FIG. 3 4. This may be helpful to compensate for the delays (including setup and hold times and propagation delays, etc.) of the flip-flops. The phase shifter 204-2 shown in FIG. 3 4 may preferably be used in the DIV-SH stage clocking circuit 102 shown in FIG. 1. The phase shifter 204-2 may be adapted to accommodate different numbers of phase-shifted clock derivatives, as needed.

FIG. 4 shows a simplified schematic FIGS. 5 and 6 show diagrams of a configuration used in prior art electronic devices for double data rate data output. In the memory buffer, the data to be written to the memory devices (is to be stored in a write first-in-first-out (FIFO) for the different memory buffer applications. There are typically two banks 502 and 504 of write first-in first-out ( FIFO) buffers FF03 and FFE3 602 and 604, which run from the core clock CLKO and the inverted core clock CLKE. The data stored in FF03 buffers 602 and 604 and FFE3 is alternately fed by multiplexer MUX 606 to the output pin (or pins) D_DDR by a core clock CLKR having twice the frequency of the clock signals CLKO and CLKE used for the FIFOs. Therefore, the approach shown in FIG. 4 FIGS. 5 and 6 requires an additional clock at twice the frequency of the core clock rate and adds latency.

FIG. 5 7 shows a simplified block diagram of an example flip-flop 700 according to an aspect of the invention for the data buffer 104 that can be used to form a write FIFO circuit. As with the conventional approach shown in FIG. 4, two complementary clock signals CLK_EVEN and CLK_ODD are fed to the flip-flop FFD 700. Further, corresponding data signals D_EVEN and D_ODD are supplied to the flip-flop 700. In the example implementation according to the invention, the flip-flop 700 (or additional circuitry) generates two non-overlapping clock signals CLK3 and CLK4 as illustrated by the waveforms below the flip-flop, and the data D_EVEN and D_ODD is source centered with respect to either signals CLK3 or CLK4.

FIG. 6 8 shows a more detailed schematic of the flip-flop 700 of FIG. 5 7. The first master stage 704-1 includes two transmission gates T1 and T3 712-1 and 712-2 being clocked by respective clock signals CKT1, CKT1Z, where signal CKT1Z is the inverted clock with respect to signal CKT1. Further, the first master stage 704-1 includes inverters INV1 inverter 708-1 and clocked inverter INV1C or tri-state inverter 710-1. The second master stage 704-2 includes the two transmission gates T0, T2 712-4 and 712-3 and inverter INV2 708-2, as well as clocked inverter INV2C 710-2. The slave stage 706 includes inverters INV3 inverter 708-3 and clocked inverter INV3C 710-3. The slave stage 706 is coupled to the outputs of both master stages 704-1 and 704-2 via transmission gates T3 and T2 712-2 and 712-3. The master stages 704-1 and 704-2 receive respective data signals D1 and D0, one being the even, the other being the odd data as explained with respect to FIG. 5 7. Accordingly, the first master stage 704-1 stores the data received via input pin D1 and the second master stage 704-2 stores the data received via input pin D0. The clock signals CKT1, CKT1Z, CKT0, CKT0Z may be derived in known ways from the third and the fourth clock signals CLK3 and CLK4 shown in FIG. 5 7 using control circuit 702. Further, an inverted version signal Zc1RZ of the clock signal c1RZ is produced by inverter INV4 708-6. Inverters INV5-INV8 708-4, 708-5, 708-7 and 708-8 are used for clock signals CKT1, CKT1Z, CKT0, CKT0Z.

With respect to the prior art circuit shown in FIG. 4 FIGS. 5 and 6, the flip-flop implementation 700 according to the invention saves a considerable amount of chip area. Each of the flip-flops shown in FIG. 5 700 includes at least a master and a slave stage. The invention provides the same, or even a better functionality in terms of speed and power dissipation, and saves the multiplexer, the control logic and signals for the multiplexer and a slave stage.

FIG. 7 9 shows an example of a multiplexer 206 that employs tri-state buffer buffers or inverters 702-1 to 702-5 according to the invention. The clock signals CLK20, CLK21, CLK22, CLK23 and CLK24 are supplied, respectively, to a number of tri-state buffers 802-1 to 802-5, each having a corresponding selection input SEL20, SEL21, SEL22, SEL23 and SEL24. The output signal CLK_OUT is selected from the phase-shifted clock input signals CLK20- to CLK24 in response to the applied selection signals. The unselected tri-state buffers of the clock signals which are not selected (i.e., 802-1) can be set in a high impedance state. The tri-state buffer multiplexer 206 may preferably be used in the DIV-SH block of FIG. 1 clocking circuit 102. The tri-state buffer may be adapted to any specific number of phase-shifted derivatives of the clock signals.

Those skilled in the art to which the invention relates will appreciate that the described implementations are merely representative examples, and that many other implementations are possible within the scope of the claimed invention.

Claims

1. A device for generating clock signals in association with a plurality of double data rate (ddr) memory devices on a dual in-line memory module (dimm) board, the electronic device comprising:

a data buffer for buffering data;

a clock divider for dividing a first clock signal having a first clock frequency to generate a second clock signal having a second clock frequency, the second clock frequency being an integer multiple of the first clock frequency;

a shift register coupled to receive the second clock signal as a data input signal;, the shift register comprising a plurality flip-flops having clock inputs coupled to receive the first clock signal, and being further coupled so that a data output of a preceding flip-flop is coupled to a data input of a following flip-flop so as to shift the second clock signal through the shift register in response to the first clock signal, thereby generating a plurality of shifted clock signals at the respective data outputs of the plurality of flip-flops; and

a multiplexer commonly coupled to the data outputs of the flip-flops for selecting a shifted clock signal to serve as an output clock signal for transmission of the buffered data to a memory device.

2. The device of claim 1, wherein the first clock signal is a differential clock signal and the plurality of flip-flops are coupled to be clocked by the differential first clock signal.

3. The device of claim 1, wherein the second clock signal is a differential clock signal and the plurality of flip-flops are coupled to process the second clock signal as a differential data signal.

4. The device of claim 1, wherein a first group of the flip-flops is coupled to operate in response to a rising edge of the first clock signal, and a second group of the flip-flops is coupled to operate in response to a falling edge of the first clock signal. by coupling the second group of flip-flops.

5. The electronic device of claim 1, further comprising a clock generator for recovering the first clock signal from input data.

6. The device of claim 1, further comprising;:

circuitry for generating a third clock signal and a fourth clock signal from the first clock signal;, wherein the third clock signal and the fourth clock signal are non-overlapping with respect to each other;

a flip-flop circuit comprising a first master stage for storing a first binary value in response to the third clock signal and a second master stage for storing a second binary value in response to the fourth clock signal; and *a slave stage coupled to the first and the second master stages, to receive and to store either a first or the second binary value in response to a fifth clock signal having twice the frequency of an input clock.

7. A system for digital data processing, comprising at least one dimm board having multiple memory modules and a device for generating clock signals in association with a plurality of ddr memory devices on a dual in-line memory module ( dimm) board, the device comprising:

a data buffer for buffering data;

a clock divider for dividing a first clock signal having a first clock frequency to generate a second clock signal having a second clock frequency, the second clock frequency being an integer multiple of the first clock frequency;

a shift register coupled to receive the second clock signal as a data input signal;, the shift register comprising a plurality flip-flops having clock inputs coupled to receive the first clock signal, and being further coupled so that a data output of a preceding flip-flop is coupled to a data input of a following flip-flop so as to shift the second clock signal through the shift register in response to the first clock signal, thereby generating a plurality of shifted clock signals at the respective data outputs of the plurality of flip-flops; and

a multiplexer commonly coupled to the data outputs of the flip-flops for selecting a shifted clock signal to serve as an output clock signal for transmission of the buffered data to a memory device.

8. A method for generating clock signals for a plurality of memory modules on a dimm board, comprising:

buffering input data to be transferred to the memory modules;

dividing a first clock signal to derive a second clock signal; and

deriving a plurality of additional clock signals from the second clock signal by sequentially shifting the second clock signal according to timing established by at least one of the rising edges and falling edges of the first clock signal.

9. The method of claim 8, wherein the method further comprises selecting at least one of the plurality of additional clock signals to produce a selected clock signal.

10. The method of claim 8, wherein the method further comprises clocking the input data that has been buffered with the selected clock signal.