Integrated circuit having oversized components and method of manufacture thereof

Integrated circuit having oversized components and method of manufacture thereof
RE45507

An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.

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Patent RE45507
Priority Feb 12 2002
Filed Nov 20 2013
Issued May 05 2015
Expiry Feb 12 2022
Inventors Contopanag…
Assg.orig Broadcom C…
Assg.curr Broadcom C…
Entity unknown
Referenced by 0
References 24
Maint.: EXPIRED

TECHNICAL FIELD OF T…
BACKGROUND OF THE IN…
SUMMARY OF THE INVEN…
BRIEF DESCRIPTION OF…
DETAIL DESCRIPTION O…

1. A method for manufacturing an integrated circuit comprises:

creating a layer; and

creating, on the layer, an electrical element having a geometric shape that exceeds prescribed integrated circuit manufacture limits, wherein the electrical element includes at least one non-conducting region that negligibly effects electrical characteristics of the electrical element and provides adequate non-conducting spacing in accordance with the prescribed integrated circuit manufacture limits.

0. 13. A method for manufacturing an integrated circuit comprising:

creating a layer; and

creating, on and within the layer, an electrical element having a geometric shape that exceeds prescribed integrated circuit manufacture limits, wherein the electrical element includes at least one non-conducting region that negligibly effects electrical characteristics of the electrical element and provides adequate non-conducting spacing in accordance with the prescribed integrated circuit manufacture limits.

0. 28. A method for manufacturing an integrated circuit comprising:

creating a dielectric layer; and

creating, on and within an etched portion of the dielectric layer, an electrical element having a geometric shape that exceeds prescribed integrated circuit manufacture limits, wherein the electrical element includes at least one non-conducting region that negligibly effects electrical characteristics of the electrical element and provides adequate non-conducting spacing in accordance with the prescribed integrated circuit manufacture limits.

2. The method of claim 1 further comprises:

creating the at least one non-conducting region as at least one of: a slit within the electrical element, a series of slits within the electrical element, a hole within the electrical element, and or a series of holes within the electrical element.

3. The method of claim 1, wherein the creating the electrical element further comprises:

creating the electrical element as at least one turn of an inductor.

4. The method of claim 3 further comprises:

creating a second layer;

creating, on the second layer, a second electrical element having a second geometric shape that exceeds the prescribed integrated circuit manufacture limits, wherein the second electrical element includes at least one non-conducting second region, wherein the second electrical element constitutes at least one other turn of the inductor; and

coupling the at least one turn to the at least one other turn in parallel or in series.

5. The method of claim 1 further comprises:

creating the electrical element as a plate of a capacitor;

wherein creating the layer comprises creating a dielectric layer, wherein comprising a first major surface of the dielectric layer that is juxtaposed to a major surface of the plate; and

creating a second electrical element as a second plate of the capacitor, wherein the second electrical element has a geometric shape that exceeds the prescribed integrated circuit manufacture limits, wherein a major surface of the second plate is juxtaposed to a second major surface of the dielectric layer, and wherein the second electrical element includes at least one non-conductive region that negligibly effects electrical characteristics of the capacitor and provides adequate non-conducting spacing in accordance with the prescribed integrated circuit manufacture limits.

6. The method of claim 5 further comprises:

creating a second dielectric layer, wherein a first major surface of the second dielectric layer is juxtaposed to a second major surface of the second plate;

creating a third electrical element as a third plate of the capacitor, wherein the third electrical element has a geometric shape that exceeds the prescribed integrated circuit manufacture limits, wherein a major surface of the third plate is juxtaposed to a second major surface of the second dielectric layer, and wherein the third electrical element includes at least one non-conductive region that negligibly effects electrical characteristics of the capacitor and provides adequate non-conducting spacing in accordance with the prescribed integrated circuit manufacture limits; and

connecting the electrical element to the third electrical element.

7. The method of claim 1 further comprises:

creating the electrical element as an electromagnetic shield.

8. The method of claim 1 further comprises:

creating the electrical element as a ground plane.

9. The method of claim 1 further comprises:

creating the electrical element as a power source trace.

10. The method of claim 1 further comprises:

creating the electrical element as at least one of: a gate of a transistor, a source of the transistor, and or a drain of the transistor.

11. The method of claim 1 further comprises:

creating the electrical element as an antenna.

0. 12. The method of claim 1, wherein the at least one non-conducting region is formed within the geometric shape.

0. 14. The method of claim 13, further comprising creating the at least one non-conducting region as at least one of:

a slit within the electrical element, a series of slits within the electrical element, a hole within the electrical element, or a series of holes within the electrical element.

0. 15. The method of claim 13, wherein the creating the electrical element further comprises:

creating the electrical element as at least one turn of an inductor.

0. 16. The method of claim 15, further comprising:

creating a second layer;

creating, on and within the second layer, a second electrical element having a geometric shape that exceeds the prescribed integrated circuit manufacture limits, wherein the second electrical element includes at least one non-conducting second region, wherein the second electrical element constitutes at least one other turn of the inductor; and

coupling the at least one turn to the at least one other turn in parallel or in series.

0. 17. The method of claim 13, further comprising:

creating the electrical element as a plate of a capacitor;

wherein creating the layer comprises creating a dielectric layer comprising a first major surface that is juxtaposed to a major surface of the plate; and

0. 18. The method of claim 17, further comprising:

creating a second dielectric layer, wherein a first major surface of the second dielectric layer is juxtaposed to a second major surface of the second plate;

connecting the electrical element to the third electrical element.

0. 19. The method of claim 13, further comprising:

creating the electrical element as an electromagnetic shield.

0. 20. The method of claim 13, further comprising:

creating the electrical element as a ground plane.

0. 21. The method of claim 13, further comprising:

creating the electrical element as a power source trace.

0. 22. The method of claim 13, further comprising creating the electrical element as at least one of:

a gate of a transistor, a source of the transistor, or a drain of the transistor.

0. 23. The method of claim 13, further comprising:

creating the electrical element as an antenna.

0. 24. The method of claim 13, further comprising using a dielectric layer as the layer.

0. 25. The method of claim 13, further comprising determining the prescribed integrated circuit manufacture limits.

0. 26. The method of claim 13, wherein the creating the electrical element comprises creating the electrical element partially within the layer.

0. 27. The method of claim 13, wherein the at least one non-conducting region is formed within the geometric shape.

0. 29. The method of claim 28, further comprising creating the at least one non-conducting region as at least one of:

a slit within the electrical element, a series of slits within the electrical element, a hole within the electrical element, or a series of holes within the electrical element.

0. 30. The method of claim 28, wherein the creating the electrical element further comprises:

creating the electrical element as at least one turn of an inductor.

0. 31. The method of claim 30, further comprising:

creating a second dielectric layer;

creating, on and within an etched portion of the second dielectric layer, a second electrical element having a geometric shape that exceeds the prescribed integrated circuit manufacture limits, wherein the second electrical element includes at least one non-conducting second region, wherein the second electrical element constitutes at least one other turn of the inductor; and

coupling the at least one turn to the at least one other turn in parallel or in series.

0. 32. The method of claim 28, further comprising:

creating the electrical element as a plate of a capacitor;

wherein a first major surface of the dielectric layer is juxtaposed to a major surface of the plate; and

0. 33. The method of claim 32, further comprising:

creating a second dielectric layer, wherein a first major surface of the second dielectric layer is juxtaposed to a second major surface of the second plate;

connecting the electrical element to the third electrical element.

0. 34. The method of claim 28, further comprising:

creating the electrical element as an electromagnetic shield.

0. 35. The method of claim 28, further comprising:

creating the electrical element as a ground plane.

0. 36. The method of claim 28, further comprising:

creating the electrical element as a power source trace.

0. 37. The method of claim 28, further comprising creating the electrical element as at least one of:

a gate of a transistor, a source of the transistor, or a drain of the transistor.

0. 38. The method of claim 28, further comprising:

creating the electrical element as an antenna.

0. 39. The method of claim 28, further comprising determining the prescribed integrated circuit manufacture limits.

0. 40. The method of claim 28, wherein the creating the electrical element comprises creating the electrical element partially within the layer.

0. 41. The method of claim 28, wherein the at least one non-conducting region is formed within the geometric shape.

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to integrated circuits and more particularly to components that comprise an integrated circuit.

BACKGROUND OF THE INVENTION

The general structure of an integrated circuit is known to include one or more dielectric layers on a substrate. As is further known, each of the dielectric layers supports a metal layer, which is etched or deposited to form integrated circuit components such as resistors, capacitors, inductors, transistors, conductive traces, et cetera. The number of dielectric layers, and hence the number of metal layers, along with acceptable physical dimensions of the dielectric layers and metal layers are dictated by the particular type of integrated circuit technology and the corresponding integrated circuit fabrication rules. For example, a CMOS integrated circuit may include multiple dielectric layers and multiple corresponding metal layers. Depending on the particular foundry rules, the size of each dielectric layer and corresponding metal layers have prescribed minimum and maximum dimensions. In addition, such foundry rules prescribe maximum dimensions for metal tracks formed on the metal layers. For instance, the maximum metal track may be 30-40 microns for a given CMOS process. As is known, IC foundries provide the maximum metal track dimensions to prevent over-stressing the integrated circuit and/or to ensure reliability of fabrication.

As is also known, integrated circuit foundries provide minimum spacing between metal tracks. For example, the minimum spacing may be 1.0 microns to 3.0 microns and may further be dependent on the particular metal layer the track is on and/or the width of adjacent tracks.

Such foundry rules limit the ability to design certain on-chip components. For instance, on-chip inductors designed using CMOS technologies are limited to a quality factor (i.e., Q factor which=2(pi)fL/R, where R=the effective series resistance, L=the inductance and f is the operating frequency) of about 5 to 8 at frequencies of 2.5 gigahertz. Such a low quality factor is primarily due to a significant effective series resistance at 2.5 gigahertz. As is further known, the effective series resistance is dependent on the operating frequency of the component and is further dependent on the size of the metal track. As such, by limiting the size of metal tracks, the quality factor of inductors is limited to low values.

Capacitance values of on-chip metal insulated metal capacitors are also limited due to the foundry rules. As is known, the capacitance of a capacitor is based on the area of its plates, the distance between the plates, and the dielectric properties of the dielectric material separating the plates. Since the foundry rules limit the size of the plates, the capacitor values are limited, which, in turn, limit the uses of on-chip capacitors.

Therefore, a need exists for a technique to increase the effective size of metal tracks while maintaining compliance with foundry metal track rules and to allow for greater range of design of on-chip integrated circuit components.

SUMMARY OF THE INVENTION

These needs and others are substantially met by the integrated circuit described herein. Such an integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element, which may be a winding(s) of an inductor, power source trace, gate of a transistor, source of a transistor, drain of a transistor, plate of a capacitor, resistor, electromagnetic shield, ground plane et cetera, has a geometric shape that exceeds prescribed integrated circuit manufacturing limits. For example, if the integrated circuit manufacturing limits prescribe metal tracks not to exceed 35 microns in width or length, the electrical element of the present invention has a dimension in width and length that exceeds 35 microns. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. For instance, the electrical element may be fabricated to include a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate a top and side view of an electrical element in accordance with the present invention;

FIG. 2 illustrates a graphical representation of a non-conducting region of an electrical element in accordance with the present invention;

FIG. 3 illustrates a graphical representation of an alternate non-conducting region of an electrical element in accordance with the present invention;

FIG. 4 illustrates a graphical representation of yet another non-conducting region of an electrical element in accordance with the present invention;

FIG. 5 illustrates a graphical representation of an on-chip inductor in accordance with the present invention;

FIGS. 6A, B and C illustrate top, side, and bottom views of a capacitor in accordance with the present invention; and

FIG. 7 illustrates a logic diagram of a method for manufacturing an integrated circuit in accordance with the present invention.

DETAIL DESCRIPTION OF A PREFERRED EMBODIMENT

FIGS. 1A and B illustrate top and side view of an integrated circuit 10 that includes an electrical element 12 created on a dielectric layer 14. The electrical element 12 may be used as at least one turn of an inductor, as one plate of a capacitor, as an electromagnetic shield, as a ground plane, as a power source trace, as a gate of a transistor, a source of a transistor, a drain of a transistor, or as an antenna.

The electrical element 12 includes a non-conducting region 16. As shown, the electrical element 12 has a dimension from end-to-end that is greater than integrated circuit (IC) manufacturing limits. The non-conducting region 16, which may be a single hole, is spaced at dimensions that are less than IC manufacturing limits. For instance, if the manufacturing limits for a CMOS process is 35 microns, the overall dimension of electrical element 12 exceeds the 35 microns. For instance, the width of the electrical element may be at least 50 microns when the electrical element 12 is used for an inductor. To provide compliance with IC manufacturing limits, the non-conducting region 16, which may be a hole having a dimension that corresponds to minimum spacing distances for the IC foundry rules, is included within the electrical element 12 such that the IC manufacturing limits are met. For instance, if the foundry rules provide that 1-3 microns are needed for spacing between metal tracks, the non-conducting region would have a diameter of 1-3 microns. In the example of an inductor, if the width of the electrical element 12 is 50 microns, by placing the non-conducting region in the middle, (i.e., at 25 microns) with respect to each end of the electrical element, the IC manufacturing limits of 35 microns for metal tracks are substantially met.

By providing the non-conducting region 12 within an electrical element 12 that exceeds IC manufacturing limits, components, such as inductors, capacitors, resistors, ground planes, electromagnetic shields, power source traces, transistors, and/or antennas may be fabricated on-chip in sizes and/or having electrical characteristics that were previously unobtainable. For instance, an on-chip CMOS inductor may be derived that has a quality factor of 12 or more utilizing the concepts generally depicted in FIG. 1.

FIGS. 2 through 4 illustrate alternate embodiments for fabricating the non-conducting region 16. FIG. 2 illustrates the electrical element 12 that includes a plurality of holes spaced to provide the non-conducting region 16. In this embodiment, the electrical element 12 has a height and width that both exceed the IC manufacturing limits (e.g., 35 microns for metal tracks). As such, the series of holes are spaced at dimensions less than the IC manufacturing limits and have a diameter that equals, or slightly exceeds the prescribed spacing requirements between metal tracks for a particular foundry rule.

FIG. 3 illustrates the electrical element 12 that includes a slit for the non-conducting region 16. The length of the slit is dependent on the width of the electrical element 12. The width of the non-conducting region 16 corresponds to the prescribed foundry rules regarding spacing between metal tracks. Accordingly, the slit may be fabricated to have varying widths depending on the width of the electrical element 12.

FIG. 4 illustrates the electrical element 12 that includes the non-conducting region 16, which includes a plurality of slits. In this embodiment, the electrical element 12 substantially exceeds the IC manufacturing limits regarding metal track dimensions in both height and width. By spacing the slits at dimensions that are less than the IC manufacturing limits, the IC manufacturing limits are substantially met. As such, the electrical elements 12 as depicted in FIGS. 1 through 4, are compliant with IC manufacturing foundry rules yet provide substantially larger conductive areas and where the size of the non-conducting region 16 has negligible effects on the electrical characteristics of the electrical element 12.

FIG. 5 illustrates an on-chip inductor 20 that includes the electrical element 12 fabricated as at least one turn of the on-chip inductor 20. The electrical element 12 has a width that exceeds the IC manufacturing limits but has a plurality of non-conducting regions, which are depicted as slots, spaced within the electrical element at dimensions that are less than the IC manufacturing limits. For instance, the width of the electrical element may be approximately 50 microns yielding a quality factor of 12 at approximately 2.4 gigahertz. The width of the slots comprising the non-conducting region may be approximately 1 micron wide and positioned at dimensions less than 35 microns. In both simulations and testing, the results with and without the slits provided essentially the same quality factor for both 0.18 micron (e.g., approximately 12) and 0.35 micron CMOS technologies. Since the non-conducting regions are relatively small, they do not perturb the electromagnetic properties of the inductor.

FIGS. 6A, B and C illustrate a top, side, and bottom view of an on-chip capacitor. In this embodiment, the electrical element 12 forms a 1^stplate of the on-chip capacitor and is created on dielectric layer 14. The electrical element 12 includes a non-conducting region 16, which may be implemented as depicted in FIGS. 1 through 4. The 2^ndplate of the on-chip capacitor is provided by electrical element 24, which is created on dielectric layer 26. The electrical element 24 includes a non-conducting region 22, which may be implemented as depicted in FIGS. 1 through 4. In this configuration, a very large parallel plate capacitor or metal insulator metal (MIM) capacitor may be obtained. For instance, the dimensions of the plates may be 400 micron by 400 micron or higher, wherein the non-conducting region includes a plurality of holes having a radius of approximately 1 micron and spaced approximately 35 microns apart in both the X and Y directions.

As one of average skill in the art will appreciate, a 3^rdplate of a capacitor may be fabricated on a 3^rddielectric layer and coupled to the electrical element 12 to produce a sandwich capacitor.

FIG. 7 illustrates a logic diagram of a method for fabricating an integrated circuit in accordance with the present invention. The process begins at Step 30 where one or more dielectric layers are created. The process then proceeds to Step 32 where an electrical element having a geometric shape that includes at least one non-conducting region is fabricated on one or more of the dielectric layers. The non-conducting region has negligible effects on the electrical characteristics of the electrical element and provides adequate non-conducting spacing in accordance with prescribed integrated circuit manufacturing limits. The electrical element has at least one dimension that exceeds the prescribed integrated circuit manufacturing limits. This was generally depicted in FIGS. 1 through 4 with specific embodiments illustrated in FIGS. 5 and 6. Accordingly, the electrical element may be used as one or more windings of an inductor, a plate of a capacitor, an electromagnetic shield, a ground plane, a power source trace, a gate of a transistor, a source of a transistor and/or a drain of a transistor, or an antenna.

The preceding discussion has presented an integrated circuit that includes on-chip components that have electrical elements that exceed integrated circuit manufacturing limits. By including the non-conductive regions within electrical elements of such on-chip components, IC manufacturing limits may be adhered to while providing the benefits of oversized electrical elements. As one of average skill in the art will appreciate, other embodiments may be derived from the teachings of the present invention, without deviating from the scope of the claims.

INVENTORS:

Contopanagos, Harry, Komninakis, Christos

THIS PATENT IS REFERENCED BY THESE PATENTS:

Patent

Priority

Assignee

Title

THIS PATENT REFERENCES THESE PATENTS:

Patent	Priority	Assignee	Title
3092893,
3436810,
4625227,	Sep 01 1980	Hitachi, LTD	Resin molded type semiconductor device having a conductor film
4748537,	May 03 1985	Circuit Components, Incorporated	Decoupling capacitor and method of formation thereof
4797726,	Feb 10 1981	Pioneer Electronic Corporation	Lead frame including deformable plates
4952999,	Apr 26 1988	National Semiconductor Corporation	Method and apparatus for reducing die stress
5150193,	May 27 1987	Hitachi, Ltd.; Hitachi Tobu Semiconductor, Ltd.	Resin-encapsulated semiconductor device having a particular mounting structure
5444186,	Oct 22 1991	Mitsubishi Denki Kabushiki Kaisha	Multilayer conductive wire for semiconductor device and manufacturing method thereof
5683944,	Sep 01 1995	SHENZHEN XINGUODU TECHNOLOGY CO , LTD	Method of fabricating a thermally enhanced lead frame
5686356,	Sep 30 1994	Texas Instruments Incorporated	Conductor reticulation for improved device planarity
6225677,	Mar 11 1998	SOCIONEXT INC	Inductance device formed on semiconductor substrate
6396122,	Sep 08 2000	Newport Fab, LLC	Method for fabricating on-chip inductors and related structure
6462396,	Dec 15 1999	STMICROELECTRONICS S A	Inductance structure on semiconductor substrate
6642604,	Sep 20 2001	Renesas Electronics Corporation	Semiconductor device with resistor layer having heat radiation path to semiconductor substrate
6812544,	Feb 12 2002	AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED	Integrated circuit having oversized components
6842199,	Oct 25 1999	LG DISPLAY CO , LTD	Array substrate for liquid crystal display device and the fabrication method of the same
7170752,	Sep 16 2003	Denso Corporation	Navigation system incorporating antenna
7173318,	Jul 28 2000	Newport Fab, LLC	On-chip inductors
20030075751,
20050012177,
20050116802,
20050122030,
EP924762,
JP98039,

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Executed on	Assignor	Assignee	Conveyance	Frame	Reel	Doc
Nov 20 2013		Broadcom Corporation	(assignment on the face of the patent)

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