An apparatus includes a buck boost converter for generating a regulated output voltage responsive to an input voltage. The buck boost converter includes an inductor, a first pair of switching transistors responsive to a first pwm signal and a second pair of switching transistors responsive to a second pwm signal. An error amplifier generates an error voltage responsive to the regulated output voltage and a reference voltage. A control circuit generates the first pwm signal and the second pwm signal responsive to the error voltage and a sensed current voltage responsive to a sensed current through the inductor. The control circuit controls switching of the first pair of switching transistors and the second pair of switching transistors using the first pwm signal and the second pwm signal responsive to the sensed current through the inductor and a plurality of offset error voltages based on the error voltage.
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13. A method for controlling operations of a buck boost converter, comprising the steps of:
generating a regulated output voltage responsive to an input voltage;
generating an error voltage responsive to the regulated output voltage and a reference voltage;
generating a first pwm signal and a second pwm signal responsive to a sensed current through an inductor and a plurality of offset error window voltages based on the error voltage; and
switching of a first pair of switching transistors and a second pair of switching transistors using the first pwm signal and the second pwm signal.
0. 19. A method for controlling operations of a buck-boost converter, comprising:
receiving a sensed current voltage responsive to a current through an inductor of the buck-boost converter;
determining if the sensed current voltage is above or below a predefined window voltage;
if the sensed current voltage is below the predefined window voltage, determining if the sensed current voltage is substantially equal to a zero voltage;
if the sensed current voltage is below the predefined window voltage and substantially equal to the zero voltage, switching the buck-boost converter to a first mode of operation; and
if the sensed current voltage is below the predefined window voltage and not substantially equal to the zero voltage, switching the buck-boost converter to a second mode of operation.
7. A control circuit for controlling switching of a buck boost converter, the control circuit comprising:
a first input for receiving a sensed current voltage responsive to a sensed current through an inductor of a buck boost converter;
a second input for receiving an error voltage from an error amplifier;
a pair of outputs for providing a first pwm signal and a second pwm signal;
a pwm control circuit for generating the first pwm signal and the second pwm signal responsive to the error voltage and a sensed current voltage responsive to a sensed current through the inductor; and
wherein the control circuit controls switching of thea first pair of switching transistors and thea second pair of switching transistors using the first pwm signal and the second pwm signal responsive to the sensed current through the inductor and a plurality of offset error window voltages based on the error voltage.
1. An apparatus, comprising:
a buck boost converter for generating a regulated output voltage responsive to an input voltage, the buck boost converter including an inductor, a first pair of switching transistors responsive to a first pwm signal and a second pair of switching transistors responsive to a second pwm signal;
an error amplifier for generating an error voltage responsive to the regulated output voltage;
a control circuit for generating a plurality of window voltages responsive to the error voltage, and for generating the first pwm signal and the second pwm signal responsive to the error voltage plurality of window voltages and a sensed current voltage responsive to a sensed current through the inductor; and
wherein the control circuit controls switching of the first pair of switching transistors and the second pair of switching transistors using the first pwm signal and the second pwm signal responsive to the sensed current through the inductor and a the plurality of offset error window voltages based on the error voltage.
2. The apparatus of
summation circuitry for generating the plurality of offset error window voltages responsive to the error voltage and a first offset voltage and a second offset voltage; and
voltage mode control circuitry for generating the first pwm signal and the second pwm signal responsive to a comparison of the sensed current voltage with each of the plurality of offset error window voltages.
3. The apparatus of
a plurality of comparators, each of the comparators comparing the sensed current voltage with one of the plurality of offset error window voltages to generate a voltage control signal;
a first latch circuit connected to receive a first pair of the voltage control signals and generate the first pwm signal responsive thereto; and
a second latch circuit connected to receive a second pair of the voltage control signals and generate the second pwm signal responsive thereto.
4. The apparatus of
5. The apparatus of
6. The apparatus of
8. The control circuit of
summation circuitry for generating the plurality of offset error window voltages responsive to the error voltage and a first offset voltage and a second offset voltage; and
a hysteretic voltage mode control circuitry for generating the first pwm signal and the second pwm signal responsive to comparison of the sensed current voltage with each of the plurality of offset error window voltages.
9. The control circuit of
a plurality of comparators, each pair of the plurality of comparators comparing the sensed current voltage with one of the plurality of offset error window voltages to generate a voltage control signal;
a first latch circuit connected to receive a first pair of the voltage control signals and generate the first pwm signal responsive thereto; and
a second latch circuit connected to receive a second pair of the voltage control signals and generate the second pwm signal responsive thereto.
10. The control circuit of
11. The control circuit of
0. 12. The control circuit of
14. The method of
generating the plurality of offset error window voltages responsive to the error voltage and a first offset voltage and a second offset voltage; and
comparing thea sensed current voltage with each of the plurality of offset error window voltagevoltages to generate the first pwm signal and the second pwm signal.
15. The method of
generating the first pwm signal responsive to a first pair of voltage control signals from the step of comparing; and
generating the second pwm signal responsive to a second pair of voltage control signals from the step of comparing.
16. The method of
alternately turning on and off each of the first pair of switching transistors responsive to the sensed current voltage either exceeding a first of the plurality of offset error window voltages or falling below a second of the plurality of offset error window voltages;
keeping turned off the one of the second pair of switching transistors; and
keeping turned on an other of the second pair of switching transistors. turning off the second pair of switching transistors.
17. The method of
alternately turning on and off each of the second pair of switching transistors responsive to the sensed current voltage either exceeding a third of the plurality of offset error window voltages or falling below a fourth of the plurality of offset error window voltages;
keeping turned off one of the first pair of switching transistors; and
keeping turned on another of the first pair of switching transistors,
turning off the first pair of switching transistors.
18. The method of
alternately turning on and off each of the first pair of switching transistors responsive to the sensed current voltage either exceeding a first of the plurality of offset error window voltages or falling below a second of the plurality of offset error window voltages; and
alternately turning on and off each of the second pair of switching transistors responsive to the sensed current voltage either exceeding a third of the plurality of offset error window voltages or falling below a fourth of the plurality of offset error window voltages.
0. 20. The method of claim 19, further comprising:
responsive to the determining if the sensed current voltage is above or below the predefined window voltage, if the sensed current voltage is above the predefined window voltage, switching the buck-boost converter to the second mode of operation.
0. 21. The method of claim 19, further comprising:
if the buck-boost converter is in the second mode of operation, and the sensed current voltage is below the predefined window voltage, determining if an increase in the sensed current voltage occurred in response to the switching the buck-boost converter to the second mode of operation; and
if the increase in the sensed current voltage did not occur in response to the switching the buck-boost converter to the second mode of operation, switching the buck-boost converter to a third mode of operation.
0. 22. The method of claim 20, further comprising:
if the buck-boost converter is in the second mode of operation, and the sensed current voltage is above the predefined window voltage, determining if a decrease in the sensed current voltage occurred in response to the switching the buck-boost converter to the second mode of operation; and
if the decrease in the sensed current voltage did not occur in response to the switching the buck-boost converter to the second mode of operation, switching the buck-boost converter to a fourth mode of operation.
0. 23. The method of claim 21, further comprising:
if the buck-boost converter is in the third mode of operation, determining if an output voltage of the buck-boost converter is decreased to a predefined threshold level;
if the output voltage is decreased to the predefined threshold level, switching the buck-boost converter to a fifth mode of operation; and
if the output voltage is not decreased to the predefined threshold level, switching the buck-boost converter to the second mode of operation.
0. 24. The method of claim 22, further comprising:
if the decrease in the sensed current voltage occurred in response to the switching the buck-boost converter to the second mode of operation, determining if an output voltage of the buck-boost converter is decreased to a predefined threshold level;
if the output voltage is decreased to the predefined threshold level, switching the buck-boost converter to a fifth mode of operation; and
if the output voltage is not decreased to the predefined threshold level, switching the buck-boost converter to the second mode of operation.
0. 25. The method of claim 21, further comprising:
if the increase in the sensed current voltage occurred in response to the switching the buck-boost converter to the second mode of operation, determining if an output voltage of the buck-boost converter is decreased to a predefined threshold level;
if the output voltage is decreased to the predefined threshold level, switching the buck-boost converter to a fifth mode of operation; and
if the output voltage is not decreased to the predefined threshold level, switching the buck-boost converter to the second mode of operation.
0. 26. The method of claim 19, wherein the first mode of operation is a diode emulation mode, and the second mode of operation is a direct pass mode.
0. 27. The method of claim 21, wherein the third mode of operation comprises a charging mode.
0. 28. The method of claim 22, wherein the fourth mode of operation comprises a discharge mode.
0. 29. The method of claim 23, wherein the fifth mode of operation comprises a free-wheeling mode.
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This application CapacitorR Rr 1114 is used to eliminate the DC component of the voltage signal applied by voltage source VR Vr 1120. The current through capacitor 1106, IRIPPLE has a similar ripple wave form as the inductor current. With the synthesized ripple signal, the hysteretic current mode control may be implemented without the actual inductor current information.
It will be appreciated by those skilled in the art having the benefit of this disclosure that this hysteretic controlled buck-boost converter provides an improved operation with less switching losses. It should be understood that the drawings and detailed description herein are to be regarded in an illustrative rather than a restrictive manner, and are not intended to be limiting to the particular forms and examples disclosed. On the contrary, included are any further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments apparent to those of ordinary skill in the art, without departing from the spirit and scope hereof, as defined by the following claims. Thus, it is intended that the following claims be interpreted to embrace all such further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments.
Liu, Jun, Moussaoui, Zaki, Qiu, Weihong
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