Assemblies include a substrate, such as a printed circuit board, with a first array of contact pads disposed thereon; a guide ring structure disposed on the substrate and at least partially surrounding the first array of contact pads; a translator socket disposed on the first array of contact pads, the translator socket adapted to receive the tester side of a translated wafer; a thermally conductive, conformal, heat spreading cushion adapted to be disposed over the backside of a wafer; a cover plate adapted to fit over the first array of contact pads, align with the guide ring structure, contain within it the various components disposed over the first array of contact pads, and removably attach to the substrate; and a bolster plate adapted to removably attach to a second side of the substrate. In a further aspect a translated wafer is disposed over the translator socket such that the tester side of the translator is in contact with the translator socket; and the heat spreading cushion is disposed over the backside of the translated wafer. In a still further aspect, the substrate includes signal communication means, such as but not limited to, an edge connector adapted to couple to various controller circuits, which are typically disposed on a printed circuit board.
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8. A wafer-level burn-in assembly, comprising:
a circuit board having a first major surface and a second major surface;
a first plurality of contact pads disposed in a first area of the first major surface of the circuit board, the first plurality of contact pads arranged in first pattern;
a guide ring disposed on the first major surface of the circuit board such that the guide ring is outside the first area;
a wafer burn-in socket having a first major surface and a second major surface, the first major surface having a plurality of contact pads arranged in a second pattern that matches the first pattern, the second major surface having a plurality of contact pads arranged in a third pattern, the first major surface of the wafer burn-in socket disposed on the circuit board;
a translated wafer having a first surface comprising a wafer backside and a second surface comprising a wafer translator tester-side;
a heat spreader disposed against a side of the wafer facing away from the translator;
a cover disposed over the heat spreader;
a controller board coupled to the circuit board.
0. 15. A wafer-level burn-in assembly, comprising:
a circuit board having a first major surface and a first plurality of contact pads arranged in a first pattern at a first area of the first major surface;
an interposer having
a first major surface facing the first major surface of the circuit board, the first major surface of the interposer having a second plurality of contact pads arranged in a second pattern that corresponds to the first pattern of the circuit board, and
a second major surface of the interposer, the second major surface having a third plurality of contact pads arranged in a third pattern; and
a wafer translator having
a first major surface facing the second major surface of the interposer, the first major surface of the wafer translator having a fourth plurality of contact pads arranged in a fourth pattern that corresponds to the third pattern of the interposer, and
a second major surface positioned to face toward a wafer;
a heat spreader disposed toward the wafer translator;
a cover disposed over the heat spreader; and
a guide ring adjacent to the cover, the guide ring having holes for fasteners.
0. 16. A wafer-level burn-in assembly, comprising:
a circuit board having a first major surface and a first plurality of contact pads arranged in a first pattern at a first area of the first major surface;
an interposer having
a first major surface facing the first major surface of the circuit board, the first major surface of the interposer having a second plurality of contact pads arranged in a second pattern that corresponds to the first pattern of the circuit board, and
a second major surface of the interposer, the second major surface having a third plurality of contact pads arranged in a third pattern;
a wafer translator having
a first major surface facing the second major surface of the interposer, the first major surface of the wafer translator having a fourth plurality of contact pads at a first scale and arranged in a fourth pattern that corresponds to the third pattern of the interposer, and
a second major surface having a fifth plurality of contact pads at a second scale and positioned to electrically contact for burn-in testing semiconductor dies of a wafer,
wherein the first scale is larger than the second scale;
a heat spreader facing toward the wafer translator; and
a cover disposed over the heat spreader.
1. A wafer-level burn-in assembly, comprising:
a circuit board having a first major surface and a second major surface;
a first plurality of contact pads disposed in a first area of the first major surface of the circuit board, the first plurality of contact pads arranged in first pattern;
a guide ring disposed on the first major surface of the circuit board such that the guide ring is outside the first area;
a wafer burn-in socket having a first major surface and a second major surface, the first major surface having a plurality of contact pads arranged in a second pattern that matches the first pattern, the second major surface having a plurality of contact pads arranged in a third pattern, the first major surface of the wafer burn-in socket disposed on the circuit board;
a wafer translator having a first major surface and a second major surface, the first major surface having a plurality of contact pads arranged in a fourth pattern that matches the third pattern, the first major surface of the wafer translator disposed on the wafer burn-in socket;
a wafer attached to the second major surface of the wafer translator;
a heat spreader disposed against a side of the wafer facing away from the translator;
a cover disposed over the heat spreader; and
a controller board coupled to the circuit board.
0. 21. A method for wafer-level burn-in, comprising:
aligning a circuit board, an interposer and a wafer translator, the circuit board having
a first major surface and a first plurality of contact pads arranged in a first pattern at a first area of the first major surface;
the interposer having
a first major surface facing the first major surface of the circuit board, the first major surface of the interposer having a second plurality of contact pads arranged in a second pattern, and
a second major surface having a third plurality of contact pads arranged in a third pattern;
the wafer translator having
a first major surface facing the second major surface of the interposer, the first major surface of the wafer translator having a fourth plurality of contact pads at a first scale and arranged in a fourth pattern, and
a second major surface having a fifth plurality of contact pads at a second scale and positioned to electrically contact for burn-in testing semiconductor dies of a wafer, wherein the first scale is larger than the second scale, and wherein aligning includes:
aligning at least one of the first and second patterns with the other of the first and the second pattern, and
aligning at least one of the third and fourth patterns with the other of the third and fourth patterns;
disposing a heat spreader against the wafer translator; and
disposing a cover over the heat spreader.
2. The wafer-level burn-in assembly of
3. The wafer-level burn-in assembly of
4. The wafer-level burn-in assembly of
5. The wafer-level burn-in assembly of
6. The wafer-level burn-in assembly of
7. The wafer-level burn-in assembly of
9. The wafer-level burn-in assembly of
10. The wafer-level burn-in assembly of
11. The wafer-level burn-in assembly of
12. The wafer-level burn-in assembly of
13. The wafer-level burn-in assembly of
14. The wafer-level burn-in assembly of
0. 17. The wafer-level burn-in assembly of claim 16, further comprising a bolster plate facing the circuit board opposite from the first major surface of the circuit board, the bolster plate attached to the cover.
0. 18. The wafer-level burn-in assembly of claim 17, further comprising a guide ring between the bolster plate and the cover, the guide ring having holes for fasteners connecting the bolster plate and the cover.
0. 19. The wafer-level burn-in assembly of claim 16, further comprising a controller board coupled to the circuit board.
0. 20. The wafer-level burn-in assembly of claim 16, further comprising a plurality of edge connectors on the circuit board, the plurality of edge connectors in electrical contact with the corresponding plurality of contact pads on the circuit board.
0. 22. The method of claim 21, further comprising:
disposing a bolster plate against the circuit board opposite from the first major surface of the circuit board, and
attaching the bolster plate to the cover.
0. 23. The method of claim 21, further comprising disposing a guide ring between the bolster plate and the cover, wherein the guide ring has holes for the fasteners connecting the bolster plate and the cover.
0. 24. The method of claim 21, further comprising operably coupling a controller board to the circuit board through a plurality of corresponding edge connectors on the controller board and the circuit board.
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This FIG. 8A is a side view of the wafer translator. The As illustrated in FIG. 8A, the wafer translator includes a substrate having two major surfaces, an inquiry-side 803a and a wafer-side 803b, each surface having terminals disposed thereon, and electrical pathways disposed through the substrate to provide for electrical continuity between at least one terminal on a first surface and at least one terminal on a second surface. The wafer-side 803b of the wafer translator has a pattern of terminals at a second scale d2 that matches the layout of at least a portion of the I/O pads of the integrated circuits on the wafer. The wafer translator, when disposed between a wafer and other electrical components, makes electrical contact with one or more I/O pads of a plurality of integrated circuits on the wafer, providing an electrical pathway therethrough to the other electrical components. The wafer translator is a structure that is used to achieve electrical connection between one or more electrical terminals that have been fabricated at a first scale, or dimension d1 at the inquiry-side 803a, and a corresponding set of electrical terminals that have been fabricated at a second scale, or dimension d2 at the wafer-side 803b. The wafer translator provides an electrical bridge between the smallest features in one technology (e.g., pins of a probe card at scale d1) and the largest features in another technology (e.g., bonding pads of an integrated circuit at scale d2). For convenience, wafer translator is referred to simply as translator where there is no ambiguity as to its intended meaning.
The expression “translated wafer” refers to a wafer that has a wafer translator attached thereto, wherein a predetermined portion of, or all of, the contact pads of the integrated circuits on the wafer are in electrical contact with corresponding electrical connection means disposed on the wafer side of the translator. Typically, the wafer translator is removably attached to the wafer. Removable attachment may be achieved by means of vacuum, or pressure differential, attachment.
The expressions “burn-in socket for wafers”, “wafer burn-in socket”, and “translator socket”, refer to a component adapted to be disposed upon a first array of contact pads, to make electrical contact with the individual terminals of that first array of contact pads, and to make electrical contact with a plurality of contact pads on the topside, also referred to as the “tester side”, of a wafer translator. The translator socket comprises an insulating body with contact pads disposed on each major surface, and further having interconnections through that insulating body to provide electrical connection between the contact pads on one side with corresponding pads on the other side. Although the term “socket” is used, the translator socket is not limited to a configuration in which insertion of terminals into the translator socket is required. In other words, the translator socket may take the form of an interposer with contact pads on each major surface thereof, and in which electrical contact is made by urging counterpart contact pads, or terminals, of the substrate and/or the non-wafer-side of the translator into contact with the translator socket.
The terms chip, integrated circuit, semiconductor device, and microelectronic device are sometimes used interchangeably in this field. The present invention relates to the manufacture and test of chips, integrated circuits, semiconductor devices and microelectronic devices as these terms are commonly understood in the field.
Referring to
Various embodiments of the present invention provide methods and apparatus for wafer-level burn-in that allows for use of conventional controller boards and burn-in ovens.
Referring to
Referring to
As shown in
Heat spreader 801 is a thermally conductive cushion characterized by the ability to transfer heat between at least the cover and the wafer. Heat spreader 801 is typically disposed such that it is in physical contact with both the backside of wafer 802 and with cover 800. In this way, heat from the burn-in oven can be transferred through cover 800 to wafer 802. Typically, heat transfer through heat spreader 801 is not uni-directional, and therefore heat from wafer 802 may also be transferred through heat spreader 801 to cover 800 when the difference in temperatures supports such transfer.
Still referring to
In one embodiment of the present invention, a wafer-level burn-in assembly, includes:
a circuit board having a first major surface and a second major surface;
a first plurality of contact pads disposed in a first area of the first major surface of the circuit board, the first plurality of contact pads arranged in first pattern;
a guide ring disposed on the first major surface of the circuit board such that the guide ring is outside the first area;
a wafer burn-in socket having a first major surface and a second major surface, the first major surface having a plurality of contact pads arranged in a second pattern that matches the first pattern, the second major surface having a plurality of contact pads arranged in a third pattern, the first major surface of the wafer burn-in socket disposed on the circuit board;
a wafer translator having a first major surface and a second major surface, the first major surface having a plurality of contact pads arranged in a fourth pattern that matches the third pattern, the first major surface of the wafer translator disposed on the wafer burn-in socket;
a wafer attached to the second major surface of the wafer translator;
a heat spreader disposed against a side of the wafer facing away from the translator; and
a cover disposed over the heat spreader.
In another embodiment, a wafer-level burn-in assembly includes:
a circuit board having a first major surface and a second major surface;
a first plurality of contact pads disposed in a first area of the first major surface of the circuit board, the first plurality of contact pads arranged in first pattern;
a guide ring disposed on the first major surface of the circuit board such that the guide ring is outside the first area;
a wafer burn-in socket having a first major surface and a second major surface, the first major surface having a plurality of contact pads arranged in a second pattern that matches the first pattern, the second major surface having a plurality of contact pads arranged in a third pattern, the first major surface of the wafer burn-in socket disposed on the circuit board;
a wafer translator having a first major surface and a second major surface, the first major surface having a plurality of contact pads arranged in a fourth pattern that matches the third pattern, the first major surface of the wafer translator disposed on the wafer burn-in socket;
a wafer removably attached to the second major surface of the wafer translator;
a heat spreader disposed against a side of the wafer facing away from the translator; and
a cover disposed over the heat spreader and in physical contact with the guide ring.
Various embodiments of the present invention include apparatus and methods for providing wafer level, i.e., pre-singulation, testing of integrated circuits, at predetermined temperatures.
Embodiments of the present invention may find application in the field of semiconductor circuit testing.
An advantage of some embodiments of the present invention includes testing integrated circuits at elevated temperatures while still in wafer form in a manner that is compatible with existing burn-in equipment, including burn-in ovens and controller boards, that are adapted for burn-in testing of individually packaged integrated circuits.
It is to be understood that the present invention is not limited to the embodiments described above, but encompasses any and all embodiments within the scope of the subjoined Claims and their equivalents.
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Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
May 29 2008 | JOHNSON, MORGAN T | ADVANCED INQUIRY SYSTEMS, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 037252 | /0229 | |
May 18 2012 | Translarity, Inc. | (assignment on the face of the patent) | / | |||
Nov 17 2014 | ADVANCED INQUIRY SYSTEMS, INC | TRANSLARITY, INC | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 037255 | /0833 |
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