High-side sensing of zero inductor current for step-down DC-DC converter

Abstract

A DC to DC converter circuit includes circuitry for generating a pwm waveform signal at a phase node of a DC to DC converter responsive to an input voltage and a monitor monitored output voltage. The circuitry further includes a high side switching transistor connected between the input voltage and a phase node and a low side switching transistor connected between the phase node and ground. An output filter is connected to the circuitry for generating the pwm waveform signal. The output filter includes an inductor having a first side connected to the phase node and a second side connected to an output voltage node. Detection circuitry detects zero current crossings in the inductor responsive to a voltage across the high side switching transistor and a voltage across the low side switching transistor.

Description

can not cannot be detected and the DC to DC converter can not cannot change from PWM (pulse width modulation) mode to PFM (pulse frequency modulation) mode, even when the load current reaches zero. The addition of comparator 312 and OR gate 310 enables this problem to be overcome. The comparator 312 enables the inductor current zero crossing point to also be detected during the “on” time of the high side switching transistor 214. When the inductor current is zero or negative, the phase voltage VPHS at node 218 is equal to or higher than the input voltage PVIN, and the output of the comparator 312 is triggered to a logical high level (“one”) due to the change of the phase node voltage VPHS minus the input node voltage VPVIN from negative to positive. This enables the inductor current zero crossing within the inductor 220 to be detected during the high side switching transistor 214 “on” time.

The outputs of comparator 312 and comparator 308 are ORed together by the OR gate 310 to generate an inductor current zero crossing level detector that measures zero crossing values across a broader frequency and duty cycle range than merely the comparator 308 monitoring the low side transistor 216. Thus, an indication of the zero current crossing within the inductor indicated by the voltage across either of the high side switching transistor 214 or the low side switching transistor 216 may cause the output of the OR gate 310 to be triggered indicating the zero current crossing detection. When the duty cycle of the DC to DC converter is high and comparator 308 does not have a sufficient response time to respond to voltage changes across the transistor 216, the longer “on” time of the high side switching transistor 214 due to its fixed switching frequency will enable sufficient time for the comparator 312 to detect voltage changes and respond to inductor current zero crossings. The same conditions occur when the duty cycle is at a very low level and comparator 312 has more time to detect inductor current zero crossings. As described previously, when the output of the OR gate 310 is determined to detect zero crossing for eight continuous clock cycles by the counter 311, this is used to initiate the PFM control mode within the switching control circuitry of the PWM controller associated with the regulator. Comparator 312 and comparator 308 are never on at the same time. Comparator 312 is on after the high-side switching transistor is turned on, while comparator 308 is turned on after the low-side switching transistor is turned on. While the comparator 308 is disabled, the output of the comparator is forced to a logical low level. When the comparator 312 is disabled, its output is also forced to a logical low level. The output of the OR gate 310 is connected to a counter 311. The counter counts the number of clock cycles that the output signal goes high. If the counter 311 monitors eight continuous clock cycles high for the output signal, this indicates, that either the COMP 1 or COMP 2 has detected zero crossings for eight continuous clock cycles which will initiate the pulse frequency modulation (PFM control mode). Thus the output signal is used in the PWM mode (CCM mode) to initiate the PFM control mode. Thus, a complementary detection system is provided.

Referring now to FIG. 4, there are illustrated the wave forms wave-forms of the various signals at particular nodes within the circuit described with respect to FIG. 3. The waveform I_L 402 represents the inductor current through the inductor 220 of a DC to DC DC-to-DC converter. The current through the conductor inductor 220 is represented by a sawtooth type waveform that goes above and below a zero amp ampere (0 A) inductor current indicated generally by the dashed line 404. The inductor current is increasing from times time T₁ one to times time T₂ and is decreasing from time T₂ to time T₃. This pattern repeats throughout the waveform 402. A zero crossing of the inductor current is indicating indicated generally at 406. Of course numerous other occurrences of zero crossings within the waveform are also present.

The phase node voltage waveform VPHS is illustrated generally by waveform 408. Additionally illustrated with respect to this waveform are the input voltage which is indicated as a consistent voltage VPVIN PVIN 410 and the ground voltage indicated by PGND 412. The voltage at the phase node 218 is decreasing from times time T₁ to times time T₂. At time T₂ the voltage VPHS drops below PGND 412. The voltage VPHS at the phase node 420 218 then begins increasing from time T₂ to time T₃. This process is then repeated.

The output voltage of comparator 308 is represented by voltage wave form 414 wave-form 416. The output of comparator 308 goes high at each instance of the decreasing inductor current crossing zero at times T₁, T₃, etc. The output of comparator 312 is indicated generally by the waveform 416 414. This pulse comparator 312 monitors the voltage across the high side transistor and provides an indication when the phase voltage VPHS is equal to or higher than the input voltage VPVIN PVIN. The OR gate output, represented generally by waveform 420, provides a wider pulse when both the outputs of the comparator comparators 308 and 312 have gone high responsive to a zero current zero-current crossing or additionally registers a narrower pulse responsive to the output of the comparator 312 when only the comparator 312 may detect the zero current crossing due to the frequency/duty cycle of the DC to DC voltage inverter converter being to too high. Therefore, using the above described system and method, there are no duty cycle limitations to the circuitry as compared with prior art implementations. The Therefore, the circuitry can achieve a truly detect a zero-current crossing point during PWM mode, and transition from PWM mode to PFM mode, even while the power supply is operating at a 100% duty cycle in PWM to PFM transition mode.

It will be appreciated by those skilled in the art having the benefit of this disclosure that this high-side sensing of zero inductor current for step down dc-dc converter provides an improved inductor current zero crossing detector. It should be understood that the drawings and detailed description herein are to be regarded in an illustrative rather than a restrictive manner, and are not intended to be limiting to the particular forms and examples disclosed. On the contrary, included are any further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments apparent to those of ordinary skill in the art, without departing from the spirit and scope hereof, as defined by the following claims. Thus, it is intended that the following claims be interpreted to embrace all such further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments.

Claims

1. A DC to DC DC-to-DC converter circuit, comprising:

circuitry for generating configured to generate a pwm waveform signal of the DC to DC DC-to-DC converter responsive to an input voltage and a monitored output voltage, the circuitry further comprising a high side high-side switching transistor connected between the input voltage and the a phase node and a low side low-side switching transistor connected between the phase node and ground;

an output filter connected to the circuitry for generating and configured to generate the pwm waveform signal, the output filter including an inductor having a first side connected to the phase node and a second side connected to an output voltage node;

detection circuitry for detecting zero current configured to detect zero-current crossings in the inductor responsive to a voltage across the high side high-side switching transistor and a voltage across the low side low-side switching transistor; and

wherein the detection circuitry detects is configured to detect zero current crossing zero-current crossings in the inductor using the turn on time of a high side during a turn-on time of the high-side switching transistor at while circuitry is operating in a frequency range causing that causes a turn on turn-on time of a low side the low-side switching transistor to be too short to detect the zero current crossing zero-current crossings in the inductor using the low side low-side switching transistor.

2. The DC to DC DC-to-DC converter circuit of claim 1, wherein the detection of the zero current crossings in the inductor enables the DC to DC DC-to-DC converter to pass from a pwm mode to a PFM mode.

3. The DC to DC DC-to-DC converter circuit of claim 1, wherein the detection circuitry further comprises:

a first comparator for comparing configured to compare a first voltage at the phase node with a second voltage at the ground and generating to generate a first output responsive thereto;

a second comparator for comparing configured to compare the first voltage at the phase node with a third voltage at an input voltage node and generating to generate a second output responsive thereto; and

a logical or gate connected to receive the first output and the second output and to generate a third output responsive thereto, wherein the third output indicates the zero current zero-current crossings in the inductor.

4. The DC to DC DC-to-DC converter circuit of claim 3, wherein the first comparator providing is configured to generate the first output at a first logical level is responsive to a difference between the first voltage and the second voltage going from a negative value to a positive value and further wherein the second comparator providing is configured to generate the second output at the first logical level is responsive to a difference between the first voltage and the third voltage going from a negative value to a positive value.

5. The DC to DC DC-to-DC converter circuit of claim 3, wherein the detection circuitry can is configured to detect the zero current zero-current crossings in the inductor when while the operating frequency of the DC to DC DC-to-DC converter operates at is in a frequency range causing a turn on turn-on time of the low side low-side switching transistor to be too short for the first comparator to detect the zero current zero-current crossings in the inductor.

6. The DC to DC DC-to-DC converter circuit of claim 2, wherein the detection circuitry detects the zero current is configured to detect the zero-current crossings in the inductor using the turn on time of high side during the turn-on time of the high-side switching transistor at while the circuitry is operating in a frequency range causing a turn on time of the low side which causes the turn-on time of the low-side switching transistor to be too short for the first comparator to detect the zero current zero-current crossings in the inductor.

7. Detection circuitry for detecting zero current zero-current crossings through an inductor of a DC to DC DC-to-DC converter circuit, comprising:

a first comparator for detecting a turn on time of a low side configured, during a turn-on time of a low-side switching transistor by comparing, to compare a first voltage at the a phase node with a second voltage at a ground node and generating to generate a first output responsive thereto;

a second comparator for detecting a turn on time of a high side configured, during a turn-on time of a high-side switching transistor by comparing, to compare the first voltage at the phase node with a third voltage at an input voltage and generating to generate a second output responsive thereto;

a logical or gate connected to receive the first output and the second output and to generate a third output responsive thereto, wherein the third output indicates the zero current zero-current crossings in the inductor; and

wherein the detection circuitry can is configured to detect the zero current zero-current crossings in the inductor when while the operating frequency of the DC to DC DC-to-DC converter operates at is in a frequency range causing a turn on time of the low side turn-on time of the low-side switching transistor to be too short for the first comparator to detect the zero current zero-current crossings in the inductor.

8. The detection circuit of claim 7, wherein the detection of the zero current zero-current crossings in the inductor enables the DC to DC DC-to-DC converter to pass from a pwm mode to a PFM mode.

9. The detection circuit of claim 7, wherein the first comparator providing is configured to generate the first output at a first logical level is responsive to a difference between the first voltage and the second voltage going from a negative value to a positive value and further wherein the second comparator providing is configured to generate the second output at the first logical level is responsive to a difference between the first voltage and the third voltage going from a negative value to a positive value.

10. The detection circuit of claim 7, wherein the detection circuitry detects is configured to detect the zero current zero-current crossings in the inductor using the turn on time of high side during the turn-on time of the high-side switching transistor at while the detection circuitry is operating in a frequency range causing a turn on time of the low side which causes the turn-on time of the low-side switching transistor to be too short for the first comparator to detect the zero current zero-current crossings in the inductor.

11. A method for detecting zero current zero-current crossings within a DC to DC DC-to-DC converter circuit, comprising the steps of:

generating a pwm waveform signal of the DC to DC DC-to-DC converter responsive to an input voltage and a monitored output voltage;

filtering the pwm waveform signal through an output filter including and an inductor to generate an output voltage; and

detecting zero current the zero-current crossings in the inductor responsive to a voltage voltages across both a high side high-side switching transistor and a low side low-side switching transistor when while the operating frequency of the DC to DC DC-to-DC converter operates at in a frequency range causing a turn on turn-on time of the low side low-side switching transistor to be too short to detect the zero current crossing zero-current crossings in the inductor using only the low side low-side switching transistor.

12. The method of claim 11, wherein the step of detecting further comprises the steps of:

detecting an “on” state of the low side low-side switching transistor;

detecting an “on” state of the high side high-side switching transistor; and

generating an indication of the zero current crossing zero-current crossings responsive to the detection of the “on” state of at least one of the low side low-side switching transistor and the “on” state of at least one of the high side high-side switching transistor.

13. The method of claim 11 further including the step of switching the DC to DC DC-to-DC converter from a pwm mode to a PFM mode responsive to the detection of the zero current zero-current crossings in the inductor.

14. The method of claim 11, wherein the step of detecting further comprises the steps of:

comparing a first voltage at a phase node on a first side of the low side low-side switching transistor with a second voltage at a ground node on a second side of the low side low-side switching transistor;

generating a first output responsive to the comparison of the first voltage and the second voltage;

comparing the first voltage at the phase node on a first side of the high side high-side switching transistor with a third voltage at an input voltage node on a second side of the high side high-side switching transistor; and

generating a second output responsive to the comparison of the first voltage and the third voltage; and

logically ORing the first output and the second output to generate a third output, wherein the third output indicates the zero current zero-current crossings in the inductor.

15. The method of claim 14, wherein the step of generating the first output further comprises the step of generating the first output at a first logical level responsive to a difference between the first voltage and the second voltage going from a negative value to a positive value.

16. The method of claim 15, wherein the step of generating the second output further comprises the step of generating the second output at the first logical level responsive to a difference between the first voltage and the third voltage going from a negative value to a positive value.

17. Detection circuitry for detecting zero current zero-current crossings through an inductor of a DC to DC DC-to-DC converter circuit, comprising:

a first comparator for detecting a turn on time of a low side configured, during a turn-on time of a low-side switching transistor by comparing, to compare a first voltage at the a phase node with a second voltage at a ground node and generating to generate a first output responsive thereto;

a second comparator for detecting a turn on time of a high side configured, during a turn-on time of a high-side switching transistor by comparing, to compare the first voltage at the phase node with a third voltage at an input voltage node and generating to generate a second output responsive thereto;

a logical or gate connected to receive the first output and the second output and to generate a third output responsive thereto, wherein the third output indicates the zero current zero-current crossings in through the inductor; and

wherein the detection circuitry detects the zero current crossings in the inductor using the turn on time of high side is configured to detect the zero-current crossings through the inductor using the high-side switching transistor during the turn-on time of the high-side switching transistor at while the low-side switching transistor is operating in a frequency range causing a turn on time of the low side which causes the turn-on time of the low-side switching transistor to be too short for the first comparator to detect the zero current crossings in the inductor zero-current crossings through the inductor using the low-side switching transistor.