A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.

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Patent
   RE46522
Priority
Jan 19 2011
Filed
Jan 21 2015
Issued
Aug 22 2017
Expiry
Jan 19 2031
Inventors
Chen, Shih…
Assg.orig
Macronix I…
Assg.curr
Macronix I…
Entity
Large
Referenced by
0
References
13
Maint.:
all paid
BACKGROUND
1. A memory device, comprising:
a substrate;
a plurality of stacked structures disposed on the substrate, wherein each of the stacked structures comprises a string selection line, a word line, a ground selection line and an insulating line lines, the string selection line, the word line and the ground selection line are separated from each other by the insulating line lines;
a channel element disposed between the stacked structures;
a dielectric element disposed between the channel element and the stacked structure;
a source element disposed between an upper surface of a substrate and the lower surface of the channel element; and
a bit line disposed on the upper surface of the channel element.
10. A method for manufacturing a memory device, comprising:
disposing a plurality of stacked structures on a substrate, wherein each of the stacked structures comprises a string selection line, a word line, a ground selection line and an insulating line lines, the string selection line, the word line and the ground selection line are separated from each other by the insulating line lines;
disposing a channel element between the stacked structures;
disposing a dielectric element between the channel element and the stacked structure;
disposing a source element between an upper surface of the substrate and a lower surface of the channel element; and
disposing a bit line on the upper surface of the channel element.
16. A method for operating a memory device, comprising:
providing a memory device comprising:
a substrate;
a plurality of stacks of horizontal lines of conductive material stacked structures disposed on vertically over the substrate, wherein each of the stacked structures comprises stacks in the plurality of stacks includes horizontal lines configured respectively as a string selection line, a word line, and a ground selection line and an insulating line, the string selection line, the word line and the ground selection line are being separated from each other by the insulating line lines;
a channel element comprising a plurality of channel lines, the channel lines are being disposed vertically between the stacked structures stacks and separated from each other;
a dielectric element material disposed between the channel lines and sides of the stacked structures stacks;
a source element disposed between an upper surface of the substrate and a lower surface of in electrical communication with the channel lines; and
a bit line disposed on a upper surface of in electrical communication with the channel element; and lines, wherein the method comprises selecting at least one of the channel lines to be turned on.
0. 36. A method for operating a memory device comprising:
a plurality of stacks of horizontal lines of conductive material, each comprising:
a string selection line;
a word line; and
a ground selection line;
wherein the first channel line is disposed between a first stack and a second stack of the plurality of stacks; and
a second channel line is disposed between the second stack and a third stack of the plurality of stacks;
a first charge storing element between and contacting the second channel line and the word line of the first stack;
a second charge storing element between and contacting the second channel line and the word line of the second stack; and
the method comprising:
applying a first bias voltage to the word line of the first stack; and
applying a second bias voltage, different than the first bias voltage, to the word line of the second stack in an operation to selectively read or program data in either of the first or second charge storage elements.
0. 27. A memory device, comprising:
a plurality of stacks of horizontal lines of conductive material, each comprising;
a string selection line,
a word line, and
a ground selection line,
a channel element comprising;
a first channel line disposed between a first stack and a second stack of the plurality of stacks; and
a second channel line disposed between the second stack and a third stack of the plurality of stacked structures;
a first charge storing element between and contacting the second channel line and the word line of the first stack;
a second charge storing element between and contacting the second channel line and the word line of the second stack; and
wherein the word line of the first stack and the word line of the second stack are electrically separate in the memory device such that different bias voltages may be applied concurrently to the word line of the first stack and the word line of the second stack to access selectively the first charge storing element or the second charge storage element.
0. 34. A method for manufacturing a memory device, comprising:
disposing a plurality of stacks of horizontal lines of conductive material on a substrate, wherein each of the stacks comprises a string selection line, a word line, and a ground selection line;
disposing a channel element between the stacks, the channel element comprising:
a first channel line disposed between a first and a second stacks of the plurality of stacks; and
a second channel line disposed between the second stack and a third stack of the plurality of stacks;
disposing a first charge storing element between and contacting the second channel line and the word line of the first stack;
disposing a second charge storing element between and contacting the second channel line and the word line of the second stack;
wherein the word line of the first stack and the word line of the second stack are electrically separate in the memory device such that different bias voltages may be applied concurrently to the word line of the first stack and the word line of the second stack.
2. The memory device according to claim 1, wherein the source element and the substrate are separated from each other by the dielectric element, the substrate is used as a bottom gate.
3. The memory device according to claim 1, wherein the string selection line, the word line and the ground selection line have a first type conductivity, the source element, the channel element and the bit line have a second type conductivity opposite to the first type conductivity, the channel element has a dopant concentration smaller than dopant concentrations that the source element and the bit line have.
4. The memory device according to claim 1, wherein the bit line, the string selection line, the word line and the ground selection line have a first type conductivity, the source element and the channel element have a second type conductivity opposite to the first type conductivity, the channel element has a dopant concentration smaller than a dopant concentration that the source element has.
5. The memory device according to claim 1, wherein the bit line has a first type conductivity, the channel element has a second type conductivity opposite to the first type conductivity.
6. The memory device according to claim 1, wherein the channel element and the bit line form a PN diode.
7. The memory device according to claim 1, wherein the source element comprises a source layer covering the substrate.
8. The memory device according to claim 1, wherein the channel element comprises a plurality of channel lines, the source element comprises a plurality of source lines,
one of the source lines below the channel lines on the same sidewall of the stacked structure is continuously extended;
the source lines below the channel lines on the opposite sidewalls of the stacked structure are separated from each other.
9. The memory device according to claim 1, wherein the channel element comprises a plurality of channel lines, the source element comprises a plurality of source lines, the channel line has a long side perpendicular to a long side that the source line has.
11. The method for manufacturing the memory device according to claim 10, wherein the stacked structures has a space therebetween, the source element comprises a source line, the method for manufacturing the memory device comprises:
forming a dielectric element on the substrate and the stacked structures exposed by the space;
forming a conductive material for filling the space; and
removing a portion of the conductive material for forming the source line and the channel element, wherein the source line and the channel element are disposed in the space, the source line and the substrate are separated from each other by the dielectric element.
12. The method for manufacturing the memory device according to claim 11, wherein the conductive material is extended on the stacked structure, the bit line is formed by a method comprising:
doping a portion of the conductive material extended on the stacked structure; and
removing a portion of the doped conductive material for forming the bit line.
13. The method for manufacturing the memory device according to claim 10, wherein the source element comprises a source layer covering the substrate, the method for manufacturing the memory device comprises:
alternately stacking a plurality of sacrificial layers and a plurality of insulating layers;
forming a first opening in the alternately-stacked sacrificial layers and insulating layers;
forming the channel element by an epitaxial growth on the source layer exposed by the first opening;
forming a second opening in the alternately-stacked sacrificial layers and insulating layers;
removing the sacrificial layer exposed by the second opening for forming a slit exposing the channel element;
forming the dielectric element exposed by the slit; and
forming a conductive material filling in the slit for forming the string selection line, the word line and the ground selection line.
14. The method for manufacturing the memory device according to claim 13, wherein the source layer and the channel element are composed of a single crystal material, and the channel element is formed by an epitaxial growth.
15. The method for manufacturing the memory device according to claim 13, wherein the source layer is a single crystal silicon, the insulating line is an oxide, the sacrificial layer is a silicon nitride, the second opening exposes the source layer and the insulating line, the sacrificial layer exposed by the second opening is removed by a method using a hot H3PO4.
17. The method for operating the memory device according to claim 16, wherein the string selection line, the word line and the ground selection line have a first type conductivity, the source element, the channel element and the bit line have a second type conductivity opposite to the first type conductivity,
the channel line is turned on by a method comprising: wherein said selecting comprises:
applying a first bias voltage to the string selection lines of the stacked structures stacks of horizontal lines on the two opposite sidewalls of the selected channel line.
18. The method for operating the memory device according to claim 17, further comprising wherein said selecting comprises applying a second bias voltage to the string selection line of the stacked structure stacks on one sidewall of the channel line not selected and to be turned off, wherein the turned off channel line and the turned-on channel line have the common string selection line that the first bias voltage applied to, the first bias voltage is opposite to the second bias voltage.
19. The method for operating the memory device according to claim 18, wherein the first type conductivity is P type conductivity, the second type conductivity is N type conductivity, the first bias voltage is a positive bias voltage, and the second bias voltage is a negative bias voltage.
20. The method for operating the memory device according to claim 17, further comprising applying a second bias voltage to the string selection lines of the stacked structures stacks on the opposite sidewalls of the channel line not selected and to be turned off.
21. The method for operating the memory device according to claim 20, wherein the first bias voltage and the second bias voltage are respectively applied to a portion adjacent to the channel line to be turned on and a portion adjacent to the channel line to be turned off of the single string selection line.
22. The method for operating the memory device according to claim 16, further comprising applying a third bias voltage and a fourth bias voltage different from each other to the word lines of the stacked structures stacks on the two opposite sidewalls of the channel line.
23. The method for operating the memory device according to claim 22, wherein the third bias voltage is VPGM or VREAD, the fourth bias voltage is zero.
24. The method for operating the memory device according to claim 16, wherein the bit line, the string selection line, the word line and the ground selection line have a first type conductivity, the source element and the channel lines have a second type conductivity,
the selected channel line is turned on by a method comprising:
applying a zero voltage or grounding the source element below the selected channel line.
25. The method for operating the memory device according to claim 16, further comprising floating the second channel line, and applying a fifth bias voltage to the source element below the channel line unselected and to be turned off.
26. The method for operating the memory device according to claim 25, wherein the first type conductivity is P type conductivity, the second type conductivity is N type conductivity, the fifth bias voltage is a positive bias voltage.
0. 28. The memory device according to claim 27, including a source element contacting the first and second channel lines, and a bit line contacting the first and second channel lines, wherein the string selection lines, the word lines and the ground selection lines have a first type conductivity, and the source element, the first and second channel lines and the bit line have a second type conductivity opposite to the first type conductivity.
0. 29. The memory device according to claim 27, including a source element contacting the first and second channel lines, and a bit line contacting the first and second channel lines, wherein the bit line, the string selection lines, the word lines and the ground selection line have a first type conductivity, and the source element and the first and second channel lines have a second type conductivity opposite to the first type conductivity.
0. 30. The memory device according to claim 27, including a source element contacting the first and second channel lines, and a bit line contacting the first and second channel lines, wherein the bit line has a first type conductivity, and the first and second channel lines have a second type conductivity opposite to the first type conductivity.
0. 31. The memory device according to claim 27, including a source element contacting the first and second channel lines, and a bit line contacting the first and second channel lines, wherein the first channel line and the bit line form a PN diode.
0. 32. The memory device according to claim 27, including a source element in electrical communication with the first and second channel lines, and a bit line in electrical communication with the first and second channel lines.
0. 33. The memory device according to claim 27, including a source element disposed below and contacting the first and second channel lines, and a bit line disposed above and contacting the first and second channel lines.
0. 35. The method of claim 34, including:
disposing a source element comprising source lines below and contacting the first and second channel lines; and
disposing a bit line above and contacting the first and second channel lines.
0. 37. The method for operating the memory device according to claim 36, wherein the string selection lines, the word lines and the ground selection lines have a first type conductivity, the source element, the channel element and the bit line have a second type conductivity opposite to the first type conductivity; and
wherein the first type conductivity is P type conductivity, the second type conductivity is N type conductivity, the first bias voltage is a positive bias voltage, and the second bias voltage is a negative bias voltage.
0. 38. The method for operating the memory device according to claim 36, wherein the first bias voltage is VPGM or VREAD.
0. 39. The method for operating the memory device according to claim 36, wherein the bit lines, the string selection lines, the word lines and the ground selection lines have a first conductivity type, and the source element and the channel lines have a second conductivity type.
BACKGROUND

1. Technical Field

The disclosure relates in general to a memory device, a manufacturing method and an operating method of the same and more particularly to a 3D vertical gate channel memory device, for example, comprising a NAND flash memory and a anti-fuse memory, etc. The memory device has the architecture scalable below 30 nm (half pitch) in both X and Y direction. Therefore, the memory device has a high element density.

FIG. 20 is a three dimensional view of a memory device in one embodiment. FIG. 20 does not shown a portion of the insulating line 217 between the channel lines 219, 221, 223. Namely, the insulating line 217 should be as continuous as the string selection lines 224, 226, 228, 230, the word lines 218, 220 and the ground selection lines 222. Referring to FIG. 20, for example, in one embodiment, the string selection lines 224, 226, 228, 230, the word lines 218, 220, and the ground selection lines 222 have P+ type conductivity; the source elements 238 and the bit lines 240 have N+ type conductivity; and the channel lines 219, 221, 223, 232, 234, 236 have N type conductivity. A method for operating the memory device comprises applying bias voltages to the word lines 218, 220 and the ground selection lines 222 of the stacked structures 208, 210, 212, 214, 216 by common contact structures 202, 204, 206. For example, a bias voltage VPGM or VREAD is applied to the word lines 218. A bias voltage VPASS is applied to the word lines 220. In addition, a zero voltage (for PGM) is applied to the ground selection lines 222. Alternatively, a bias voltage Vcc (for read) is applied to the ground selection lines 222. Therefore, recoding for the word lines 218, 220 is easy. In this embodiment, the string selection lines 224, 226, 228, and 230 are separately decoded. The selected channel line 232 is turned on by applying a positive bias voltage (+Vcc, such as +3.3 V) to the string selection lines 226, 228 of the stacked structures 210, 212 on the two opposite sidewalls of the selected channel line 232. In order to avoid disturbing to the adjacent unselected channel lines 234, 236, a negative bias voltage (−Vcc, such as −3.3 V) may be applied to the string selection lines 224, 230 of the stacked structures 208, 214 on one sidewall of the channel lines 234, 236 to turn off the adjacent SSL transistor. A far string selection line 231 could be applied a zero voltage or grounded simply. During reading, a positive bias voltage (for example, +Vcc such as +5V) may be applied to the substrate 237 used as the bottom gate for reducing the resistance of the source elements 238.

FIG. 21 is a three dimensional view of a memory device in one embodiment. The conductivity types of the elements of the memory device of FIG. 21 are similar with the conductivity types of the elements of the memory device of FIG. 20. Therefore, it is described again in detail. Referring to FIG. 21, a method for operating the memory device comprises applying bias voltages to the word lines 314, 316 and the ground selection lines 318 of the stacked structures 308 310, 312 by common contact structures 302, 304, 306. For example, a bias voltage VPGM or VREAD is applied to the word lines 314. A bias voltage VPASS is applied to word lines 136. In addition, a zero voltage is applied to the ground selection lines 318 (for PGM). Alternatively, a bias voltage Vcc is applied to the ground selection lines 318 (for read). The selected channel line 336 is turned on by applying a positive bias voltage (such as +3.3 V) to the string selection lines 320, 322 of the stacked structures 308, 310 on the two opposite sidewalls 340, 342 of the selected channel line 336 through the contact structure 326. For example, the string selection lines 322, 324 of the stacked structures 310, 312 on the two opposite sidewalls 344, 346 of the unselected channel lines 338 to be turned off are applied a zero voltage or grounded. The positive bias voltage for turn-on and the zero voltage for turn-off are respectively applied to a portion adjacent to the turned-on channel line 336 and a portion adjacent to the turned-off channel lines 338 of the single string selection line 322.

FIG. 22 is a three dimensional view of a memory device in one embodiment. The conductivity types of the elements of the memory device of FIG. 22 are similar with the conductivity types of the elements of the memory device of FIG. 20. Therefore, it is described again in detail. Referring to FIG. 22, a method for operating the memory device comprises applying bias voltages to the ground selection lines 414 of the stacked structures 404, 406, 408, 410, 412 by a common contact structure 402. In one embodiment, the word lines 426, 428, 430, 432 are divided into, for example, an odd group of the word lines 428, 432 and an even group of the word lines 426, 430. The different groups are applied voltages separately. For example, a VREAD or VPGM is applied to the odd group of the word lines 428, 432. The even group of the word lines 426, 430 is applied with a zero voltage or grounded. In one embodiment, a positive bias voltage (such as +3.3 V) is applied to the ground selection lines 414. The selected channel line 446 is turned on by applying a positive bias voltage (such as +3.3 V) to the string selection lines 418, 420 of the stacked structures 406, 408 on the two opposite sidewalls 450, 452 of the channel line 446. A VREAD or VPGM is applied to the word line 428 of the stacked structure 406. A zero voltage is applied to the word line 430 of the stacked structure 408. Therefore, only one ONONO structure on the sidewall 450 is selected to be programmed or read so that physically two-bit/cell can be achieved. A negative bias voltage (such as −3.3 V) may be applied to the string selection lines 416, 422 of the stacked structures 404, 410 on one sidewall of the unselected channel lines 444, 448. A far string selection line 424 could be applied a zero voltage or grounded.

FIG. 23 is a three dimensional view of a memory device in one embodiment. The conductivity types of the elements of the memory device of FIG. 23 are similar with the conductivity types of the elements of the memory device of FIG. 20, except that the bit lines 502 have P+ type conductivity in FIG. 23. The bit line 502 and the channel line 512 (or the channel line 514) (N type conductivity) form a PN diode. In one embodiment, a positive bias voltage (such as +3.3V) is applied to the string selection lines 504. A bias voltage VPGM or VREAD is applied to the word lines 506. A bias voltage VPASS is applied to the word lines 508. A zero voltage is applied to the ground selection lines 510 for PGM. A bias voltage Vcc is applied to the ground selection lines 510 for read. In one embodiment, during reading, the source element 516 below the channel line 512 is applied a zero voltage or grounded. The source element 518 below, for example, the unselected channel line 514 to be turned off is floating or applied a positive bias voltage (such as +Vcc). Since the diode formed by the bit line 502 and the channel line 512 (or the channel line 514) does not allow reverse current, the unselected source element 518 would not be read. FIG. 24 shows a proposed waveform for decoding in some embodiments. Referring to FIG. 24, during T1 period, source line self-boosting is performed by a Vcc on the GSL and unselected SL. Vch is boosted for Cell C and D. During T2 period, bit-line self-boosting is performed by a Vcc on the SSL and unselected BL. Vch is boosted for Cell B. The boosted Vch of Cell C does not leak out due to the PN diode at BL. During T3 period, programming Cell A is started. The inversion channel is already formed during T1 and T2 periods and it can be programmed even SSL/GSL is turned-off. In addition, Cell E is the Vpass disturb, which is not a serious concern if Vpass<10V.

FIG. 25 shows a layout of a memory device in one embodiment. The bottom diffusion source lines must be connected to metal source line periodically to reduce the source resistance. It can be fan-out like the proposed layout. Optionally, source lines can be separated in even/odd pairs, which also allows flexible selectivity for the array. The source line contact can facilitate the sidewall ONONO for self-aligned contact (SAC). The diffusion bit lines are connected to metal bit lines periodically to reduce the resistance. WL's of each layer can be shared or grouped into even/odd, and connect to WL decoder. The top SSL gates are connected to the SSL decoder.

While the disclosure has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

INVENTORS:

Chen, Shih-Hung, Lue, Hang-Ting

THIS PATENT IS REFERENCED BY THESE PATENTS:
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