Regulators regulating charge pump and memory circuits thereof

Abstract

A regulator for regulating a charge pump is provided. The regulator includes a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump. The first voltage is associated with an output voltage of the charge pump. The second voltage is associated with an internal power voltage and a reference voltage V_ref.

Description

R₆/(R₅+R₆) (R₅+R₆)/R₆. To substantially couple the voltage VDD/K to an output end 230a of the means 230, the resistance R₃ can be substantially larger than the resistances R₅ and/or R₆.

For example, the resistance R₃ can be about ten times or more of the resistance R₅ or R₆. In some embodiments, the resistance R₃ can be about 100 KΩ or more and the resistance R₅ or R₆ can be about 10 KΩ.

In some embodiments, the voltage divider 250 can include resistors, diodes, other suitable devices, and/or combinations thereof. For example, the voltage divider 250 can include resistors having a seventh resistance R₇ and an eighth resistance R₈. The output end 250a of the voltage divider 250 is between the resistors having resistances R₇ and R₈ and coupled with the resistor having the resistance R₄. In embodiments, the output end 250a of the voltage divider 250 is capable of providing a voltage V_ref/K, wherein K is equal to R₈/(R₇+R₈) (R₇+R₈)/R₈. To substantially couple the voltage V_ref/K to an output end 230a of the means 230, the resistance R₄ can be substantially larger than the resistances R₇ and/or R₈. For example, the resistance R₄ can be about ten times or more of the resistance R₇ or R₈. The resistance R₄ can be about 100 KΩ or more and the resistance R₇ or R₈ can be about 10 KΩ. In some embodiments, the resistances R₃ and R₄ can have the same resistance, the resistances R₅ and R₇ can have the same resistance, and the resistances R₆ and R₈ can have the same resistance. It is noted that the resistances, number of the resistors, and the configuration of the voltage dividers described above are mere examples. The scope of the disclosure is not limited thereto.

Referring again to FIG. 2, the resistors having the resistances R₃ and R₄ can be parallel. Since the voltage VDD/K and voltage V_ref/K can be substantially coupled to the output end 230a of the means 230, the output end 230a of the means 230 is capable of providing the second voltage (VDD+V_ref)/2K to the input end 210b of the comparator 210. As noted, the first voltage VPP/2K is applied to the first end 210a of the comparator 210 and the second voltage (VDD+V_ref)/2K is applied to the second end 210b of the comparator 210. Since the voltages are provided to the comparator 210 by the amplifier-free means, e.g., voltage dividers, signals representing the pump voltage VPP output from the charge pump 130 and signals representing the internal voltage VDD and the reference voltage V_ref can be swiftly applied to the comparator 210. Unlike the conventional voltage regulator having at least two stage amplifiers, the regulator 140 can substantially reduce the delays for enabling or disabling the charge pump 130.

In some embodiments, the output end (not labeled) of the comparator 210 can be coupled with at least one inverter, e.g., inverters 260 and 270, to rectify signals from the comparator 210. For example, the output signal from the comparator 210 is output to enable the charge pump 130 (shown in FIG. 1). The inverter 260 inverts the enable output signal to a disable signal. The inverter 270 then inverts the disable signal to a rectified enable signal. It is noted that the number and type of the inverters 260 and 270 may vary depending on the type of the output signals from the comparator 210 for enabling or disabling the charge pump 130. The scope of the disclosure is not limited thereto.

FIG. 4 is a schematic drawing showing a system including an exemplary memory circuit. In FIG. 4, a system 400 can include a processor 410 coupled with the memory circuit 100. The processor 410 is capable of accessing the datum stored in the memory cell 101a (shown in FIG. 1) of the memory circuit 100. In some embodiments, the processor 410 can be a processing unit, central processing unit, digital signal processor, or other processor that is suitable for accessing data of memory circuit.

In some embodiments, the processor 410 and the memory circuit 100 can be formed within a system that can be physically and electrically coupled with a printed wiring board or printed circuit board (PCB) to form an electronic assembly. The electronic assembly can be part of an electronic system such as computers, wireless communication devices, computer-related peripherals, entertainment devices, or the like.

In embodiments, the system 400 including the memory circuit 100 can provides an entire system in one IC, so-called system on a chip (SOC) or system on integrated circuit (SOIC) devices. These SOC devices may provide, for example, all of the circuitry needed to implement a cell phone, personal data assistant (PDA), digital VCR, digital camcorder, digital camera, MP3 player, or the like in a single integrated circuit.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A regulator for regulating a charge pump, the regulator comprising:

a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump, wherein the first voltage is associated with an output voltage of the charge pump and the second voltage is associated with an internal power voltage and a reference voltage V_ref;

wherein a first voltage divider is coupled between the internal power voltage and ground, a second voltage divider is coupled between the reference voltage V_ref and ground, and the second input end of the comparator is coupled with an output end of the first voltage divider and an output end of the second voltage divider.

2. The regulator of claim 1, wherein the output voltage of the charge pump is a pump voltage VPP, the first voltage is VPP/2K, the internal power voltage is VDD, the second voltage is (VDD+V_ref)/2K, and K is a factor that is capable of maintaining at least one transistor of the comparator operating at a saturation mode.

3. The regulator of claim 2 further comprising a first third voltage divider having an output end coupled with the first input end of the regulator, wherein the first third voltage divider being coupled with the charge pump.

4. The regulator of claim 3, wherein the first third voltage divider comprises a first resistor having a first resistance (R₁) and a second resistor having a second resistance (R₂), the output end of the first third voltage divider is between the first and second resistors, and K is equal to (R₁+R₂)/2R₂.

5. The regulator of claim 2 further comprising a means for providing the second voltage being coupled with the comparator.

6. The regulator of claim 5 1, wherein the means for providing the second voltage comprises:

a second voltage divider coupled between the internal power voltage VDD and ground, the second first voltage divider having an the output end coupled with a third resistor having a third resistance (R₃); and

a third voltage divider coupled between the reference voltage V_ref and ground, the third second voltage divider having an the output end coupled with a fourth resistor having a fourth resistance (R₄).

7. The regulator of claim 6, wherein the second first voltage divider comprises a fifth resistor having a fifth resistance (R₅) and a sixth resistor having a sixth resistance (R₆), the output end of the second first voltage divider is between the fifth and sixth resistors, and K is equal to R₆/(R₅+R₆) (R₅+R₆)/R₆.

8. The regulator of claim 7, wherein the third resistance R₃ is about ten times or more of the fifth resistance R₅ or the sixth resistance R₆.

9. The regulator of claim 6, wherein the third second voltage divider comprises a seventh resistor having a seventh resistance (R₇) and an eighth resistor having an eighth resistance (R₈), the output end of the third second voltage divider is between the seventh and eighth resistors, and K is equal to R₈/(R₇+R₈) (R₇+R₈)/R₈.

10. The regulator of claim 9, wherein the fourth resistance R₄ is about ten times or more of the seventh resistance R₇ or the eighth resistance R₈.

11. A memory circuit comprising:

at least one memory cell for storing a charge representative of a datum, the memory cell being coupled with a word line and a bit line;

a charge pump coupled with the word line; and

a regulator for regulating the charge pump, the regulator comprising a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump, wherein the first voltage is associated with an output voltage of the charge pump and the second voltage is associated with an internal power voltage and a reference voltage V_ref;

wherein a first voltage divider is coupled between the internal power voltage and ground, a second voltage divider is coupled between the reference voltage V_ref and ground, and the second input end of the comparator is coupled with an output end of the first voltage divider and an output end of the second voltage divider.

12. The memory circuit of claim 11, wherein the output voltage is a pump voltage VPP, the first voltage is VPP/2K, the internal power voltage is VDD, the second voltage is (VDD+V_ref)/2K, and K is a factor that is capable of maintaining at least one transistor of the comparator operating at a saturation mode.

13. The memory circuit of claim 12, wherein the regulator further comprises a first third voltage divider having an output end coupled with the first input end of the regulator, wherein the first third voltage divider being coupled with the charge pump.

14. The memory circuit of claim 13, wherein the first third voltage divider comprises a first resistor having a first resistance (R₁) and a second resistor having a second resistance (R₂), the output end of the first third voltage divider is between the first and second resistors, and K is equal to (R₁+R₂)/2R₂.

15. The memory circuit of claim 12, wherein the regulator further comprises a means for providing the second voltage being coupled with the comparator.

16. The memory circuit of claim 15 11, wherein the means for providing the second voltage comprises:

a second voltage divider coupled between the internal power voltage VDD and ground, the second first voltage divider having an the output end coupled with a third resistor having a third resistance (R₃); and

a third voltage divider coupled between the reference voltage V_ref and ground, the third second voltage divider having an the output end coupled with a fourth resistor having a fourth resistance (R₄).

17. The memory circuit of claim 16, wherein the second first voltage divider comprises a fifth resistor having a fifth resistance (R₅) and a sixth resistor having a sixth resistance (R₆), the output end of the second first voltage divider is between the fifth and sixth resistors, and K is equal to R₆/(R₅+₆) (R₅+R₆)/R₆.

18. The memory circuit of claim 17, wherein the third resistance R₃ is about ten times or more of the fifth resistance R₅ or the sixth resistance R₆.

19. The memory circuit of claim 16, wherein the third second voltage divider comprises a seventh resistor having a seventh resistance (R₇) and an eighth resistor having an eighth resistance (R₈), the output end of the third second voltage divider is between the seventh and eighth resistors, and K is equal to R₈/(R₇+R₈) (R₇+R₈)/R₈.

20. The memory circuit of claim 19, wherein the fourth resistance R₄ is about ten times or more of the seventh resistance R₇ or the eighth resistance R₈.

21. The regulator of claim 1, wherein the output voltage of the charge pump is a pump voltage VPP, the first voltage is VPP/2K, the internal power voltage is VDD, the second voltage is (VDD+V_ref)/2K, and K is a predetermined number.

22. The memory circuit of claim 11, wherein the output voltage is a pump voltage VPP, the first voltage is VPP/2K, the internal power voltage is VDD, the second voltage is (VDD+V_ref)/2K, and K is a predetermined number.