Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.
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0. 15. A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:
performing a first program loop; and
performing a second program loop;
wherein the first program loop comprising:
during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline corresponding to a first data value among the plurality of data values; and
during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline corresponding to a third data value among the plurality of data values,
wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,
a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,
each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,
the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously;
physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one first memory cell and at least one other memory cell adjacent to the at least one first memory cell;
the first programming pulse and the second programming pulse are successively applied to the wordline.
0. 23. A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:
during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline corresponding to a first data value among the plurality of data values;
during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline corresponding to a third data value among the plurality of data values; and
during a verification time after the applying the first programming pulse and the second programming pulse, applying successively, to the wordline, a first wordline verification pulse corresponding to the first data value, a second wordline verification pulse corresponding to the second data value and a third wordline verification pulse corresponding to the third data value,
wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,
a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,
each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,
the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously;
physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one first memory cell and at least one other memory cell adjacent to the at least one first memory cell;
the first programming pulse and the second programming pulse are successively applied.
0. 31. A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:
during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline corresponding to a first data value among the plurality of data values;
during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline corresponding to a third data value among the plurality of data values; and
during a verification time after the applying the first programming pulse and the second programming pulse, applying successively, to the wordline, a first wordline verification pulse corresponding to the first data value, a second wordline verification pulse corresponding to the second data value and a third wordline verification pulse corresponding to the third data value,
wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,
a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,
each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,
the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously;
physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one second memory cell and at least one other memory cell adjacent to the at least one first memory cell;
the first programming pulse and the second programming pulse are successively applied.
0. 39. A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:
during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline, the at least one first bitline corresponding to a first data value among the plurality of data values;
during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline, the at least one second bitline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline, the at least one third bitline corresponding to a third data value among the plurality of data values; and
during a verification time, applying, to the wordline, a first wordline verification pulse corresponding to the first data value, a second wordline verification pulse corresponding to the second data value and a third wordline verification pulse corresponding to the third data value,
wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,
a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,
each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,
the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously,
physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one first memory cell and at least one other memory cell adjacent to the at least one first memory cell, and
the first programming pulse and the second programming pulse are successively applied.
0. 47. A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:
during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline, the at least one first bitline corresponding to a first data value among the plurality of data values;
during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline, the at least one second bitline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline, the at least one third bitline corresponding to a third data value among the plurality of data values; and
during a verification time after the applying the first programming pulse and the second programming pulse, applying, to the wordline, a first wordline verification pulse corresponding to the first data value, a second wordline verification pulse corresponding to the second data value and a third wordline verification pulse corresponding to the third data value,
wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,
a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,
each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,
the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously,
physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one first memory cell and at least one other memory cell adjacent to the at least one first memory cell, and
the first programming pulse and the second programming pulse are successively applied.
0. 1. A method of programming memory cells of a multi-level cell non-volatile memory to one of a plurality of data values, the method comprising:
applying a first programming pulse to a wordline of the non-volatile memory device and a first bitline voltage to at least one first bitline associated with the wordline corresponding to a first data value among a plurality of data values;
applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline associated with the wordline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline associated with the wordline corresponding to a third data value among the plurality of data values,
wherein a voltage level of the second programming pulse is different from a level of the first programming pulse,
the second bitline voltage is different from the third bitline voltage if the second data value and third data value are different,
the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously, and
a time interval required to apply both the first programming pulse and the second programming pulse to the wordline is sufficiently small to preclude substantial capacitive coupling between physically proximate memory cells in the nonvolatile memory device.
0. 2. The method of
0. 3. The method of
after applying the second programming pulse, applying at least one of a sequence of verifying voltages to the respective bitlines, wherein a level of the at least one of the sequence of verifying voltages varies in accordance with the data value to be programmed to the memory cell.
0. 4. The method of
0. 5. The method of
0. 6. The method of
applying the first programming pulse to the wordline and the first bitline voltage to the at least one first bitline, and then applying the second programming pulse to the wordline and the second bitline voltage to the at least one second bitline and the third bitline voltage to the at least one third bitline voltage, and then applying the at least one of the sequence of verifying voltages to the bitline.
0. 7. The method of
0. 8. The method of
0. 9. A method of programming a non-volatile memory device comprising a first memory cell connected to a wordline and a first bitline and a second memory cell connected to the wordline and a second bitline, wherein the first memory cell and second memory cell are multi-level non-volatile memory cells capable of being programmed to 1st through Mth data values, the method comprising:
performing a programming operation during which the first memory cell is programmed to an ith data value among the 1st through Mth data values using a first programming pulse applied to the wordline, and the second memory cell is programmed to a jth data value among the 1st through Mth data values using a second programming pulse different from the first programming pulse and applied to the wordline, the programming operation comprising:
simultaneously applying a first bitline voltage having a first level and corresponding to the ith data value to the first bitline, and a second bitline voltage having a second level different from the first level and corresponding to the jth data value to the second bitline; and
performing a verifying operation on the first memory cell and second memory cell, wherein execution timing for the verifying operation varies in relation to the 1st through Mth data values,
wherein a time interval required to apply both the first programming pulse and the second programming pulse to the wordline is sufficiently small to preclude substantial capacitive coupling between either the first memory cell and the second memory and at least one other memory cell physically proximate to the at least one of the first memory cell and the second memory cell.
0. 10. The method of
applying at least one of a sequence of verifying voltages to the first and second bitlines, wherein respective levels of the sequence of verifying voltages vary in accordance with a corresponding one of the 1st through Mth data values.
0. 11. The method of
the verifying operation comprises applying up to a first number of verifying voltages to verify the programming of the ith data value and applying up to a second number of verifying voltages to verify the programming of the jth data value, wherein the first number is greater than the second number.
0. 12. The method of
0. 13. An iterative method of programming memory cells of a multi-level cell non-volatile memory to one of a plurality of data values, the iterative method comprising multiple programming loops, wherein each programming loop comprises:
applying a first programming pulse to a wordline of the non-volatile memory device, and applying a first bitline voltage corresponding to a first data value among a plurality of data values to a first bitline;
applying a second programming pulse having a level different from a level of the first programming pulse to the wordline after applying the first programming pulse to the wordline, and applying a second bitline voltage corresponding to a second data value among the plurality of data values to a second bitline, and applying a third bitline voltage corresponding to a third data value among the plurality of data values to a third bitline, wherein the second bitline voltage is applied to the second bitline and the third bitline voltage is applied to the third bitline simultaneously, wherein the second bitline voltage is different from the third bitline voltage if the second data value and third data value are different; and
after applying the second programming pulse, applying at least one of a sequence of verifying voltages to the first bitline and the second bitline, wherein a level of the at least one of the sequence of verifying voltages varies in accordance with a data value being programmed to the memory cell.
0. 14. The method of
0. 16. The method of claim 15, wherein the second program loop comprising:
applying the first programming pulse to the wordline; and
applying the second programming pulse to the wordline.
0. 17. The method of claim 15, wherein, during the first program time, applying the program inhibit voltage to the at least one second bitline and the at least one third bitline concurrently with the applying the first bitline voltage to the at least one first bitline.
0. 18. The method of claim 16, wherein, during the second program time, applying the program inhibit voltage to the at least one first bitline concurrently with the applying the second bitline voltage to the at least one second bitline.
0. 19. The method of claim 15, wherein a first programming operation corresponding to the first data value and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed in a same program loop.
0. 20. The method of claim 15, wherein the second programming pulse is applied to the wordline after the applying the first programming pulse.
0. 21. The method of claim 15, wherein during a verification time after the applying the first programming pulse and the applying the second programming pulse, a first verification pulse, a second verification pulse and a third verification pulse are applied to the wordline successively.
0. 22. The method of claim 21, wherein a voltage level of the first verification pulse is lower than a voltage level of the second verification pulse, and
the voltage level of the second verification pulse is lower than a voltage level of the third verification pulse.
0. 24. The method of claim 23, wherein, during the first program time, applying the program inhibit voltage to the at least one second bitline and the at least one third bitline concurrently with the applying the first bitline voltage to the at least one first bitline.
0. 25. The method of claim 24, wherein, during the second program time, applying the program inhibit voltage to the at least one first bitline concurrently with the applying the second bitline voltage to the at least one second bitline.
0. 26. The method of claim 23, wherein a first programming operation corresponding to the first data value and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed substantially simultaneously.
0. 27. The method of claim 23, wherein a first programming operation corresponding to the first data value and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed at a same program loop.
0. 28. The method of claim 23, wherein the second programming pulse is applied to the wordline after the applying the first programming pulse.
0. 29. The method of claim 23, wherein the first wordline verification pulse, the second wordline verification pulse and the third wordline verification pulse are applied to the wordline successively.
0. 30. The method of claim 29, wherein a voltage level of the first wordline verification pulse is lower than a voltage level of the second wordline verification pulse, and
the voltage level of the second wordline verification pulse is lower than a voltage level of the third wordline verification pulse.
0. 32. The method of claim 31, wherein, during the first program time, applying the program inhibit voltage to the at least one second bitline and the at least one third bitline concurrently with the applying the first bitline voltage to the at least one first bitline.
0. 33. The method of claim 32, wherein, during the second program time, applying the program inhibit voltage to the at least one first bitline concurrently with the applying the second bitline voltage to the at least one second bitline.
0. 34. The method of claim 31, wherein a first programming operation corresponding to the first data value and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed substantially simultaneously.
0. 35. The method of claim 31, wherein a first programming operation corresponding to the first data value and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed at a same program loop.
0. 36. The method of claim 31, wherein the second programming pulse is applied to the wordline after the applying the first programming pulse.
0. 37. The method of claim 31, wherein the first wordline verification pulse, the second wordline verification pulse and the third wordline verification pulse are applied to the wordline successively.
0. 38. The method of claim 37, wherein a voltage level of the first wordline verification pulse is lower than a voltage level of the second wordline verification pulse, and
the voltage level of the second wordline verification pulse is lower than a voltage level of the third wordline verification pulse.
0. 40. The method of claim 39, wherein, during the first program time, applying the program inhibit voltage to the at least one second bitline and the at least one third bitline concurrently with the applying the first bitline voltage to the at least one first bitline.
0. 41. The method of claim 40, wherein, during the second program time, applying the program inhibit voltage to the at least one first bitline concurrently with the applying the second bitline voltage to the at least one second bitline.
0. 42. The method of claim 40, wherein a first programming operation corresponding to the first data value, and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed substantially simultaneously.
0. 43. The method of claim 40, wherein a first programming operation corresponding to the first data value, and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed at a same program loop.
0. 44. The method of claim 39, wherein the second programming pulse is applied to the wordline after the applying the first programming pulse.
0. 45. The method of claim 39, wherein the first wordline verification pulse, the second wordline verification pulse and the third wordline verification pulse are applied to the wordline successively.
0. 46. The method of claim 45, wherein a voltage level of the first wordline verification pulse is lower than a voltage level of the second wordline verification pulse, and
the voltage level of the second wordline verification pulse is lower than a voltage level of the third wordline verification pulse.
0. 48. The method of claim 47, wherein, during the first program time, applying the program inhibit voltage to the at least one second bitline and the at least one third bitline concurrently with the applying the first bitline voltage to the at least one first bitline.
0. 49. The method of claim 48, wherein, during the second program time, applying the program inhibit voltage to the at least one first bitline concurrently with the applying the second bitline voltage to the at least one second bitline.
0. 50. The method of claim 48, wherein a first programming operation corresponding to the first data value, and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed substantially simultaneously.
0. 51. The method of claim 48, wherein a first programming operation corresponding to the first data value, and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed at a same program loop.
0. 52. The method of claim 47, wherein the second programming pulse is applied to the wordline after the applying the first programming pulse.
0. 53. The method of claim 47, wherein the first wordline verification pulse, the second wordline verification pulse and the third wordline verification pulse are applied to the wordline successively.
0. 54. The method of claim 53, wherein a voltage level of the first wordline verification pulse is lower than a voltage level of the second wordline verification pulse, and
the voltage level of the second wordline verification pulse is lower than a voltage level of the third wordline verification pulse.
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This application claims the benefit of Korean Patent Application No. 10-2008-0017409 filed on Feb. 26, 2008, the subject matter of which is hereby incorporated entirety by reference.
The present invention relates to a method of programming a non-volatile memory device. More particularly, the invention relates to a method of programming a non-volatile memory device which requires less time for programming and is capable of reducing coupling effect due to a programming sequence and/or cell distribution.
Non-volatile memory devices are electrically programmable and erasable and are able to retain stored data when supplied power is interrupted. Flash memory is one type of non-volatile memory and uses an electrical charge to store data. Each of the memory cells forming a flash memory device includes a control gate, a charge storage layer, and a cell transistor having a source and a drain. The flash memory device changes the data value stored by a memory cell by controlling the quantity of charge accumulated on the charge storage layer of the memory cell.
The cell transistor of the flash memory device controls the quantity of charge stored on the charge storage layer using the so-called F-N tunneling phenomenon. An erase operation may be performed in relation to a cell transistor by applying a ground voltage to the control gate and by applying a voltage higher than a constituent power supply voltage to the semiconductor substrate (or bulk). Under these erase bias conditions, a strong electric field is formed between the charge storage layer and the semiconductor bulk due to a large difference in the electrical resistances of same. As a result, charge accumulated on the charge storage layer is discharged by F-N tunneling, and the critical voltage of the erased cell transistor decreases.
A programming operation may be performed in relation to the cell transistor by applying a voltage higher than the power supply voltage to the control gate and applying a ground voltage to the drain, as well as the semiconductor bulk. Under these programming bias conditions, charge accumulates on the charge storage layer due to F-N tunneling, and the critical voltage of the cell transistor increases.
Hence, a memory cell state in which charge is relatively absent from the charge storage layer and the corresponding critical voltage of the cell transistor is negative is conventionally referred to as an erased state. Further, a memory cell state in which charge accumulates on the charge storage layer and the corresponding critical voltage of the cell transistor is greater than zero is referred to as a programmed state.
Embodiments of the invention provide a programming method for a non-volatile device which is capable of reducing coupling effects commonly associated with a programming sequence and/or cell distribution.
In one embodiment, the invention provides a programming method for a multi-level cell non-volatile memory device. The method includes; applying a first programming pulse to a wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage level of the second programming pulse is different from that of the first programming pulse, and applying bitline voltages to respective bitlines associated with the wordline, wherein the bitline voltages vary in accordance with a plurality of data bit values to be programmed to a plurality of memory cells associated with the word line and bitlines and in response to either the first programming pulse or the second programming pulse.
In another embodiment, the invention provides a method of programming a non-volatile memory device, the method comprising; performing a programming operation during which at least one programming pulse that varies in relation to a plurality of 1st through Mth data bit values to be programmed to a plurality of memory cells connected to a wordline is applied to the wordline, and thereafter performing a verifying operation, wherein execution timing of the verifying operation varies in relation to the plurality 1st through Mth data bit values.
In another embodiment, the invention provides a method of programming a non-volatile memory device, the method comprising; applying first through Nth, where is a natural integer greater than 1, programming pulses to a word line, wherein respective voltage levels for the first through Nth programming pulses are different, and applying bitline voltages to respective bitlines associated with the wordline, wherein the bitline voltages vary in accordance with a plurality of data bit values to be programmed to a plurality of memory cells associated with the word line and bitlines and in response to either the first programming pulse or the second programming pulse.
Several embodiments of the invention will now be described with reference to the attached drawings. The invention may, however, be variously embodied and should not be construed as being limited to only the illustrated embodiments. Rather, the embodiments are presented as examples teaching the making and use of the invention. Throughout the drawings and written description, like reference indicators are used to denote like or similar elements.
In similar manner, where the value of the first data bit is ‘1’, the non-volatile memory cell initially remains in the first voltage distribution (VTHD1), assuming an initially erased state. Subsequently, where the value of a second bit of data to be programmed is also ‘0’, the critical voltage of the non-volatile memory cell is changed to the fourth voltage distribution (VTHD4). (See, operation 2-1 in
In the example shown in
For example, the upper diagram shown in
The non-volatile memory devices shown in
Number 0 through 6 shown in
In the non-volatile memory device shown in
Numbers 0 through 12 shown in
At this point in the programming operation described in relation to
Referring to
At this point, as shown in
As suggested by
This difference in programming time causes a problem, as shown in
Hereinafter, methods of programming a non-volatile memory device according to certain embodiments of the invention will be described. These embodiments provide methods that prevent capacitive coupling effects due to programming sequence and/or cell distribution.
Referring to
In this case, the non-volatile memory device of
Referring to
In other words, the second programming operation P2 and the third programming operation P3, respectively corresponding to the fourth and third bit values 10 and 00, may be performed simultaneously by applying the second programming pulse (PPLS2) of
Referring collectively to
For example, like the embodiment shown in
As shown in
However, when the bit value to be programmed is 01, the bitlines do not receive the second programming pulse (PPLS2), and an inhibit voltage Vdd may be applied to the bitlines not programmed by the second programming pulse (PPLS2) the corresponding bitlines so as to deactivate the bitlines. Likewise, for a section ‘d2’ of the programming sequence shown in
Referring back to
Although
If sufficient margin may be obtained, more than two bit values may be programmed by a single programming pulse. Thus, the present invention subsumes embodiments capable of programming with a single programming pulse.
Although
Referring to
More particularly, a first programming pulse (PPLS1) is applied to a corresponding wordline of the non-volatile memory device, a second programming pulse (PPLS2) having a different voltage from that of the first programming pulse (PPLS1) is applied to the wordline, and a third programming pulse (PPLS3) having a different voltage from those of the first programming pulse (PPLS1) and the second programming pulse (PPLS2) is applied to the wordline. In like manner to the method of programming the two bits multi-level cell flash memory device, the first through third programming pulse (PPLS1 through PPLS3) can be activated successively.
Thus, the first programming operation P1 may be performed in response to the first programming pulse (PPLS1), the second programming operation P2 may be performed in response to the second programming pulse (PPLS2), and the third programming operation P3 may be performed in response to the third programming pulse (PPLS3).
At this point, programming operations simultaneously performed by a single programming pulse can program differently by applying different bitline voltages. For example, when the second and fourth programming operations P2 and P4 are simultaneously performed by the second programming pulse (PPLS2), bitline voltages different from each other, such as 0V, V1, and V2, may be applied to bitlines connected to memory cells corresponding to each of the second and fourth programming operations P2 and P4.
Also, the inhibit voltage Vdd may be applied to bitlines of memory cells corresponding to second through seventh programming operations P2 through P7 deactivated at a section in which the first programming pulse (PPLS1) is activated. The inhibit voltage Vdd may be applied to bitlines of memory cells corresponding to the first programming operation P1 and the fifth through seventh programming operation P5 through P7 which are not activated by the second programming pulse (PPLS2). Likewise, the inhibit voltage Vdd may be applied to bitlines of memory cells corresponding to first through fourth programming operations P1 through P4 which are deactivated in a section in which the third programming pulse (PPLS3) is activated.
Accordingly, a coupling effect due to a programming sequence can be prevented in multi-level cell flash memory devices having three or more bits.
Referring back to
For example, if the method of programming according to the present invention employs an incremental step pulse programming (ISPP),
At this point, verifying voltages applied to bitlines corresponding to bit values can have different magnitudes. However, the present invention is not limited thereto, and a plurality of bit values can be verified in a single verifying operation.
Accordingly, in the methods of programming a non-volatile memory device according to embodiments of the invention, the first through third programming operations P1 through P3 regarding to a plurality of bit values are completed simultaneously or substantially simultaneously as shown in
Referring to
The voltage levels of the verifying voltages Vvrf-1 through Vvrf-3 may be the same as what is shown in
Although
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by one of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention as defined by the following claims.
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