Disclosed herein is a semiconductor integrated circuit, wherein a desired circuit is formed by combining and laying out a plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized, the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (≥2) pairs of all the complementary transistor pairs are driven in phase, and the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N≥M≥2) times the basic cell length which is appropriate to the single complementary transistor pair.
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0. 9. A semiconductor integrated circuit comprising:
first voltage lines that extend in a first direction, the first direction differs from a second direction;
second voltage lines that extend in the first direction, one of the second voltage lines is between one of the first voltage lines and a different one of the first voltage lines;
a first active region of a first conductivity type, the first conductivity type differs from a second conductivity type;
a second active region of the second conductivity type, the first active region and the second active region are between the one of the first voltage lines and the one of the second voltage lines;
a third active region of the first conductivity type that an element isolation region isolates from the first active region and the second active region;
a fourth active region of the second conductivity type that the element isolation region isolates from the second active region and the third active region, the third active region and the fourth active region are between the one of the second voltage lines and the different one of the first voltage lines;
a multi-height standard cell, a cell length of the multi-height standard cell is a distance in the second direction from the one of the first voltage lines to the different one of the first voltage lines;
a first gate electrode configured to drive a plurality of complementary transistor pairs, the first gate electrode extends in the multi-height standard cell along the second direction while overlapping at least the first active region and the second active region and the third active region and the fourth active region;
a second gate electrode that is shorter than the first gate electrode, the second gate electrode extends in the multi-height standard cell along the second direction while overlapping at least the first active region; and
a branch between the first gate electrode and the second gate electrode, the branch extends in the first direction from the first gate electrode to the second gate electrode.
0. 1. A semiconductor integrated circuit, wherein
a desired circuit is formed by combining and laying out plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized,
the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (≥2) pairs of all the complementary transistor pairs are driven in phase, and
the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N≥M≥2) times the basic cell length which is appropriate to the single complementary transistor pair, and the common gate electrodes of at least M pairs of the N complementary transistor pairs to be driven in phase are arranged linearly in the direction of the M-fold cell length.
0. 2. The semiconductor integrated circuit of
single height cells or standard cells having the basic cell length and multi-height cells or the complementary in-phase driven standard cells having the M-fold cell length are arranged adjacent to each other to share power lines so as to form the desired circuit.
0. 3. The semiconductor integrated circuit of
the multi-height cell has a total of (M+1) power lines which is the sum of (M−1) power wirings that are arranged parallel to each other to extend in an arbitrary cell length direction orthogonal to the M-fold cell length with a separation pitch equal to the basic cell length obtained by dividing the M-fold cell length into M equal parts and two shared power wirings, each of which is shared with an adjacent cell at the center of the width of one of two cell boundaries, one on each side along the M-fold cell length,
the (M+1) power lines include source voltage lines and reference voltage lines that are alternately arranged, and
the single height cell connected to a pair of the source voltage line and reference voltage line arranged adjacent and parallel to each other is arranged adjacent to the multi-height cell in the arbitrary cell length direction.
0. 4. The semiconductor integrated circuit of
two active regions of the same conductivity type where transistors are respectively formed are arranged line-symmetrically with respect to the center line of the width of each of the (M−1) power wirings, and
the common gate electrodes are arranged linearly to intersect each of one of the active regions, power wirings and the other of the active regions.
0. 5. The semiconductor integrated circuit of
all the gate electrodes overlapping an element isolation region provided between the two active regions are the common gate electrodes extending from one of the two active regions to the other of the two active regions and intersecting the element isolation region.
0. 6. The semiconductor integrated circuit of
the (M+1) power lines and all intracell connection lines are formed with a first metal wiring layer, and
intercell signal lines are formed with a second metal wiring layer.
0. 7. The semiconductor integrated circuit of
the multi-height cell is a non-rectangular cell that surrounds the single height cell in an L-shaped manner by including first and second rectangular sections, the first rectangular section having the M-fold cell length in which M complementary transistor pairs of all the complementary transistor pairs to be driven in phase are arranged, and the second rectangular section extending along one of two sides that are opposed to each other in the direction of the standardized cell length of the first rectangular section.
0. 8. The semiconductor integrated circuit of
a plurality of standard cells forming the desired circuit include at least one non-rectangular standard cell that is L-shaped as a whole in plan view by comprising first and second rectangular sections, the first rectangular section having the M-fold cell length in which M complementary transistor pairs of all the complementary transistor pairs to be driven in phase are arranged, and the second rectangular section extending along one of two sides that are opposed to each other in the direction of the standardized cell length of the first rectangular section.
0. 10. A semiconductor integrated circuit as set forth in claim 9, further comprising:
a single height standard cell, a cell length of the single height standard cell is a distance in the second direction from the one of the second voltage lines to the one of the first voltage lines.
0. 11. A semiconductor integrated circuit as set forth in claim 10, wherein the third active region continuously extends in the first direction from within the multi-height standard cell to the single height cell.
0. 12. A semiconductor integrated circuit as set forth in claim 10, further comprising:
a third gate electrode in the single height cell, the third gate electrode overlaps at least the third active region.
0. 13. A semiconductor integrated circuit as set forth in claim 10, wherein the cell length of the multi-height standard cell is an integral multiple of the cell length of the single height standard cell.
0. 14. A semiconductor integrated circuit as set forth in claim 10, wherein the cell length of the multi-height standard cell is double the cell length of the single height standard cell.
0. 15. A semiconductor integrated circuit as set forth in claim 9, wherein the branch touches a side of the first gate electrode.
0. 16. A semiconductor integrated circuit as set forth in claim 9, wherein the branch touches an end of the second gate electrode.
0. 17. A semiconductor integrated circuit as set forth in claim 9, wherein the branch is between a substrate and the one of the first voltage lines.
0. 18. A semiconductor integrated circuit as set forth in claim 9, wherein the branch extends from the first gate electrode to the second gate electrode.
0. 19. A semiconductor integrated circuit as set forth in claim 9, wherein the branch is formed from an electrically conductive material.
0. 20. A semiconductor integrated circuit as set forth in claim 19, wherein the first gate electrode and the second gate electrode are formed from the electrically conductive material.
0. 21. A semiconductor integrated circuit as set forth in claim 9, wherein the first gate electrode intersects with the one of the second voltage lines.
0. 22. A semiconductor integrated circuit as set forth in claim 9, wherein a gate layer includes the first gate electrode, the second gate electrode, and the branch.
0. 23. A semiconductor integrated circuit as set forth in claim 22, wherein a first layer includes wiring.
0. 24. A semiconductor integrated circuit as set forth in claim 23, wherein a second layer includes the first voltage lines and the second voltage lines.
0. 25. A semiconductor integrated circuit as set forth in claim 24, wherein the gate layer, the first layer and the second layer are arranged in order.
0. 26. A semiconductor integrated circuit as set forth in claim 24, wherein the gate layer is under the first layer, the gate layer is under the second layer.
0. 27. A semiconductor integrated circuit as set forth in claim 23, further comprising:
a transistor in the multi-height standard cell, the wiring is connected to a source or drain region of the transistor.
0. 28. A semiconductor integrated circuit as set forth in claim 23, wherein the wiring crosses the one of the second voltage lines at an intersection point, the one of the second voltage lines is physically isolated from the wiring at the intersection point.
0. 29. A semiconductor integrated circuit as set forth in claim 9, wherein a metal layer includes the first voltage lines and the second voltage lines.
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More than one reissue application has been filed. The present application is a continuation reissue application of parent reissue application Ser. No. 14/600,627, filed Jan. 20, 2015, which is a reissue application of application Ser. No. 12/805,158, now U.S. Pat. No. 8,357,955, issued Jan. 22, 2013. The present invention contains subject matter related Japanese Patent Application JP 2009-198547 filed in the Japan Patent Office on Aug. 28, 2009, the entire contents of which being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a desired circuit formed by combining and laying out a plurality of standard cells each having transistors and gate electrodes and connecting the cells together.
2. Description of the Related Art
In a common standard cell, at least one of the sizes thereof in the directions orthogonal to each other (so-called vertical and horizontal directions) is standardized to a few types or, for example, to three types. The so-called vertical size is referred to as the height of the standard cell. This height is standardized to three types or so. Here, in order to avoid confusion between this cell size (height) and its structural height perpendicular to the semiconductor substrate, the cell size will not be called the “height.” Instead, this size will be referred to as the “standard cell length” for the sake of convenience.
Even when a few standard lengths of the standard cell may be used in an LSI (Large Scale Integration) as a whole, the same standard length is used when viewed locally as in the same circuit block to ensure efficient layout of cells.
Therefore, various types of standard cells with the same standard cell length are made available and registered in a library. In general, standard cell patterns such as internal wiring patterns are limited in layout space along the standard cell length.
In contrast, the standard cell size in the direction orthogonal to the common cell length (so-called horizontal direction) is available in a variety of lengths according to the scale of the gate circuit. The cell size in the direction orthogonal to the common cell length will be hereinafter referred to as the “arbitrary cell length” for the sake of convenience.
The inverter is normally the most basic building block of logic circuits achieved by the standard cell system. The inverter is formed by connecting NMOS and PMOS transistors in series between VDD and VSS lines so that the gates are shared. In the most basic standard cell used for logic circuits, the distance between the center of the VDD line and that of the VSS line is the standard cell length, and the direction along the VDD and VSS lines is the arbitrary cell length direction when the VDD and VSS lines are arranged alternately and parallel to each other. This most basic standard cell is designed by increasing or reducing the size of the arbitrary cell length as appropriate according to the scale of the standard cell circuit. Such a basic standard cell has a standard cell length of a CMOS pair that is appropriate to the sum of the lengths of NMOS and PMOS gates. Such a standard cell has a height appropriate to that of a single CMOS pair. Therefore, this cell will be hereinafter referred to as a “single height cell.”
The layout of standard cells each having a standard cell length of a CMOS pair is described, for example, in Japanese Patent Laid-Open No. Hei 10-173055.
There would be no problems if the circuit to be achieved with a standard cell was a basic logic gate circuit such as an inverter or a NAND circuit. However, there are cases in which the single height configuration is not suitable depending on the circuit scale.
We assume, for example, that there is a standard cell configured in such a manner that the gates of a number of CMOS pairs must be driven in phase.
In this standard cell, the PMOS and NMOS transistor gates in each CMOS pair are connected by a gate line made, for example, of polysilicon. However, several gate lines must be further shorted together. Therefore, the gate lines are connected together by upper layer wirings (normally, metal wirings in the first layer). However, a number of other internal wirings are also required in the standard cell to connect transistor gates to the sources or drains of other transistors. As a result, it may be impossible to secure a space to connect the gates together with the upper layer wirings.
Even if a space is secured, it may be necessary to design wirings that are bent in a complex manner, thus resulting in reduced workability for design and mask preparation and leading to higher cost.
If a space cannot be secured, there is no alternative but to increase the standard cell length in the standard cell specification to provide more leeway or use the wirings in a higher layer.
However, increasing the standard cell length leads to waste in areas other than the CMOS pairs of the cell and small-scale basic circuitry such as inverters. Moreover, using the wirings in a higher layer (e.g., wirings in the second metal wiring layer) clutters the space where other wirings are supposed to be formed in the second metal wiring layer.
It is desirable to provide a semiconductor integrated circuit having a cell layout unlikely to produce wasted space and advantageous in terms of cost when the semiconductor integrated circuit contains standard cells for achieving a circuit adapted to drive a plurality of complementary transistor pairs (e.g., CMOS pairs) in phase.
In a semiconductor integrated circuit according to an embodiment of the present invention, a desired circuit is formed by combining and laying out a plurality of standard cells and connecting the cells together. The cell length, i.e., as the gap between a pair of opposed sides, of the standard cells is standardized. These standard cells include a complementary in-phase driven standard cell. Each of the complementary in-phase driven standard cell includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together. N (≥2) pairs of all the complementary transistor pairs are driven in phase. Further, the size of the standardized cell length of a complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N≥M≥2) times the basic cell length which is appropriate to the single complementary transistor pair. In a complementary in-phase driven standard cell, the common gate electrodes of at least M pairs of the N complementary transistor pairs to be driven in phase are arranged linearly in the direction of the M-fold cell length.
In the embodiment of the present invention, single height cells or standard cells having the basic cell length and multi-height cells or the complementary in-phase driven standard cells having the M-fold cell length, are preferably arranged adjacent to each other to form the desired circuit. Further, when arranged adjacent to the single height cells, the multi-height cells preferably have a power line arrangement structure that allows for power lines to be shared.
In the above configuration of the semiconductor integrated circuit according to the embodiment of the present invention, if electrical shorting is required for in-phase driving, the gate electrodes of a plurality of complementary transistor pairs to be driven in phase are formed integrally with a common gate line itself. This provides a reduced number of internal wirings required to short the gate lines, thus eliminating wasted space. Further, this eliminates the need to form internal wirings in complex shapes.
The above preferable configuration does not impede the advantages of the standard cell layout system because the multi-height cells preferably have a power line sharing structure with the adjacent single height cells. At this time, the single height cells need only have a required minimum basic cell length suitable for a small-scale circuit. The standard cell length of the multi-height cell is a plurality of times the basic cell length thereof. This makes it possible to secure a power line sharing structure with other surrounding cells even if the standard cell length of the multi-height cell is increased. Further, in this case, the single height cell has a required minimum basic cell length suitable for a small-scale circuit, thus eliminating wasted space.
The present invention provides a semiconductor integrated circuit having a cell layout unlikely to produce wasted space and advantageous in terms of cost when the semiconductor integrated circuit contains standard cells for achieving a circuit adapted to drive a plurality of complementary transistor pairs (e.g., CMOS pairs) in phase.
A description will be given below of embodiments of the present invention with reference to the accompanying drawings by taking, as main examples, double height and triple height circuit cells.
1. First embodiment: Embodiment in which the double height cell to which the present invention is applied is shown by four application examples (circuit examples). In the first and second application examples, the effect obtained by the application of the present invention will be described by using comparative examples 1 and 2.
2. Second embodiment: Embodiment of a triple height cell to which the present invention is applied.
3. Third embodiment: Embodiment of an L-shaped cell (double height cell having the same functionality as a triple height cell) to which the present invention is applied.
4. Modification examples: Two modification examples relating to a substrate contact will be described.
In
Although being a schematic plan view of the semiconductor integrated circuit with a focus on the cell layout,
In a semiconductor integrated circuit 1 shown in
The standard cell design system is used in the design process of ASIC (Application Specific Integrated Circuit) and ASSP (Application Specific Standard Product). ASIC is an IC developed and manufactured to meet a specific application requirement of each customer. ASSP is an IC designed and developed as a general-purpose part for a plurality of customers.
A description will be given below of the size of the standard cell SC.
In the standard cell SC, the cell length in the direction along one of two sides that are orthogonal to each other is commonly standardized. This cell length direction will be hereinafter referred to as the “standard cell length direction.” There may not be only one, but a few sizes or, for example, three sizes, in the standard cell length direction (standard cell lengths) in an entire IC. It should be noted, however, that there has been, up until today, one unified standard cell length, when viewed locally, as in a single circuit block or a circuit adapted to achieve a desired function. One of the major characteristics of the embodiments of the present invention is that there are a plurality of standard cell lengths in a local circuit such as a single circuit block or a circuit adapted to achieve a desired function.
In relation to this characteristic, common single height standard cells SHSC and multi-height standard cells MHSC, both serving as the standard cells SC, are mixed in the example shown in
The cell size can be determined at will in the direction orthogonal to the standard cell length direction. Although the cell size may be determined at will, it is common that there are fixed discrete sizes that can be used (specified by the grid number) for reasons of design efficiency or to meet the demand for consistency. The direction orthogonal to the standard cell length direction will be hereinafter referred to as the “arbitrary cell length direction.”
In a circuit block as shown in
Further, the double height standard cell WHSC includes a type denoted by reference numeral WHSC1. The double height standard cell WHSC1 has the two VSS lines that are disposed, one along each of the two short sides, in the standard cell length direction, with the VDD line passing through the same cell WHSC1 at the center between the two VSS lines. Further, the double height standard cell WHSC includes a type denoted by reference numeral WHSC2. In contrast to the double height standard cell WHSC1, the double height standard cell WHSC2 has the two VDD lines that are disposed, one along each of the two short sides, with the VSS line passing through the same cell WHSC2 at the center between the two VDD lines. Although only one of these two types may be used, the two types are mixed here from the viewpoint of layout efficiency.
[Single Height Layout]
Next, the reason will be clarified why the single height standard cells SHSC and multi-height standard cells MHSC are mixed in the same circuit block by stating the disadvantages of the major techniques adapted to design a semiconductor integrated circuit with only single height cells.
Each of these single height standard cells SHSC_1, SHSC_2 and SHSC_3 has two doped regions, namely, a P-type doped region 13P and an N-type doped region 13N, arranged parallel to each other between the VDD and VSS lines. The P-type doped region 13P serves as the sources or drains of PMOS transistors. The N-type doped region 13N serves as the sources or drains of NMOS transistors. The reason for this is that the inverter is the basic building block of CMOS logic circuits. Polysilicon gate electrodes 20A and 20B forming an inverter input are arranged linearly so as to be orthogonal to a rectangular region including a P-type doped region 13P (hereinafter denoted by the same reference numeral as the P-type doped region 13P and referred to as the “PMOS active region 13P”). The polysilicon gate electrodes 20A and 20B are also arranged linearly so as to be orthogonal to a rectangular region including an N-type doped region 13N (hereinafter denoted by the same reference numeral as the N-type doped region 13N and referred to as the “NMOS active region 13N”) (
In such a standard cell configuration, vertically long common gate electrodes of the complementary transistor pair (hereinafter the CMOS gate lines) are arranged side by side. This leads to an increased number of internal wirings adapted to connect CMOS gate lines or a CMOS gate line and other node (e.g., transistor source and drain). Moreover, because such a number of internal wirings must be provided in a limited space, the wiring pattern is inevitably complex. This leads to many vertices and bends in the metal and polysilicon layouts, thus resulting in a complex shape.
In leading-edge processes, the more complex the pattern shape is, the more design rule restrictions are imposed. Further, a complex pattern shape leads to a long time required to perform optical proximity correction (OPC) in the mask preparation or is disadvantageous from the viewpoint of design for manufacturing (DFM). Here, the term “DFM (design for manufacturing)” refers to a technique adapted to resolve the LSI manufacturing problems at the design stage. In the cell layout, a simple shape provides a device less susceptible to variations at the time of manufacture. Therefore, this aspect is important.
Further, difficulty in performing OPC, for example, may lead to a reduced yield of physical device.
The viewpoints described above constitute the first disadvantage of designing a logic circuit with only the single height standard cells SHSC.
A high likelihood of producing wasted space is the second disadvantage.
Standard cells used, for example, for a clock tree may be laid out with a changed size ratio between the PMOS and NMOS to ensure that the clock delay is the same. For example, a standard cell (SHSC_2:
In this case, enlarging the PMOS active region 13P horizontally leads to a vacancy in the NMOS transistor forming region as shown in
The embodiments of the present invention propose a complementary transistor pair (e.g., CMOS pair) standard cell configuration that resolves the above two disadvantages. The present invention is applied to a complementary in-phase driven standard cell of all the types of complementary transistor pair standard cells.
Three layout configuration examples of the complementary in-phase driven double height standard cells WHSC to which the present invention is applied will be shown below together with circuit examples.
It should be noted that the gates of the CMOS pairs that are supplied, for example, with the same input in
The carry-out (CO) section includes a NAND circuit and an inverter. The NAND circuit includes two PMOS transistors P1 and P2 and two NMOS transistors N1 and N2. The inverter includes a PMOS transistor P3 and an NMOS transistor N3. The NAND circuit and inverter are connected by a wiring denoted by reference numeral 31 (internal wiring 31) where an inverted carry-out bit (NCO) appears. The P1-N1 CMOS pair is supplied with the first input bit A1. The P2-N2 CMOS pair is supplied with the second input bit A2.
The single-bit addition (Sum) section includes four PMOS transistors P4 to P7 and four NMOS transistors N4 to N7 and has the inverted carry-out bit (NCO) and the first and second input bits (A1 and A2) as its inputs. Although performing a single bit addition, the same section produces a single bit output. Therefore, the same section performs a half addition operation adapted to produce a “0” output with the help of the inverted carry-out bit (NCO) that is “0 (e.g., low level)” when both the first and second input bits A1 and A2 are “1 (e.g., high level).”
In such a configuration, when the two input bits (A1 and A2) are both low, the PMOS transistors P1 and P2 are ON. Therefore, the NCO is high, and the CO is low. As a result, no carry is generated. On the other hand, both the PMOS transistors P5 and P6 are ON. This pulls an inverted half addition bit (NS) up to high level. The NS is the potential of an internal connection line 33 forming the input node of the inverter at the final stage. As a result, an internal connection line 34 outputs a low level as the half addition bit (S).
When the two input bits (A1 and A2) are high and low, respectively, the PMOS transistor P1 is OFF but the PMOS transistor P2 is ON. Similarly, therefore, the NCO is high, and the CO is low. As a result, no carry is generated. On the other hand, both the NMOS transistors N4 and N5 are ON. This pulls the inverted half addition bit (NS) down to low level. Therefore, a high level is output as the half addition bit (S).
When the two input bits (A1 and A2) are low and high, respectively, the PMOS transistor P2 is OFF but the PMOS transistor P1 is ON. Similarly, therefore, the NCO is high, and the CO is low. As a result, no carry is generated. On the other hand, both the NMOS transistors N4 and N5 are ON. This pulls the inverted half addition bit (NS) down to low level. Therefore, a high level is output as the half addition bit (S).
When the two input bits (A1 and A2) are both high, the NMOS transistors N1 and N2 are ON, which stands in contrast to the above three cases. Therefore, the NCO is low, and the CO is high. As a result, a carry is generated. On the other hand, because the NCO is low, the PMOS transistor P4 is ON although the PMOS transistors P5 and P6, provided in parallel with the PMOS transistor P4, are OFF. This pulls the inverted half addition bit (NS) up to high level. Therefore, a low level is output as the half addition bit (S).
The standard cell illustrated in
In this double height standard cell WHSC1, a VDD line 30D extends in the arbitrary cell length direction (horizontal direction) at the center of the standard cell length direction (vertical direction). Further, two VSS lines, i.e., VSS lines 30S1 and 30S2, are disposed. The VSS line 30S1 is arranged along the center of the width of one of the short sides of the horizontal outer frame of the cell. The VSS line 30S2 is arranged along the center of the width of the other of the short sides thereof. The VSS lines 30S1 and 30S2 are arranged parallel to each other, and also parallel to the VDD line 30D. The VDD line 30D and VSS lines 30S1 and 30S2 are formed by patterning the first wiring layer (1M).
The circuit (CO section) adapted to generate the carry-out bit (CO bit) is provided on the lower half of the cell in such a manner as to have the VSS line 30S1 and share the VDD line 30D. On the other hand, the circuit (Sum section) adapted to generate the half addition bit (S) is provided on the upper half of the cell in such a manner as to have the VSS line 30S2 and share the VDD line 30D.
Two active regions of the same conductivity type, i.e., PMOS active regions 11P and 12P, are arranged line-symmetrically with respect to the center line of the power line (VDD line 30D) passing through the cell. Further, an NMOS active region 11N is arranged between the PMOS active region 11P and VSS line 30S1, and an NMOS active region 12N between the PMOS active region 12P and VSS line 30S2.
Surrounded by an element isolation insulating layer 10, these four active regions are isolated from one another and arranged to be horizontally long in shape and parallel to the power line.
It should be noted that the CO section has six transistors whereas the Sum section has eight. Therefore, the PMOS and NMOS active regions 12P and 12N are longer in shape than the NMOS and PMOS active regions 11N and 11P.
Three common gate electrodes 21 to 23 are arranged linearly in such a manner as to penetrate the four active regions vertically (in the standard cell length direction).
The common gate electrode 21 serves as a common gate of the transistors (P1, N1, P5 and N5) adapted to receive the first input bit A1 shown in
The common gate electrode 22 serves as a common gate of the transistors (P2, N2, P6 and N6) adapted to receive the second input bit A2 shown in
On the other hand, a common gate electrode 24 for the remaining two transistors (P7 and N7) is shorter than the other three and penetrates the PMOS and NMOS active regions 12P and 12N because the two transistors must receive the inverted half addition bit (NS) in the Sum section.
Internal wirings 31 to 35 shown in
[Characteristics of the Layout to Which the Present Invention is Applied]
A first characteristic of the layout is that the connection rule with the single layout power line arrangement is maintained. That is, the relationship between the VSS line 30S1 and VDD line 30D and that between the VSS line 30S2 and VDD line 30D are appropriate to the standard cell length of the single height standard cell SHSC (
A second characteristic of the layout is that the gate electrodes of the plurality of or M (M=2 in this case) complementary transistor pairs to be driven in phase are arranged linearly as common gate electrodes.
This commonization of gate electrodes contributes to a reduced number of internal wirings, thus providing leeway in the layout of other internal wirings. When there is leeway in the layout of internal wirings, wirings may be laid out without forming a complex shape, possibly contributing to improved yield and ease of manufacturing. Further, there is no need to connect the gates together using the upper layer wirings, thus providing leeway in the layout of the upper layer wirings. In the case of this circuit example in particular, there is no need to connect the gates together in the higher second wiring layer, as in the comparative examples which will be described layer, thus ensuring effective use of multi-wiring resources and providing reduced cost.
A third characteristic of the layout is that active regions of the same conductivity type (11N and 12N) are arranged line-symmetrically with respect to (M−1) power lines passing midway therebetween, or the one VDD line 30D because M=2.
A fourth characteristic of the layout is that all the gate electrodes overlapping the portion of the element isolation insulating layer 10 located within the width of separation between the two active regions are the common gate electrodes 21 to 23 of the complementary transistor pairs to be drive in phase. In contrast, the common gate electrode 24 is not a common electrode of a plurality of complementary transistor pairs, but is instead a common electrode of NMOS and PMOS transistors in a single complementary transistor pair. Such an electrode does not overlap any portion of the element isolation insulating layer 10 located within the width of separation between the two active regions (instead overlaps the portion of the same layer 10 located outside the width of separation).
The fourth characteristic is obvious when we consider the case in which this characteristic is not present. That is, we assume that two gate electrodes, one extending from up to down and another extending from down to up into the width of separation between the two active regions, are separated within the same width. In this case, a space for separating the electrodes is required in addition to the alignment tolerance required to reliably align the gate electrodes with the active regions in consideration of the misalignment of the photomask. As a result, there are limits to reducing the space between the active regions.
In the case of the layout shown in
The above characteristics are also available when triple or higher standard cells which will be described later are used.
A description will be given next of comparative examples to which the present invention is not applied to further clarify the effects of the above characteristics.
The circuits shown in
In
Further, while the single common gate electrode 21 is linearly arranged in
Because the two common gate lines are arranged separately, the pairs of gate electrodes shown by bi-directional arrows in
A first approach to making these connections would be to achieve horizontal connections using the common gate electrodes themselves (gate polysilicon layer).
In order to short the common gate electrodes 21A and 21B together, it is necessary, for example, to expand the space between the PMOS active region 11P or 12P and VDD line 30D in the standard cell length direction. Further, in order to short the common gate electrodes 22A and 22B together, it is necessary, for example, to expand the space between the NMOS active region 11N or 12N and VSS line 30S in the standard cell length direction. Even in this case, the common gate electrodes 23A and 23B cannot be shorted together. As a result, it is inevitable that this remaining pair of common gate electrodes should be shorted together using the first wiring layer (1M).
With the first approach, the cell length must be expanded in the standard cell length direction so as to secure a space for arranging two common gate electrodes. However, this gives rise to significant wasted space in the standard cell array as a whole, which makes this approach unacceptable.
For this reason, a second approach would be to use the second wiring layer (2M).
If the branches for the active region contacts of the power lines (30D and 30S) and internal wirings (31 to 33) are moved backward in
On the other hand, the connections between the first and second input bits A1 and A2 and half addition bit (S) and the unshown adjacent cell are not shown in
Even in such a case, the layout shown in
As described above, both the first and second approaches are disadvantageous in that they are highly likely to result in significantly increased cost. The layout shown in
It should be noted that the CO section shown in
Further, as a result of an embodiment of the application of the present invention, the wiring pattern layouts for the first wiring layer (1M) and polysilicon are simpler in shape thanks to fewer vertices and bends. The application of the present invention is advantageous from the viewpoint of design for manufacturing (DFM) in that it contributes to reduced man-hours for mask preparation including the OPC process and design, thus providing further reduced manufacturing cost and improved yield.
A clock buffer cell is a cell including an even number of stages of cascaded inverters. This type of cell is designed so that the clock output from the cell has the same duty ratio to the extent possible. Therefore, a clock buffer is characterized in including larger-than-normal PMOS transistors or smaller-than-normal NMOS transistors.
A specific clock buffer circuit includes two cascaded inverters INV1 and INV2 shown in
In this layout diagram, a VDD line 31D is arranged at the center of the standard cell length and extends in the arbitrary cell length direction. Two VSS lines 31S1 and 31S2 are arranged parallel to the VDD line 31D and along the center of the width of one of the short sides on both sides along the standard cell length. These three power lines are formed by using the second wiring layer (2M).
A specific description of the circuit configuration in the cell and the connections is omitted because the circuit itself is simple. Here, the element isolation insulating layer 10, PMOS active regions 11P and 12P, and NMOS active regions 11N and 12N are arranged in the same manner as in the first application example as like components as those in the first application example denoted by like reference numerals. Contact with the active regions is achieved by providing branches of the power lines in the first application example. Here, however, contact with the active regions is achieved by providing power connection lines 39D1, 39D2, 39S1 and 39S2 that are formed with the first wiring layer (1M).
Internal wirings 36 and 37 are formed with the first wiring layer (1M) to connect the inverters INV1 and INV2 together as shown in
Common gate electrodes 25 and 26 are arranged parallel to each other and extend in the standard cell length direction as with the common gate electrodes 21 to 23 (
In this layout, PMOS transistors can be formed as far as in the region close to the VDD line which cannot be used in an ordinary single height cell, as with the layout in
The cell shown in
In the horizontal layout shown in
In other words, the cell layouts shown in
As compared to the clock buffer shown in
The comparison of the cells shown in
It should be noted that the cell shown in
The circuit shown in
In the clock buffer with branched outputs, the output node is separated into the internal wirings 38A and 38B. As a result, there is no need for the internal wiring of the output node to intersect the VDD line 31D at the center. This makes it possible to form the VDD line 31D (and VSS lines 31S1 and 31S2) with the first wiring layer (1M) as illustrated in
The second embodiment is a modification of the circuits shown in
If, for example, the double height portion of the upper two stages in
It should be noted that the equivalent circuit achieved by the layout diagram shown in
In the additional portion, reference numeral 10P denotes a PMOS active region, and reference numeral 10N an NMOS active region. Further, a VSS line denoted by reference numeral 31D0 is added. The VDD lines 31D0 and 31D1 are provided respectively with the power connection lines 39S2 and 39D2 that are formed with the first wiring layer (1M). The same lines 39S2 and 39D2 are branch lines adapted to connect the NMOS active region 10N and PMOS active region 10P respectively to the power lines.
It should be noted that the internal wiring 36+37 is disposed to extend as long as the length of three basic cells. However, the internal wirings 36 and 37 can be similarly connected together to extend as long as the length of two standard cells in
Other components of the cell shown in
It should be noted that the corrections made by changing a double height cell to a triple height cell can be applied to multi-height cells equal to or greater than triple height cell using the same technique.
Still further, the advantages of a double height cell are similarly inherited by multi-height cells equal to or greater than triple height cell.
Multi-height cells equal to or greater than triple height cell can be used to produce a non-rectangular cell that is bent in the shape of L as a whole.
In a layout example according to the standard cell system as shown in
The third embodiment is designed to meet such a need. The layout as shown in
In
In the present embodiment, the functions of a triple height cell can be achieved with the standard cell height of a double height cell. This allows a greater degree of freedom in the layout, making it possible to choose between the layouts shown in
It should be noted that, including this third embodiment, the number of complementary transistor pairs to be driven in phase or N need not necessarily agree with the number of complementary transistor pairs or M that is appropriate to the standard cell length of multi-height layout. That is, a multi-height layout is possible that satisfies the relationship N≥M≥2.
Modification examples of substrate contacts will be shown next.
In the first to third embodiments, substrate contacts are not shown in the layout diagrams.
Basically, in order to dispose gate polysilicon layer wirings (common gate lines) in the presence of substrate contacts SCH, the same contacts SCH and doped regions are removed, as appropriate only where the gate polysilicon layers are disposed. Here, the substrate contacts SCH are also referred to as taps. More specifically, an N-type doped region 14N that is higher in concentration is formed on the surface of the tap region where the PMOS active regions 12P and 11P and the element isolation insulating layer 10 are connected together in the deep side of the substrate. The substrate contacts SCH serve as connection plugs between the N-type doped region 14N and first wiring layer (1M). This allows for the channel forming regions of the PMOS transistors formed in the PMOS active regions 11P and 12P to be supplied with VDD voltage from the VDD line 30D. Further, the source region of the PMOS transistors is supplied with power by the branch from the VDD line 30D and the contacts connected to the branch.
On the other hand, many substrate contacts SCH are provided in the VSS lines 30S1 and 30S2 for the same purpose as above. The substrate contacts SCH in these areas are provided to connect the NMOS active region 11N or 12N to the VSS voltage. Strictly speaking, the channel forming region formed in the NMOS active region 11N or 12N or the substrate is connected to the VSS voltage. That is, a P-type doped region 14P that is higher in concentration is formed on the surface of the tap region where the NMOS active region 12N or 11N and the element isolation insulating layer 10 are connected together in the deep side of the substrate. The substrate contacts SCH serve as connection plugs between the P-type doped region 14P and first wiring layer (1M). This allows for the channel forming regions of the NMOS transistors formed in the NMOS active regions 11N and 12N to be supplied with VSS voltage. Further, the source region of the NMOS transistors is supplied with power by the branch from the VSS line 30S1 or 30S2 and the contacts connected to the branch.
Alternatively, a tapless circuit cell having none of the substrate contacts SCH (referred to as the taps) as shown in
The tap cell 2 is laid out as appropriate in the gap formed as appropriate in the arbitrary cell direction shown in
The first to third embodiments described above provide the following advantages.
Firstly, the number of horizontal (arbitrary cell length direction) metal wirings can be reduced, thus allowing for effective use of the metal wiring resources.
Secondly, increased wiring resources eliminate the need to use metal in the upper layers.
Thirdly, polysilicon gate wirings (common gate lines) are disposed where they would not exist if the present invention was not applied, thus eliminating the horizontal polysilicon gate wirings and providing increased wiring resources.
Fourthly, the polysilicon gate wirings are simpler in shape.
Fifthly, thanks to the polysilicon gate wirings that are simpler in shape, there is more layout area in the diffusion regions (active regions) or the layout is easier to do.
Sixthly, since the metal and polysilicon wirings and diffusion regions are easier to lay out, the geometries are no longer complex, which is effective from the viewpoint of design for manufacturing (DFM).
Seventhly, where a VDD line is shared in a multi-height cell, the PMOS size can be increased, thus providing improved transistor mounting area efficiency.
Similarly, where a VSS line is shared in a multi-height cell, the NMOS size can be increased, thus providing improved transistor mounting area efficiency also in this respect.
The above advantages are achieved by elaborately taking advantage of the fact that, in a CMOS circuit, a signal is commonly connected to the gate terminals of the paired PMOS and NMOS transistors, In the case of an inverter, for example, a signal is connected to the gate terminals of the CMOS pair. In the first to third embodiments, when the cell input signals and the intracell signals are connected to the gate terminals of a plurality of CMOS pairs, a multi-height cell is intentionally used to lay out these CMOS pairs vertically.
The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2009-198547 filed in the Japan Patent Office on Aug. 28, 2009, the entire content of which is hereby incorporated by reference.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factor in so far as they are within the scope of the appended claims or the equivalents thereof.
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